THCS133_Rev.2.00_E
THCS133
I/OSpreader
General Description
Features
The THCS133 provides a function to serialize
multiple parallel signals into single-ended serial
line at least or to deserialize the data stream over
single-ended serial line or single differential pair
into multiple parallel signals.
This small number of transmission line simplifies
system configuration and reduces system cost
including cable width, connector size and pins
and PCB layout area.
The THCS133 is offered in 8bit parallel IOs as
host MPU interface.
It can transfer 8bit independent parallel signals to
remote side by only 1-line or 1-pair cable.
Transmitter or receiver function can be selected
by pin.
- No External Clock Required.
-8bit Parallel IOs to MPU.
- Single-ended/Differential Mode (noise tolerant)
Selectable
- AC Coupling Supported with Differential Mode
- Transmission Status Error Indicator Supported
(Line Cut Detection and Packet Error
Detection)
- Digital Filter Function
- Power supply : 3.0 to 5.5V
- DIP 20-pin Package
- EU RoHS Compliant
Block Diagram
THCS133
OSC
RXEN
(Tx/Rx select)
DATA<7:0>
(Parallel I/O)
Internal Condition : Pull-down
IOP
ION
SER
＆
DES
I/O
MUX
CTL0
CTL1
(I/O control)
(Serial I/O)
RSTN
(Reset input)
FAULTN
(Error flag output)
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SIG
(Single-ended / differential select)
FILT (Digital filter select)
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Pin Diagram
GND
1
20
VDD
TEST
2
19
SIG
FILT
3
18
IOP
RXEN
4
17
ION
FAULTN
5
16
DATA7
RSTN
6
15
DATA6
DATA0
7
14
DATA5
DATA1
8
13
DATA4
DATA2
9
12
CTL1
DATA3
10
11
CTL0
Pin Description
Pin No.
Pin Name
Internal Condition
1
2
GND
TEST
-
Input, Pull-down
3
FILT
Input, Pull-down
4
RXEN
Input, Pull-down
5
FAULTN
Output, Open-drain
6
RSTN
Input, Pull-down
7-10
13-16
DATA0-7
Input/Output,
Pull-down
11
CTL0
Input, Pull-down
12
CTL1
Input, Pull-down
17
18
ION
IOP
Input/Output
Input/Output
19
SIG
Input, Pull-down
20
VDD
-
Description
Ground
Test pin. Please connect to GND
Digital filter enable pin
Low : OFF High : ON
Receiver mode enable
Transmitter status error indicator
Low : Abnormal operation detected
Reset input
Low : Reset High : Normal operation
Parallel data I/O bit : 0-7
Lower 8bit input latch (Transmitter mode）
Lower 8bit Output enable (Receiver mode)
Upper 8bit input latch (Transmitter mode）
Upper 8bit Output enable (Receiver mode)
Serial data differential mode(-) I/O
Serial data CMOS/differential mode(+) I/O
Serial data I/O mode select
Low : CMOS High : Differential
Power Supply
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Absolute Maximum Rating
Parameter
Condition
Min
Typ
Max
Unit
-
-0.4
-
6
V
-
-0.4
-
VDD+0.4
V
-
-0.4
-
VDD+0.4
V
Ta=25℃
-
-
1
W
Storage Temperature
-
-55
-
150
℃
Junction Temperature
-
-
-
125
℃
Power Supply Voltage VDD
Digital Input Voltage (DATA0-DATA7,
FILT, RXEN, CTL0, CTL1, RSTN, SIG)
Open-drain Output Pin(FAULTN)
Allowable Power Dissipation
Recommended Operating Condition
Parameter
Condition
Min
Typ
Max
Unit
Power Supply Voltage VDD
-
3.0
-
5.5
V
Ambient Operating Temperature
-
-40
-
85
℃
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Electrical Characteristics DC Characteristics （at VDD＝5.0V, Ta=25℃, unless otherwise noted）
Parameter
Condition
Min
Typ
Max
Unit
-
20
30
mA
Transmitter mode
Power Supply Current
LVDS mode
(Note)
UVLO Threshold Voltage (VDD Rising)
-
-
2.6
2.8
V
UVLO Hysteresis Voltage
-
-
0.15
-
V
Digital Input High-level Voltage (VIH)
-
0.7VDD
-
-
V
Digital Input Low level Voltage (VIL)
-
-
-
0.3VDD
V
Digital Input Leakage Current 1
Except CTL1
-
-
+/-50
uA
Digital Input Leakage Current 2
CTL1
-
-
+/-150
uA
Digital Input Hysteresis Voltage
VDD=3.0V
-
0.11VDD
-
V
Tj=125℃
VDD-0.6
-
-
V
Digital Output High-level Voltage
(VOH)
Iout=-4mA
Digital Output High-level ON Resistance
VDD=3.3V
-
56
-
(RonH)
VDD=5.0V
-
46
-
-
-
0.4
V
VDD=3.0V
Digital Output Low-level Voltage (VOL)
Tj=125℃
Iout=4mA
Digital Output Low-level ON Resistance
VDD=3.3V
-
44
-
(RonL)
VDD=5.0V
-
36
-
-
-
0.4
V
Open Drain Output Low-level Voltage
Iout=1mA
FAULTN
LVDS Differential Input Voltage (VID)
IOP/ION
200
-
-
mV
LVDS Input Leakage Current
IOP/ION
-
-
+/-50
uA
350
-
-
mV
-
600
-
mV
-
-
750
mV
1.0
1.25
1.4
V
VDD=3.0V
IOP/ION
LVDS Differential Output Voltage
(VOD)
VDD=5.0V
IOP/ION
VDD=5.5V
IOP/ION
LVDS Output Common-mode Voltage
(VOC)
Pull-down Resistance
IOP/ION
250
k
Note: The power supply current is maximum in this condition.
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LVDS Input Output Differential Voltage
ION
ION
VOC
VID
VOD
IOP
IOP
Electrical Characteristics AC Characteristics (Reset Section)
Mark
Parameter
Time from Reset (RSTN) Release to
tRST
Valid Input
tWRST
Reset (RSTN) Low Pulse Width
Condition
Min
Typ
-
-
-
-
5
-
Max
100
(Note)
-
Unit
us
us
Note : In AC coupling, tRST changes with the capacity to connect.
Timing Chart (Reset Section)
Rese t signal （ RSTN ）
tWRST
Reset input (RSTN)
tRST
Input dta (DATA)
Valid data
Output data （DATA)
Pull-down
Output Low
Valid data output
In case Output is controlled by signal of output enable (CTL0,
CTL1), a pull-down state is continued until it sets signal of
output enable to LOW.
Electrical Characteristics AC Characteristics (Serial Communication)
Mark
Condition
Min
Typ
Max
Unit
Serializer Input Sampling Frequency
-
50
-
-
kHz
tPS
Time of Serializer Transmission
-
-
-
18
us
tSP
Deserializer Output Renewal Time
-
-
-
2
us
Serial Data Transmission Rate
-
-
2.5
-
MHz
fPSPL
fSTR
Item
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Timing Chart
Transmitter Mode
Internal Register
Input (DATA[15:0])
Parallel Input[15:0]
1/fPSPL
Internal Sampling Clock
tPS
Serial Data Output
Serial Output
Serial Output
Serial Input
Serial Input
Receiver Mode
Serial Data Input
Internal Register
Output (DATA[15:0])
Parallel Output[15:0]
tSP
Internal sampling clock and CTL signals are asynchronous.
Electrical Characteristics AC Characteristics (Latch Enable, Output Enable)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tWLE
tSULE
Latch Enable Pulse Width
Latch Enable Rise Edge Setup Time
-
130
133
-
-
ns
ns
tHLE
Latch Enable Rise Edge Hold Time
-
20
-
-
ns
tCLLE1
Latch Enable Clearance1
-
100
-
-
ns
tCLLE2
Latch Enable Clearance2
-
20
-
-
us
tWOE
Output Enable Pulse Width
-
50
-
-
ns
tCLOE
Output Enable Clearance
-
50
-
-
ns
-
50
ns
tPZO
Output Enable Delay Time
CL=25pF
-
tPOZ
Output Disable Delay Time
CL=25pF
ns
38
Note: CL=Capacity Load
Timing Chart (Latch Enable, Output Enable)
8bit Input + Latch Enable
Upper Latch Enable
（CTL1）
Lower Latch Enable
（CTL0）
Data Input
(DATA[7:0])
tCLLE2
tWLE
tCLLE1
tSULE
tHLE
Upper 8bit data
Lower 8bit data
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Upper 8bit data
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8bit Output + Output Enable
Upper Output Enable
（CTL1）
Lower Output Enable
（CTL0）
tCLOE
tWOE
tPZO
Data Output
(DATA[7:0])
tPOZ
Upper 8bit data
Lower 8bit data
When receiving new incoming data during CTL0 or CTL1 = Low, output data is updated to this new data.
・Latch Enable, Output Enable Truth Table
Transmitter mode
CTL1
CTL0
Latch Enable Input
L
L
↑
H
Upper 8bit input latch
H
↑
Lower 8bit input latch and 16-bit data reception
H
H
Keep data
Lower 8bit data is transmitted by sampling frequency
(8bit through mode)
The rising edge of CTL0 is the trigger for sampling of upper and lower data.
Receiver mode
CTL1
CTL0
Output Enable Input
L
L
L
H
Upper 8bit Output enable
H
L
Lower 8bit Output enable
H
H
Output disable
（DATA pins are pulled down by 250kΩ internally）
Output disable
（DATA pins are pulled down by 250kΩ internally）
・Transmitter or Receiver select
Pin
RXEN
Description
H
Receiver mode (Serial to Parallel)
L
Transmitter mode (Parallel to Serial)
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THCS133_Rev.2.00_E
・Connection Example（16-bit Transmitter and Receiver）
Latch
circuit
DIN[7:0]
Deserializer
Serializer
DOUT[7:0]
Selector
CTL1
CTL0
CTL0
RXEN
RXEN
CTL1
・Connection Example（8bit Transmitter and Receiver）
Latch
circuit
DIN[7:0]
Deserializer
Serializer
Selector
DOUT[7:0]
CTL1
CTL0
CTL0
RXEN
RXEN
CTL1
・Function Setup for Serial I/O Pins
IOP and ION pins are set as 1 lane CMOS I/O or 2-lane LVDS I/O with a SIG pin.
Pin Setup
Function
Description
SIG
IOP
ION
L
CMOS I/O
*
H
Differential mode I/O＋
Differential mode I/O-
CMOS I/O
Differential mode I/O
＊: Please keep pin open (No connection)
・Function of Transmission Status Error Indicator, FAULTN (Receiver mode)
FAULTN is the output pin. When the protocol of received data is not correct or serial data more than
50usec (typ) is not received, FAULTN pin will be changed into low level. The received data is canceled
when a FAULTN pin outputs Low. When normal serial data is received, a FAULTN pin outputs High in
case of pulled up externally.
・Digital Filter Function
When FILT pin is set to high level, the digital filter function is active.
If the receiver matches the 3
sampling frequency content with the deserialized parallel data, it is updated as the correct data.
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Package
Unit: inch (mm)
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always
apply to the customer's design. We are not responsible for possible errors and omissions in this material.
Please note if errors or omissions should be found in this material, we may not be able to correct them
immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third
parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications : audio-video
device, office automation device, communication device, consumer electronics, smartphone, feature
phone, and amusement machine device. This product must not be used
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this
data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than
the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that
the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a
certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged
to have sufficiently redundant or error preventive design applied to the use of the product so as not to
have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary
to support warranty for performance of this product. Except where mandated by applicable law or deemed
necessary by THine based on the user’s request, testing of all functions and performance of the product is
not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of
strategic goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings
or malfunction, if pins of the product are shorted by such as foreign substance. The damageｓ may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
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