4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE IDT7M1024 Integrated Device Technology, Inc. ramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs. The IDT7M1024 module is designed to be used as a standalone 36-bit Dual-Port Static RAM. The IDT7M1024 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is independent of the HIGH and LOW periods of the clock. This allows the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. The data inputs are gated to control on-chip noise in bussed applications. The user must guarantee that the R/W pins are LOW for at least one clock cycle before any write is attempted. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. The IDT7M1024 module is packaged in a 142-lead ceramic FEATURES: • High-density 4K x 36 Synchronous Dual-Port SRAM module • Architecture based on Dual-Port RAM cells — Allows full simultaneous access from both ports • Synchronous operation — 4ns set-up to clock, 1ns hold on all control, data, and address inputs — Data input, address, and control registers — Fast 20ns clock to data out — Self-timed write allows fast write cycle • Clock enable feature • Single 5V (±10%) power supply • Multiple GND pins and decoupling capacitors for maximum noise immunity • Inputs/outputs directly TTL-compatible DESCRIPTION: The IDT7M1024 is a 4K x 36 bit high-speed synchronous Dual-Port Static RAM module constructed on a co-fired ce- FUNCTIONAL BLOCK DIAGRAM L_CLK R_CLK R_CLKENL L_CLKENL L_CEL L_OEL R_CEL R_OEL R_A0 – 11 L_A0 – 11 L_I/O0 – 8 L_ R/W0 IDT7099 4K x 9 R_ R/W0 R_I/O9 – 17 L_I/O9 – 17 L_ R/W1 L_CEH L_OEH L_I/O18 – 26 L_ R/W2 R_I/O0 – 8 IDT7099 4K x 9 IDT7099 4K x 9 L_CLKENH R_ R/W1 R_CEH R_OEH R_I/O18 – 26 R_ R/W2 R_CLKENH L_I/O27 – 35 R_I/O27 – 35 IDT7099 4K x 9 L_ R/W3 R_ R/W3 2809 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. MARCH 1996 DSC-2809/6 7.4 1 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES PGA (Pin Grid Array). All IDT military modules are constructed with semiconductor components manufactured in compliance with the latest revision of MIL-STD-883, Class B making them ideally suited to applications demanding the highest level of performance and reliability. PIN CONFIGURATION 1 2 3 4 5 GND 6 7 8 9 10 11 12 13 L_I/O1 L_I/O0 GND R_I/O0 R_I/O1 GND R_I/O2 R_I/O3 GND L_A1 L_A0 L_CLK R_A0 R_A1 R_A2 R_I/O6 R_I/O5 R_I/O4 GND R_I/O7 VCC R_I/O8 R_A4 R_I/O11 R_I/O10 R_I/O9 A GND L_I/O3 L_I/O2 B L_I/O4 L_I/O5 L_I/O6 C L_I/O8 VCC L_I/O7 D L_I/O9 L_I/O10 L_I/O11 L_A3 E L_I/O12 L_ CE L L_ CE H L_A4 R_A5 R_ CE H R_CE L R_I/O12 F L_I/O13 L_ OE L L_ OE H L_A5 R_A6 R_OE H R_OE L R_I/O13 G GND L_R/ W0 L_R/ W1 H L_I/O14 L_R/ W2 L_R/ W3 J L_I/O15 L_I/O16 L_I/O17 K L_I/O20 L_I/O19 L_I/O18 L L_I/O21 M L_I/O23 N GND VCC L_A2 GND L_CLKEN L L_CLKEN H R_CLK GND R_CLKEN H R_CLKEN L GND R_A3 GND R_R/ W1 R_R/ W0 GND L_A6 R_A7 R_R/ W3 R_R/ W2 R_I/O14 L_A7 R_A8 R_I/O17 R_I/O16 R_I/O15 GND R_I/O18 R_I/O19 R_I/O20 GND GND L_A10 L_A11 GND R_A11 R_A10 L_I/O22 L_A8 L_A9 L_I/O31 R_I/O35 R_I/O34 R_I/O30 R_A9 R_I/O22 VCC R_I/O21 L_I/O24 L_I/O25 L_I/O29 L_I/O30 L_I/O32 L_I/O35 R_I/O33 R_I/O31 R_I/O29 R_I/O25 R_I/O24 R_I/O23 L_I/O26 L_I/O27 L_I/O28 GND L_I/O33 L_I/O34 R_I/O32 GND R_I/O28 R_I/O27 R_I/O26 GND 2809 drw 02 PIN NAMES Left Port Right Port L_R/W 0-3 R_R/W 0-3 L_OE L, H R_OE L, H L_CE L, H R_CE L, H L_CLKEN L, H Names Byte Read/Write Enables Word Output Enables Word Chip Enables R_CLKEN L, H Word Clock Enables L_CLK R_CLK Clock Inputs L_A 0-11 R_A 0-11 Address Inputs L_I/O 0-35 R_I/O 0-35 Data Input/Outputs VCC Power GND Ground 2809 tbl 01 7.4 2 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7.0 –0.5 to +7.0 Terminal Voltage –0.5 to VCC VTERM(3) TA Commercial Operating Temperature 0 to +70 Military RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Unit –0.5 to VCC V V –55 to +125 °C Grade Ambient Temperature GND VCC Military –55°C to +125°C 0V 5.0V ± 10% Commercial 0°C to +70°C 0V 5.0V ± 10% 2809 tbl 03 TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C IOUT DC Output Current 50 50 RECOMMENDED DC OPERATING CONDITIONS Symbol mA NOTES: 2809 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Inputs and Vcc terminals only. Parameter VCC Supply Voltage GND Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 — 6.0 V — 0.8 V –0.5 (1) NOTE: 1. VIL = -3.0V for pulse width less than 20ns. 2809 tbl 04 CAPACITANCE (TA = +25°C, F = 1.0MHZ) Symbol Parameter(1) Condition Max. Unit CIN Input Capacitance VIN = 0V 50 pF COUT Output Capacitance VOUT = 0V 15 pF 2809 tbl 05 TRUTH TABLES TRUTH TABLE I: READ/WRITE CONTROL (1) Inputs Synchronous Clk u u u u u Asynchronous Outputs CE R/W OE I/O0-35 Mode h h X High-Z Deselected, Power Down, Data I/O Disabled h l X DATAIN Deselected, Power Down, Data Input Enabled l l X DATAIN Write l h L DATAOUT l h H High-Z Read Data I/O Disabled 2809 tbl 06 TRUTH TABLE II: CLOCK ENABLE FUNCTION TABLE (1) Inputs Operating Mode Load “1” Load “0” Hold (do nothing) Clk u u u X Register Inputs Register Outputs CLKEN ADDR DATAIN ADDR DATAOUT l h h H H l l l L L h X X N/C N/C H X X N/C N/C NOTE: 2809 tbl 07 1. H = HIGH voltage level steady state, h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, L =LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, X = Don't care, N/C = No change 7.4 3 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%) IDT7M1024 Symbol Parameter Test Condition Min. Max. Unit |ILI| Input Leakage Current VCC = 5.5V, VIN = 0V to VCC — 40 Output Leakage Current CE = VIH, VOUT = 0V to VCC µA |ILO| — 10 µA VOL Output LOW Voltage IOL = 4mA — 0.4 V VOH Output HIGH Voltage IOH = –4mA 2.4 — V 2809 tbl 08 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5V ± 10%) IDT7M1024SxxG, IDT7M1024SxxGB –20 Symbol Parameter Dynamic ICC Operating Current (Both Ports Active) Standby ISB1 Current (Both Ports—TTL Level Inputs) Standby ISB2 Current (One Port—TTL Level Inputs) ISB3 Full Standby Current (Both Ports—CMOS Level Inputs) ISB4 Full Standby Current (One Port—CMOS Level Inputs) Test Condition CE ≤ VIL Outputs Open f = fMAX(1) L_CE and R_CE ≥ VIH f = fMAX(1) L_CE or R_CE ≥ VIH Active Port Outputs Open, f = fMAX(1) Both Ports R_CE and L_CE ≥ V CC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0(2) One Port L_CE or R_CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs Open, f = fMAX(1) Version Mil. –25 Typ. Max. — — –30 Typ. — Max. 1480 Typ. — Max. 1440 Com’l. — 1440 — 1360 — — Mil. — — — 680 — 560 Com’l. — 720 — 640 — — Mil. — — — 1080 — 1000 Com’l. — 1080 — 1000 — — Mil. — — — 80 — 80 Com’l. — 80 — 80 — — Mil. — — — 1040 — 960 Com’l. — 1040 — 960 — — Unit mA mA mA mA mA NOTES: 2809 tbl 09 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to inputs at CMOS level standby. 7.4 4 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load DATA OUT Zo = 50Ω 50Ω 1.5V See Figures 1, 2 and 3 2809 drw 03 2909 tbl 10 Figure 1. Output Load 5V 8 7 1250Ω 6 ∆TAA 5 (Typical, ns) 4 DATA OUT 775Ω 3 5pF* 2 1 2809 drw 04 20 40 60 80 100 120 140 160 180 200 Figure 2. Output Load (for tCLZ, tCHZ, tOLZ, and tOHZ) Capacitance (pF) 2809 drw 05 *Including scope and jig. Figure 3. Lumped Capacitive Load, Typical Derating AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE — (READ AND WRITE CYCLE TIMING) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) 7M1024SxxG, 7M1024SxxGB –20 Symbol Parameter –25 Min. Max. –30 Min. Max. Min. Max. Unit tCLK Clock Cycle Time 20 — 25 — 30 — ns tCLKH Clock HIGH Time 8 — 10 — 12 — ns tCLKL Clock LOW Time 8 — 10 — 12 — ns tCQV Clock HIGH to Output Valid — 20 — 25 — 30 ns tRSU Registered Signal Set-up Time 5 — 6 — 7 — ns tRHD Registered Signal Hold Time 2 — 2 — 2 — ns tCOH Data Output Hold After Clock HIGH 3 — 3 — 3 — ns tCLZ Clock HIGH to Output Low-Z 2 — 2 — 2 — ns tCHZ Clock HIGH to Output High-Z 2 9 2 12 2 15 ns tOE Output Enable to Output Valid — 10 — 12 — 15 ns tOLZ Output Enable to Output Low-Z 0 — 0 — 0 — ns tOHZ Output Disable to Output High-Z — 9 — 11 — 14 ns tCSU Clock Enable, Disable Set-up Time 5 — 6 — 7 — ns tCHD Clock Enable, Disable Hold Time 3 — 3 — 3 — ns — 35 — 45 — 55 Port-to-Port Delay tCWDD Write Port Clock HIGH to Read Data Delay ns 2809 tbl 11 7.4 5 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE, EITHER SIDE(1,2) tCLK tCLKH CLOCK tCLKL tCSU tCHD tCSU CLKEN tRSU tRHD CE R/W ADDRESS An An + 1 tCQV An + 2 An + 3 tCOH tCHZ Qn DATAOUT Qn + 1 Qn + 1 tCLZ tOHZ tOLZ tOE OE 2809 drw 06 TIMING WAVEFORM OF READ CYCLE WITH PORT-TO-PORT DELAY CLOCKR R/WR ADDRR DATA INR NO MATCH MATCH VALID CLOCKL R/WL ADDRL NO MATCH MATCH tCWDD tCQV DATA OUTL VALID VALID tCOH NOTES: 1. L_CE = R_CE = L, L_CLKEN = R_CLKEN = L 2. OE = L for the reading port. 2809 drw 07 7.4 6 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ-TO-WRITE CYCLE No. 1, CE HIGH(1) tCLK tCLKH CLOCK tCLK tCLKL tCLKH tCLKL CLKEN tRSU tRHD CE R/W ADDRESS An An + 1 DATAIN tCQV An + 2 An + 3 Dn + 2 Dn + 3 tCHZ DATAOUT Qn tCLZ 2809 drw 08 NOTE: 1. OE LOW throughout. TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1, CE LOW(1,2) tCLK tCLKH CLOCK tCLKL CLKEN tRSU tRHD CE R/W ADDRESS An An + 1 DATAIN tCQV DATAOUT An + 1 An + 2 Dn + 1 Dn + 2 tCHZ Qn tCLZ 2809 drw 09 NOTES: 1. During dead cycle, if CE is LOW, data will be written into array. 2. OE LOW throughout. 7.4 7 IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES PACKAGE DIMENSIONS TOP VIEW SIDE VIEW 1.327 1.353 0.045 0.055 0.015 0.021 1.327 1.353 0.100 TYP 0.195 MAX 0.125 0.135 0.050 TYP PIN A1 BOTTOM VIEW 2809 drw 10 ORDERING INFORMATION IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B G Ceramic Pin Grid Array 20 25 30 Commercial Only S Standard Power Speed in Nanoseconds Military Only 7M1024 4K x 36-Bit Synchronous Dual-Port RAM Module 2809 drw 11 7.4 8