ISL1208 ® I2C® Real Time Clock/Calendar Data Sheet August 23, 2006 Low Power RTC with Battery Backed SRAM Features The ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. Ordering Information PART PART NUMBER MARKING • Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds - Day of the Week, Day, Month, and Year • 15 Selectable Frequency Outputs • Single Alarm - Settable to the Second, Minute, Hour, Day of the Week, Day, or Month - Single Event or Pulse Interrupt Mode • Automatic Backup to Battery or Super Cap • Power Failure Detection • On-Chip Oscillator Compensation VDD RANGE TEMP. RANGE (°C) • 2 Bytes Battery-Backed User SRAM PACKAGE ISL1208IU8 AGS 2.7V to 5.5V -40 to +85 8 Ld MSOP ISL1208IU8-TK AGS 2.7V to 5.5V -40 to +85 8 Ld MSOP Tape & Reel ISL1208IU8Z (Note) ANW 2.7V to 5.5V -40 to +85 8 Ld MSOP (Pb-free) • I2C Interface - 400kHz Data Transfer Rate • 400nA Battery Supply Current • Same Pin Out as ST M41Txx and Maxim DS13xx Devices • Small Package Options - 8 Ld MSOP and SOIC Packages ISL1208IU8Z-TK ANW (Note) 2.7V to 5.5V -40 to +85 8 Ld MSOP Tape & Reel (Pb-free) ISL1208IB8 1208I 2.7V to 5.5V -40 to +85 8 Ld SOIC Applications ISL1208IB8-TK 1208I 2.7V to 5.5V -40 to +85 8 Ld SOIC Tape & Reel • Utility Meters ISL1208IB8Z (Note) 1208ZI 2.7V to 5.5V -40 to +85 8 Ld SOIC (Pb-free) ISL1208IB8Z-TK 1208ZI (Note) FN8085.5 2.7V to 5.5V -40 to +85 8 Ld SOIC Tape & Reel (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. * Contact Factory for availability. • Pb-Free Plus Anneal Available (RoHS Compliant) • HVAC Equipment • Audio/Video Components • Set Top Box/Television • Modems • Network Routers, Hubs, Switches, Bridges • Cellular Infrastructure Equipment • Fixed Broadband Wireless Equipment • Pagers/PDA • POS Equipment • Test Meters/Fixtures Pinout ISL1208 (8 LD MSOP, SOIC) TOP VIEW • Office Automation (Copiers, Fax) • Home Appliances • Computer Products X1 1 8 VDD X2 2 7 IRQ/FOUT VBAT 3 6 SCL GND 4 5 SDA 1 • Other Industrial/Medical/Automotive CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL1208 Block Diagram SDA BUFFER SDA I2C INTERFACE SCL BUFFER SCL Seconds RTC CONTROL LOGIC Minutes Hours Day of Week X1 CRYSTAL OSCILLATOR X2 RTC DIVIDER Date Month VDD POR FREQUENCY OUT Year ALARM CONTROL REGISTERS VTRIP USER SRAM SWITCH IRQ/ FOUT INTERNAL SUPPLY VBAT Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. 2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 3 VBAT This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. 4 GND Ground. 5 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. 6 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 7 8 IRQ/FOU Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. T VDD Power supply. 2 FN8085.5 August 23, 2006 ISL1208 Absolute Maximum Ratings Voltage on VDD, VBAT, SCL, SDA, and IRQ Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Voltage on X1 and X2 Pins (respect to ground) . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode) -0.5V to VBAT + 0.5 (VBAT Mode) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL PARAMETER CONDITIONS TYP (Note 4) MIN MAX UNITS VDD Main Power Supply 2.7 5.5 V VBAT Battery Supply Voltage 1.8 5.5 V IDD1 Supply Current IDD2 Supply Current With I2C Active IDD3 IBAT VDD = 5V 2 6 µA VDD = 3V 1.2 4 µA VDD = 5V 40 120 µA 1, 2 Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 1.4 5 µA 1 Battery Supply Current VBAT = 3V 400 950 nA 1 ILI Input Leakage Current on SCL 100 nA ILO I/O Leakage Current on SDA 100 nA VTRIP NOTES 1, 2 VBAT Mode Threshold 1.6 2.2 2.6 V VTRIPHYS VTRIP Hysteresis 10 30 75 mV VBATHYS VBAT Hysteresis 15 50 100 mV VDD = 5V IOL = 3mA 0.4 V VDD = 2.7V IOL = 1mA 0.4 V MAX UNITS NOTES 10 V/ms 3 IRQ/FOUT VOL Output Low Voltage Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL VDD SR- PARAMETER CONDITIONS TYP (Note 4) MIN VDD Negative Slewrate Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNITS NOTES SERIAL INTERFACE SPECS VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V SDA and SCL Input Buffer Hysteresis 0.05 x VDD Hysteresis VOL SDA Output Buffer LOW Voltage, Sinking 3mA 3 0 V 0.4 V FN8085.5 August 23, 2006 ISL1208 Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER Cpin SDA and SCL Pin Capacitance fSCL SCL Frequency TEST CONDITIONS MIN TA = 25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V TYP (Note 4) MAX UNITS 10 pF 400 kHz tIN Pulse width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must Be Free Before the SDA crossing 70% of VDD during a Start of a New Transmission STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. 20 tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 600 ns tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. 600 ns Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. 0 ns tR SDA and SCL Rise Time From 30% to 70% of VDD 20 + 0.1 x Cb 300 ns tF SDA and SCL Fall Time From 70% to 30% of VDD 20 + 0.1 x Cb 300 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5kΩ. For Cb = 40pF, max is about 15~20kΩ 1 tDH 900 NOTES ns kΩ NOTES: 1. IRQ & FOUT Inactive. 2. LPMODE = 0 (default). 3. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 4. Typical values are for T = 25°C and 3.3V supply voltage. 4 FN8085.5 August 23, 2006 ISL1208 SDA vs SCL Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 5 FN8085.5 August 23, 2006 ISL1208 Typical Performance Curves Temperature is 25°C unless otherwise specified 1E-6 1E-6 900E-9 800E-9 800E-9 600E-9 600E-9 IBAT(A) IBAT (A) 700E-9 500E-9 400E-9 400E-9 300E-9 200E-9 200E-9 100E-9 000E+0 1.5 2.0 2.5 3.0 3.5 4.0 VBAT (V) 4.5 5.0 000E+0 5.5 FIGURE 1. IBAT vs VBAT -20 0 20 40 TEMPERATURE (°C) 60 80 FIGURE 2. IBAT vs TEMPERATURE AT VBAT = 3V 2.4E-6 2.4E-06 2.2E-6 2.2E-06 2.0E-6 VCC = 5V 2.0E-06 1.8E-6 1.8E-06 1.6E-06 LPMODE = 0 1.6E-6 IDD1 (A) IDD1 (A) -40 1.4E-6 LPMODE = 1 1.2E-6 VCC = 3.3V 1.0E-6 1.4E-06 800.0E-9 1.2E-06 600.0E-9 40 60 400.0E-9 2.5 80 3.0 3.5 4.0 TEMPERATURE (°C) FIGURE 5. IDD1 vs FOUT AT VDD = 3.3V 6 5.5 4096 FOUT (Hz) 32768 4096 32768 64 1024 16 32 4 8 1 2 1/2 1/4 1/8 1/16 1.3E-6 64 1.4E-6 1024 1.5E-6 1 1.6E-6 1/2 1.7E-6 1/4 IDD1 (A) 1.8E-6 1/32 IDD1 (A) 1.9E-6 3.0E-6 2.9E-6 2.8E-6 2.7E-6 2.6E-6 2.5E-6 2.4E-6 2.3E-6 2.2E-6 2.1E-6 2.0E-6 1.9E-6 1.8E-6 1/8 2.0E-6 1/16 2.1E-6 FOUT (Hz) 5.0 FIGURE 4. IDD1 vs VCC WITH LPMODE ON & OFF 1/32 FIGURE 3. IDD1 vs TEMPERATURE 1.2E-6 4.5 VCC (V) 16 20 32 0 4 -20 8 -40 2 1.0E-06 FIGURE 6. IDD1 vs FOUT AT VDD = 5V FN8085.5 August 23, 2006 ISL1208 EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V X1 1533Ω FOR VOL= 0.4V X2 AND IOL = 3mA SDA AND IRQ/FOUT 100pF FIGURE 8. RECOMMENDED CRYSTAL CONNECTION VBAT FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V General Description The ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, and battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. The ISL1208's powerful alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or SuperCap with automatic switchover from VDD to VBAT. The entire ISL1208 device is fully operational from 2.0V to 5.5V and the clock/calendar portion of the device remains fully operational down to 1.8V (Standby Mode). Pin Description X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1208 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a 32.768kHz source at pin X1. 7 This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used. IRQ/FOUT (Interrupt Output/Frequency Output) This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. • Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. • Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain active low output. Serial Clock (SCL) The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. VDD, GND Chip power supply and ground pins. The device will operate with a power supply from 2.0V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. Functional Description Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power FN8085.5 August 23, 2006 ISL1208 Normal Mode (VDD) to Battery Backup Mode (VBAT) The I2C bus is deactivated in battery backup mode to provide lower power. Aside from this, all RTC functions are operational during battery backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL1208 are active during battery backup mode unless disabled via the control register. The User SRAM is operational in battery backup mode down to 2V. To transition from the VDD to VBAT mode, both of the following conditions must be met: Power Failure Detection Condition 1: VDD < VBAT - VBATHYS where VBATHYS ≈ 50mV The ISL1208 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT). the ISL1208 for up to 10 years. Another option is to use a Super Cap for applications where VDD is interrupted for up to a month. See the Applications Section for more information. Condition 2: VDD < VTRIP where VTRIP ≈ 2.2V Low Power Mode Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL1208 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS ≈ 30mV These power control situations are illustrated in Figures 9 and 10. BATTERY BACKUP MODE VDD VTRIP 2.2V VBAT 1.8V The normal power switching of the ISL1208 is designed to switch into battery backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Another mode, called Low Power Mode, is available to allow direct switching from VDD to VBAT without requiring VDD to drop below VTRIP. Since the additional monitoring of VDD vs VTRIP is no longer needed, that circuitry is shut down and less power is used while operating from VDD. Power savings are typically 600nA at VDD = 5V. Low Power Mode is activated via the LPMODE bit in the control and status registers. Low Power Mode is useful in systems where VDD is normally higher than VBAT at all times. The device will switch from VDD to VBAT when VDD drops below VBAT, with about 50mV of hysteresis to prevent any switchback of VDD after switchover. In a system with a VDD = 5V and backup lithium battery of VBAT = 3V, Low Power Mode can be used. However, it is not recommended to use Low Power Mode in a system with VDD = 3.3V ±10%, VBAT ≥ 3.0V, and when there is a finite I-R voltage drop in the VDD line. InterSeal™ Battery Saver VBAT + VBATHYS VBAT - VBATHYS FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP BATTERY BACKUP MODE VDD Real Time Clock Operation VBAT 3.0V VTRIP 2.2V VTRIP VTRIP + VTRIPHYS FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP 8 The ISL1208 has the InterSeal™ Battery Saver which prevents initial battery current drain before it is first used. For example, battery-backed RTCs are commonly packaged on a board with a battery connected. In order to preserve battery life, the ISL1208 will not draw any power from the battery source until after the device is first powered up from the VDD source. Thereafter, the device will switchover to battery backup mode whenever VDD power is lost. The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL1208 powers up after the loss of both VDD and VBAT, the clock will FN8085.5 August 23, 2006 ISL1208 not begin incrementing until at least one byte is written to the clock register. Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer. The ISL1208 provides on-chip crystal compensation networks to adjust load capacitance to tune oscillator frequency from -94ppm to +140ppm. For more detailed information see the Application Section. Single Event and Interrupt The alarm mode is enabled via the ALME bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, an IRQ pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to “1”. NOTE: The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery backup mode using the FOBATB bit. For more information on the alarm, please see the Alarm Registers Description. I2C Serial Interface The ISL1208 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bidirectional data signal (SDA) and a clock signal (SCL). Oscillator Compensation The ISL1208 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. The total possible compensation is typically -94ppm to +140ppm. Two compensation mechanisms that are available are as follows: 1. An analog trimming (ATR) register that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. The individual digital capacitor is selectable from a range of 9pF to 40.5pF (based upon 32.758kHz). This translates to a calculated compensation of approximately -34ppm to +80ppm. (See ATR description.) 2. A digital trimming register (DTR) that can be used to adjust the timing counter by ±60ppm. (See DTR description.) Also provided is the ability to adjust the crystal capacitance when the ISL1208 switches from VDD to battery backup mode. (See Battery Mode ATR Selection for more details.) Register Descriptions The battery-backed registers are accessible following a slave byte of “1101111x” and reads or writes to addresses [00h:13h]. The defined addresses and default values are described in the Table 1. Address 09h is not used. Reads or writes to 09h will not affect operation of the device but should be avoided. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 4 sections. These are: Frequency Output Mode 1. Real Time Clock (7 bytes): Address 00h to 06h. The ISL1208 has the option to provide a frequency output signal using the IRQ/FOUT pin. The frequency output mode is set by using the FO bits to select 15 possible output frequency values from 0 to 32kHz. The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit. 2. Control and Status (5 bytes): Address 07h to 0Bh. 3. Alarm (6 bytes): Address 0Ch to 11h. 4. User SRAM (2 bytes): Address 12h to 13h. There are no addresses above 13h. General Purpose User SRAM The ISL1208 provides 2 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode. 9 FN8085.5 August 23, 2006 ISL1208 instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 4 of address 07h) is set to “1”. A multi-byte read or write operation is limited to one section per operation. Access to another section requires a new operation. A read or write can begin at any address within the section. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers. TABLE 1. REGISTER MEMORY MAP BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 00h SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0-59 00h 01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0-59 00h 02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0-23 00h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1-31 00h 04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1-12 00h 05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0-99 00h 06h DW 0 0 0 0 0 DW2 DW1 DW0 0-6 00h 07h SR ARST WRTC Reserved ALM BAT RTCF N/A 01h INT IM FOBATB FO3 FO2 FO1 FO0 N/A 00h N/A 00h 03h 08h 09h 0Ah RTC Control and Status XTOSCB Reserved ALME LPMODE Reserved ATR BMATR1 0Bh DTR Reserved 0Ch SCA ESCA ASC22 ASC21 ASC20 0Dh MNA EMNA AMN22 AMN21 HRA EHRA 0 0Fh DTA EDTA 10h MOA 11h 0Eh BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 N/A 00h DTR2 DTR1 DTR0 N/A 00h ASC13 ASC12 ASC11 ASC10 00-59 00h AMN20 AMN13 AMN12 AMN11 AMN10 00-59 00h AHR21 AHR20 AHR13 AHR12 AHR11 AHR10 0-23 00h 0 ADT21 ADT20 ADT13 ADT12 ADT11 ADT10 1-31 00h EMOA 0 0 AMO20 AMO13 AMO12 AMO11 AMO10 1-12 00h DWA EDWA 0 0 0 0 ADW12 ADW11 ADW10 0-6 00h USR1 USR17 USR16 USR15 USR14 USR13 USR12 USR11 USR10 N/A 00h USR2 USR27 USR26 USR25 USR24 USR23 USR22 USR21 USR20 N/A 00h Alarm 12h User 13h 10 FN8085.5 August 23, 2006 ISL1208 Real Time Clock Registers REAL TIME CLOCK FAIL BIT (RTCF) Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as “0”. 24 HOUR TIME If the MIL bit of the HR register is “1”, the RTC uses a 24hour format. If the MIL bit is “0”, the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a “1” representing PM. The clock defaults to 12-hour format time with HR21 = “0”. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL1208 does not correct for the leap year in the year 2100. Control and Status Registers Addresses [07h to 0Bh] The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers. The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure, battery mode, alarm trigger, write protection of clock counter, crystal oscillator enable and auto reset of status bits. TABLE 2. STATUS REGISTER (SR) 07h Default 7 6 5 4 3 2 1 0 ARST XTOSCB reserved WRTC reserved ALM BAT RTCF 0 0 BATTERY BIT (BAT) This bit is set to a “1” when the device enters battery backup mode. This bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. ALARM BIT (ALM) These bits announce if the alarm matches the real time clock. If there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. NOTE: An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB) Status Register (SR) ADDR This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL1208 internally) when the device powers up after having lost all power to the device (both VDD and VBAT go to 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). 0 0 0 0 0 0 This bit enables/disables the internal crystal oscillator. When the XTOSCB is set to “1”, the oscillator is disabled, and the X1 pin allows for an external 32kHz signal to drive the RTC. The XTOSCB bit is set to “0” on powerup. AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the BAT and ALM status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to “0”, the user must manually reset the BAT and ALM bits. Interrupt Control Register (INT) TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 11 7 08h IM Default 0 6 5 4 3 2 1 0 ALME LPMODE FOBATB FO3 FO2 FO1 FO0 0 0 0 0 0 0 0 FN8085.5 August 23, 2006 ISL1208 FREQUENCY OUT CONTROL BITS (FO <3:0>) These bits enable/disable the frequency output function and select the output frequency at the IRQ/FOUT pin. See Table 4 for frequency selection. When the frequency mode is enabled, it will override the alarm mode at the IRQ/FOUT pin. NOTE: When the frequency output mode is enabled, the alarm function is disabled. INTERRUPT/ALARM MODE BIT (IM) TABLE 4. FREQUENCY SELECTION OF FOUT PIN FREQUENCY, FOUT UNITS is cleared to “0”, the alarm function is disabled. The alarm function can operate in either a single event alarm or a periodic interrupt alarm (see IM bit). FO3 FO2 FO1 FO0 0 Hz 0 0 0 0 32768 Hz 0 0 0 1 4096 Hz 0 0 1 0 1024 Hz 0 0 1 1 64 Hz 0 1 0 0 32 Hz 0 1 0 1 16 Hz 0 1 1 0 8 Hz 0 1 1 1 4 Hz 1 0 0 0 2 Hz 1 0 0 1 1 Hz 1 0 1 0 1/2 Hz 1 0 1 1 1/4 Hz 1 1 0 0 1/8 Hz 1 1 0 1 1/16 Hz 1 1 1 0 1/32 Hz 1 1 1 1 This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to “1”, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ/FOUT pin when the RTC is triggered by the alarm as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to “0”, the alarm will operate in standard mode, where the IRQ/FOUT pin will be tied low until the ALM status bit is cleared to “0”. IM BIT FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables the FOUT/IRQ pin during battery backup mode (i.e. VBAT power source active). When the FOBATB is set to “1” the FOUT/IRQ pin is disabled during battery backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to “0”, the FOUT/IRQ pin is enabled during battery backup mode. LOW POWER MODE BIT (LPMODE) This bit enables/disables low power mode. With LPMODE = “0”, the device will be in normal mode and the VBAT supply will be used when VDD < VBAT - VBATHYS and VDD < VTRIP. With LPMODE = “1”, the device will be in low power mode and the VBAT supply will be used when VDD < VBAT - VBATHYS. There is a supply current saving of about 600nA when using LPMODE = “1” with VDD = 5V. (See Typical Performance Curves: IDD vs VCC with LPMODE ON & OFF.) ALARM ENABLE BIT (ALME) INTERRUPT/ALARM FREQUENCY 0 Single Time Event Set By Alarm 1 Repetitive/Recurring Time Event Set By Alarm Analog Trimming Register ANALOG TRIMMING REGISTER (ATR<5:0>) X1 CX1 Crystal Oscillator X2 CX2 FIGURE 11. DIAGRAM OF ATR Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34 to +80ppm to the nominal frequency compensation. The combination of analog and digital trimming can give up to -94 to +140ppm of total adjustment. The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 This bit enables/disables the alarm function. When the ALME bit is set to “1”, the alarm function is enabled. When the ALME 12 FN8085.5 August 23, 2006 ISL1208 and X2 pins to ground (see Figure 11). The value of CX1 and CX2 is given by the following formula: C X = ( 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 )pF The effective series load capacitance is the combination of CX1 and CX2: 1 C = ----------------------------------LOAD 1 1 ⎛ ---------- + -----------⎞ ⎝C ⎠ X1 C X2 C LOAD 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 = ⎛ -----------------------------------------------------------------------------------------------------------------------------⎞ pF ⎝ ⎠ 2 For example, CLOAD(ATR=00000) = 12.5pF, CLOAD(ATR=100000) = 4.5pF, and CLOAD(ATR=011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. BATTERY MODE ATR SELECTION (BMATR <1:0>) Since the accuracy of the crystal oscillator is dependent on the VDD/VBAT operation, the ISL1208 provides the capability to adjust the capacitance between VDD and VBAT when the device switches between power sources. DELTA CAPACITANCE (CBAT TO CVDD) BMATR1 BMATR0 0 0 0pF 0 1 -0.5pF (≈ +2ppm) 1 0 +0.5pF (≈ -2ppm) 1 1 +1pF (≈ -4ppm) DIGITAL TRIMMING REGISTER (DTR <2:0>) The digital trimming bits DTR0, DTR1, and DTR2 adjust the average number of counts per second and average the ppm error to achieve better accuracy. • DTR2 is a sign bit. DTR2 = “0” means frequency compensation is >0. DTR2 = “1” means frequency compensation is <0. • DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm adjustment and DTR0 gives 20ppm adjustment. A range from -60ppm to +60ppm can be represented by using these three bits (see Table 5). TABLE 5. DIGITAL TRIMMING REGISTERS DTR REGISTER DTR2 DTR1 DTR0 ESTIMATED FREQUENCY PPM 0 0 0 0 (default) 0 0 1 +20 0 1 0 +40 0 1 1 +60 1 0 0 0 1 0 1 -20 1 1 0 -40 1 1 1 -60 Alarm Registers Addresses [0Ch to 11h] The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. There are two alarm operation modes: Single Event and periodic Interrupt Mode: • Single Event Mode is enabled by setting the ALME bit to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to “1” and the IRQ output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the auto-reset feature. • Interrupt Mode is enabled by setting the ALME bit to “1”, the IM bit to “1”, and disabling the frequency output. The IRQ output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. To clear an alarm, the ALM bit in the status register must be set to “0” with a write. Note that if the ARST bit is set to 1 (address 07h, bit 7), the ALM bit will automatically be cleared when the status register is read. 13 FN8085.5 August 23, 2006 ISL1208 Below are examples of both Single Event and periodic Interrupt Mode alarms. Example 1 – Alarm set with single interrupt (IM=”0”) Once the registers are set, the following waveform will be seen at IRQ-: RTC and alarm registers are both “30” sec A single alarm will occur on January 1 at 11:30am. A. Set Alarm registers as follows: ALARM REGISTER 7 BIT 6 5 4 3 2 1 0 HEX SCA 0 0 0 0 0 0 0 0 00h Seconds disabled DESCRIPTION MNA 1 0 1 1 0 0 0 0 B0h Minutes set to 30, enabled Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared. HRA 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled User Registers DTA 1 0 0 0 0 0 0 1 81h Date set to 1, enabled MOA 1 0 0 0 0 0 0 1 81h Month set to 1, enabled DWA 0 0 0 0 0 0 0 0 00h Day of week disabled B. Also the ALME bit must be set as follows: CONTROL REGISTER 7 INT 0 BIT 6 5 4 3 2 1 0 HEX 1 x x 0 0 0 0 x0h DESCRIPTION Enable Alarm xx indicate other control bits After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register to “1” and also bringing the IRQ output low. Example 2 – Pulsed interrupt once per minute (IM=”1”) Interrupts at one minute intervals when the seconds register is at 30 seconds. A. Set Alarm registers as follows: BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX SCA DESCRIPTION 1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled MNA 0 0 0 0 0 0 0 0 00h Minutes disabled HRA 0 0 0 0 0 0 0 0 00h Hours disabled DTA 0 0 0 0 0 0 0 0 00h Date disabled MOA 0 0 0 0 0 0 0 0 00h Month disabled DWA 0 0 0 0 0 0 0 0 00h Day of week disabled B. Set the Interrupt register as follows: BIT CONTROL REGISTER 7 6 5 4 3 2 1 0 HEX INT DESCRIPTION 1 1 x x 0 0 0 0 x0h Enable Alarm and Int Mode 60 sec Addresses [12h to 13h] These registers are 2 bytes of battery-backed user memory storage. I2C Serial Interface The ISL1208 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL1208 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 12). On power-up of the ISL1208, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL1208 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 12). A START condition is ignored during the powerup sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 12). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the xx indicate other control bits 14 FN8085.5 August 23, 2006 ISL1208 Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 13). The ISL1208 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL1208 also responds with an ACK after receiving a Data SCL SDA DATA STABLE START DATA CHANGE DATA STABLE STOP FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE ISL1208 S T A R T ADDRESS BYTE IDENTIFICATION BYTE 1 1 0 1 1 1 1 0 S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 14. BYTE WRITE SEQUENCE 15 FN8085.5 August 23, 2006 ISL1208 Device Addressing Write Operation Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are “1101111”. Slave bits “1101” access the register. Slave bits “111” specify the device select bits. A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL1208 responds with an ACK. At this time, the I2C interface enters a standby state. The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a “1”, then a read operation is selected. A “0” selects a write operation (Refer to Figure 15). After loading the entire Slave Address Byte from the SDA bus, the ISL1208 compares the device identifier and device select bits with “1101111”. Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up the internal address counter is set to address 0h, so a current address read of the CCR array starts at address 0h. When required, as part of a random read, the master must supply the 1 Word Address Bytes as shown in Figure 16. In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the “read” section. For a random read of the Clock/Control Registers, the slave byte must be “1101111x” in both places. R/W SLAVE ADDRESS BYTE A1 A0 WORD ADDRESS D1 D0 DATA BYTE 1 1 0 1 1 1 1 A7 A6 A5 A4 A3 A2 D7 D6 D5 D4 D3 D2 Read Operation A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 16). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL1208 responds with an ACK. Then the ISL1208 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 16). The Data Bytes are from the memory location indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 13h the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W=0 S T IDENTIFICATION A BYTE WITH R R/W = 1 T ADDRESS BYTE S T O P A C K 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 A C K SIGNALS FROM THE SLAVE A C K A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 16. READ SEQUENCE 16 FN8085.5 August 23, 2006 ISL1208 Application Section Oscillator Crystal Requirements The ISL1208 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 6 lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL1208 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 12.5pF and an equivalent series resistance of less than 50k. The crystal’s temperature range specification should match the application. Many crystals are rated for -10°C to +60°C (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. TABLE 6. SUGGESTED SURFACE MOUNT CRYSTALS In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the ISL1208. There are 3 bits known as the Digital Trimming Register (DTR). The range provided is ±60ppm in increments of 20ppm. DTR operates by adding or skipping pulses in the clock counter. It is very useful for coarse adjustments of frequency drift over temperature or extending the adjustment range available with the ATR register. Initial accuracy is best adjusted by enabling the frequency output (using the INT register, address 08h), and monitoring the ~IRQ/FOUT pin with a calibrated frequency counter. The frequency used is unimportant, although 1Hz is the easiest to monitor. The gating time should be set long enough to ensure accuracy to at least 1ppm. The ATR should be set to the center position, or 100000Bh, to begin with. Once the initial measurement is made, then the ATR register can be changed to adjust the frequency. Note that increasing the ATR register for increased capacitance will lower the frequency, and vice-versa. If the initial measurement shows the frequency is far off, it will be necessary to use the DTR register to do a coarse adjustment. Note that most all crystals will have tight enough initial accuracy at room temperature so that a small ATR register adjustment should be all that is needed. MANUFACTURER PART NUMBER Citizen CM200S Epson MC-405, MC-406 Raltron RSM-200S SaRonix 32S12 Ecliptek ECPSM29T-32.768K ECS ECX-306 Temperature Compensation Fox FSM-327 The ATR and DTR controls can be combined to provide crystal drift temperature compensation. The typical 32.768kHz crystal has a drift characteristic that is similar to that shown in Figure 17. There is a turnover temperature (T0) where the drift is very near zero. The shape is parabolic as it varies with the square of the difference between the actual temperature and the turnover temperature. The ISL1208 device contains circuitry for adjusting the frequency of the crystal oscillator. This circuitry can be used to trim oscillator initial accuracy as well as adjust the frequency to compensate for temperature changes. The Analog Trimming Register (ATR) is used to adjust the load capacitance seen by the crystal. There are six bits of ATR control, with linear capacitance increments available for adjustment. Since the ATR adjustment is essentially “pulling” the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. The equations which govern pulling show that lower capacitor values of ATR adjustment will provide larger increments. Also, the higher values of ATR adjustment will produce smaller incremental frequency changes. These values typically vary from 6-10 ppm/bit at the low end to <1ppm/bit at the highest capacitance settings. The range afforded by the ATR adjustment with a typical surface mount crystal is typically -34 to +80ppm around the ATR=0 default setting because of this property. The user should note this when using the ATR for calibration. The temperature drift of the capacitance used in the ATR control is extremely low, so this feature can be used for temperature compensation with good accuracy. 17 0.0 -20.0 -40.0 -60.0 PPM Crystal Oscillator Frequency Adjustment -80.0 -100.0 -120.0 -140.0 -160.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) FIGURE 17. RTC CRYSTAL TEMPERATURE DRIFT If full industrial temperature compensation is desired in an ISL1208 circuit, then both the DTR and ATR registers will need to be utilized (total correction range = -94 to +140ppm). FN8085.5 August 23, 2006 ISL1208 A system to implement temperature compensation would consist of the ISL1208, a temperature sensor, and a microcontroller. These devices may already be in the system so the function will just be a matter of implementing software and performing some calculations. Fairly accurate temperature compensation can be implemented just by using the crystal manufacturer’s specifications for the turnover temperature T0 and the drift coefficient (β). The formula for calculating the oscillator adjustment necessary is: Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit to cause misclocking. Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device. Adjustment (ppm) = (T – T0)2 * β Once the temperature curve for a crystal is established, then the designer should decide at what discrete temperatures the compensation will change. Since drift is higher at extreme temperatures, the compensation may not be needed until the temperature is greater than 20°C from T0. PPM ADJUSTMENT A sample curve of the ATR setting vs. Frequency Adjustment for the ISL1208 and a typical RTC crystal is given in Figure 18. This curve may vary with different crystals, so it is good practice to evaluate a given crystal in an ISL1208 circuit before establishing the adjustment values. 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 -40.0 FIGURE 19. SUGGESTED LAYOUT FOR ISL1208 AND CRYSTAL In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. If the ~IRQ/FOUT pin is used as a clock, it should be routed away from the RTC device as well. The traces for the VBAT and VCC pins can be treated as a ground, and should be routed around the crystal. Super Capacitor Backup 0 5 10 15 20 25 30 35 40 45 50 55 60 ATR SETTING FIGURE 18. ATR SETTING vs OSCILLATOR FREQUENCY ADJUSTMENT This curve is then used to figure what ATR and DTR settings are used for compensation. The results would be placed in a lookup table for the microcontroller to access. Layout Considerations The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies such as 32.768kHz are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. Figure 19 shows a suggested layout for the ISL1208 device using a surface mount crystal. Two main precautions should be followed: 18 The ISL1208 device provides a VBAT pin which is used for a battery backup input. A Super Capacitor can be used as an alternative to a battery in cases where shorter backup times are required. Since the battery backup supply current required by the ISL1208 is extremely low, it is possible to get months of backup operation using a Super Capacitor. Typical capacitor values are a few µF to 1 Farad or more depending on the application. If backup is only needed for a few minutes, then a small inexpensive electrolytic capacitor can be used. For extended periods, a low leakage, high capacity Super Capacitor is the best choice. These devices are available from such vendors as Panasonic and Murata. The main specifications include working voltage and leakage current. If the application is for charging the capacitor from a +5V ±5% supply with a signal diode, then the voltage on the capacitor can vary from ~4.5V to slightly over 5.0V. A capacitor with a rated WV of 5.0V may have a reduced lifetime if the supply voltage is slightly high. The leakage current should be as small as possible. For example, a Super Capacitor should be specified with leakage of well below 1µA. A standard electrolytic capacitor with DC leakage current in the microamps will have a severely shortened backup time. Below are some examples with equations to assist with calculating backup times and required capacitance for the ISL1208 device. The backup supply current plays a major FN8085.5 August 23, 2006 ISL1208 part in these equations, and a typical value was chosen for example purposes. For a robust design, a margin of 30% should be included to cover supply current and capacitance tolerances over the results of the calculations. Even more margin should be included if periods of very warm temperature operation are expected. Example 1. Calculating backup time given voltages and capacitor value Combining with Equation 2 gives the equation for backup time: TBACKUP = CBAT * (VBAT2 - VBAT1) / (IBATAVG + ILKG) seconds (EQ. 5) where CBAT = 0.47F VBAT2 = 4.7V 1N4148 VBAT1 = 1.8V ILKG = 0 (assumed minimal) 2.7V to 5.5V VBAT VCC Solving equation 4 for this example, IBATAVG = 4.387E-7 A CBAT TBACKUP = 0.47 * (2.9) / 4.38E-7 = 3.107E6 sec GND FIGURE 20. SUPERCAPACITOR CHARGING CIRCUIT In Figure 20, use CBAT = 0.47F and VCC = 5.0V. With VCC = 5.0V, the voltage at VBAT will approach 4.7V as the diode turns off completely. The ISL1208 is specified to operate down to VBAT = 1.8V. The capacitance charge/discharge equation is used to estimate the total backup time: I = CBAT * dV/dT Example 2. Calculating a capacitor value for a given backup time (EQ. 1) (EQ. 2) CBAT = dT*I/dV CBAT is the backup capacitance and dV is the change in voltage from fully charged to loss of operation. Note that ITOT is the total of the supply current of the ISL1208 (IBAT) plus the leakage current of the capacitor and the diode, ILKG. In these calculations, ILKG is assumed to be extremely small and will be ignored. If an application requires extended operation at temperatures over 50°C, these leakages will increase and hence reduce backup time. Note that IBAT changes with VBAT almost linearly (see Typical Performance Curves). This allows us to make an approximation of IBAT, using a value midway between the two endpoints. The typical linear equation for IBAT vs VBAT is: IBAT = 1.031E-7*(VBAT) + 1.036E-7 Amps CBAT = 0.70 * 35.96 = 25.2 days Referring to Figure 20 again, the capacitor value needs to be calculated to give 2 months (60 days) of backup time, given VCC = 5.0V. As in Example 1, the VBAT voltage will vary from 4.7V down to 1.8V. We will need to rearrange Equation 2 to solve for capacitance: Rearranging gives dT = CBAT * dV/ITOT to solve for backup time. Since there are 86,400 seconds in a day, this corresponds to 35.96 days. If the 30% tolerance is included for capacitor and supply current tolerances, then worst case backup time would be: (EQ. 3) Using this equation to solve for the average current given 2 voltage points gives: (EQ. 6) Using the terms described above, this equation becomes: CBAT = TBACKUP * (IBATAVG + ILKG)/(VBAT2 – VBAT1) (EQ. 7) where TBACKUP = 60 days * 86,400 sec/day = 5.18 E6 sec IBATAVG = 4.387 E-7 A (same as Example 1) ILKG = 0 (assumed) VBAT2 = 4.7V VBAT1 = 1.8V Solving gives CBAT = 5.18 E6 * (4.387 E-7)/(2.9) = 0.784F If the 30% tolerance is included for tolerances, then worst case cap value would be CBAT = 1.3 *.784 = 1.02F IBATAVG = 5.155E-8*(VBAT2 + VBAT1) + 1.036E-7 Amps (EQ. 4) 19 FN8085.5 August 23, 2006 ISL1208 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X θ L1 SEATING PLANE C 0.20 (0.008) C a CL E1 C D MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC -B- 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N C 0.20 (0.008) MIN A L1 -A- SIDE VIEW SYMBOL e L MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 20 FN8085.5 August 23, 2006 ISL1208 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8085.5 August 23, 2006