Statistical Analysis and Design: From Picoseconds to Probabilities Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY http://www.research.ibm.com/people/c/chandu With acknowledgments to the extended timing, modeling, synthesis and methodology teams at IBM Yorktown, Fishkill and Burlington © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 1 of 80 Happy Independence Day © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 2 of 80 Propositions (and outline) 1. Variability is proportionately increasing; therefore, a new paradigm is required 2. Correlations matter 3. Statistical timing tools are rising to the challenge 4. Robustness is an important metric 5. Statistical treatment of variability will pervade all aspects of chip design methodology, manufacturing and test • ASICs and processors will both benefit © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 3 of 80 Section 1: The Problem … and what exactly is a statistical timer? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 4 of 80 Performance The march of technology Technology generation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 5 of 80 The source of the problem • Variability is proportionately increasing – manufacturing • FEOL: critical dimensions are scaling faster than our control of them • BEOL: variability dramatically increases the number of independent and significant sources of variation – – – – environmental (Vdd, temperature) fatigue (NBTI, hot electron effect) across-chip (OCV/ACLV, temperature, Vdd) circuit design (PLL jitter, coupling noise, SOI history) – model-to-hardware correlation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 6 of 80 Delay impact of variations Parameter Delay Impact BEOL metal (Metal mistrack, thin/thick wires) -10% → +25% Environmental (Voltage islands, IR drop, temperature) 15 % Device fatigue (NBTI, hot electron effects) 10% Vt and Tox device family tracking (Can have multiple Vt and Tox device families) 5% Model/hardware uncertainty (Per cell type) 5% N/P mistrack (Fast rise/slow fall, fast fall/slow rise) 10% PLL (Jitter, duty cycle, phase error) 10% [Courtesy Kerim Kalafala] • Requires 220 timing runs or [-65%,+80%] guard band! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 7 of 80 Can you answer these questions about your favorite digital chip? • What does 5% random delay variability on each gate and wire do to your frequency distribution? • What does 5% correlated delay variability do to your frequency distribution? • What % delay variation leads to a hold violation? • How many yield points does OCV/ACLV cost? • What is the shape of your parametric yield curve? • What is the sensitivity of your chip’s frequency to – – – – thickness of a metal level? gate/wire mistracking? N/P mistracking? mistracking between metal levels i and j? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 8 of 80 New paradigm required • ASICs – old paradigm: sign-off is corner- or case-based – would require 220 timing runs to hit all corners – cumbersome, risky and pessimistic all at the same time! • Microprocessors – for the most part, nominal performance is targeted – some ad hoc methods to deal with certain types of mistracking • Both – our design/synthesis methods do not target robustness, nor do our timing tools measure robustness or give credit for robust design • Solution: statistical timing and optimization © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 9 of 80 ITRS predictions © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 10 of 80 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 11 of 80 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 12 of 80 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 13 of 80 What is a statistical timer? Netlist + assertions Delay and slew models Statistics of the sources of variability Static Statistical timer 1. Yield Slack curve 2. Diagnostics Diagnostics Dependence on sources of variability © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 14 of 80 Parametric yield curve Yield ¢ ¢¢ $ $$ Clock frequency © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 15 of 80 Section 2: The Importance of Correlations … and why they make computations a pain © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 16 of 80 Importance of correlations • Consider a circuit with 50K latches, each with a setup and hold test, each of which has a 99.99% probability of being met • If all tests are perfectly correlated, yield = 99.99% • If all tests are perfectly independent, yield = 0.005% • The truth is closer to the perfectly correlated case! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 17 of 80 Correlation due to path sharing © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 18 of 80 Clock and cell-type correlation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 19 of 80 Voltage island correlation V V V V V V V V V dd1 dd 4 dd7 © Chandu Visweswariah, 2004 dd 2 dd5 dd8 dd3 dd6 dd9 Statistical Analysis and Design: From Picoseconds to Probabilities 20 of 80 Global correlation FFXXUU I S U F P U I S U F P U I D U I D U L S U L S U I F U I F U B X U B X U L 2 L 2 L3Directoy/Cnrl L 2 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 21 of 80 Temperature/Vdd correlation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 22 of 80 Geographical correlation [From M. Orshansky, L. Statistical Milor,Analysis P. Chen, C. Hu, ICCAD 2000] © Chandu Visweswariah, 2004 and Design: K. From Keutzer, Picoseconds to Probabilities 23 of 80 Types of variability • Global within a die/reticle – metal dimensions – device family strength mistracking – ambient temperature and power supply • Spatial/local correlation across a die/reticle – Leff – junction temperature, Vdd • Independently random – tox – doping effects © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 24 of 80 First-cut approach to static timing • Deterministic a • Statistical + c + MAX b a + + c MAX b • Question: what do correlations do to the MAX and PLUS operations? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 25 of 80 1 0.8 Probability The max of two unit Gaussians =0 =0.2 =0.4 =0.6 =0.8 =1.0 Note! 0.6 0.4 0.2 0 -2.0 © Chandu Visweswariah, 2004 Delay -1.0 0.0 1.0 Statistical Analysis and Design: From Picoseconds to Probabilities 2.0 26 of 80 1 0.8 Probability Equally critical signals (=0) 0.6 1 2 3 30 0.4 0.2 0 -3.0 Delay -2.0 © Chandu Visweswariah, 2004 -1.0 0.0 1.0 2.0 Statistical Analysis and Design: From Picoseconds to Probabilities 3.0 27 of 80 1 0.8 Probability Equally critical signals (=0.5) 0.6 1 2 3 30 0.4 0.2 0 -3.0 Delay -2.0 © Chandu Visweswariah, 2004 -1.0 0.0 1.0 2.0 Statistical Analysis and Design: From Picoseconds to Probabilities 3.0 28 of 80 1 0.8 Probability Equally critical signals (=1.0) 0.6 1 2 3 30 0.4 0.2 0 -3.0 Delay -2.0 © Chandu Visweswariah, 2004 -1.0 0.0 1.0 2.0 Statistical Analysis and Design: From Picoseconds to Probabilities 3.0 29 of 80 1 0.8 Probability Thirty equally critical signals 0.6 =1 =0.5 =0 0.4 0.2 0 -3.0 Delay -2.0 © Chandu Visweswariah, 2004 -1.0 0.0 1.0 2.0 Statistical Analysis and Design: From Picoseconds to Probabilities 3.0 30 of 80 tuned #paths Slack histogram +20 ps © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities slack 31 of 80 0.04 0.03 Probability The sum of n unit Gaussians (=1.0) 1 2 3 4 5 6 7 8 9 10 0.02 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 6 Statistical Analysis and Design: From Picoseconds to Probabilities 8 10 32 of 80 0.04 0.03 Probability The sum of n unit Gaussians (=0.5) 1 2 3 4 5 6 7 8 9 10 0.02 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 6 Statistical Analysis and Design: From Picoseconds to Probabilities 8 10 33 of 80 0.04 0.03 Probability The sum of n unit Gaussians (=0) 1 2 3 4 5 6 7 8 9 10 0.02 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 6 Statistical Analysis and Design: From Picoseconds to Probabilities 8 10 34 of 80 Summary: the sum of 10 unit Gaussians =1.0 =0.5 =0.0 Probability 0.02 0.01 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 6 Statistical Analysis and Design: From Picoseconds to Probabilities 8 10 35 of 80 Conventional wisdom revisited • Conventional wisdom says, “Use sizing and multiple Vts to tune the circuit aggressively, creating a wall of critical paths – the new wisdom is to optimize the expected value of the critical path delay, which in turn means reducing the wall of critical paths • Conventional wisdom says, “Make pipeline stages short and crank up clock frequency” – the new wisdom is to take advantage of RMS/ RSS effects in moderately longer pipelines © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 36 of 80 Separating out independent randomness 0.6 New: systematic variability N(20,2/3) 0.5 0.4 Old: N(20,1) 0.3 New: independent variability N(0,1/3) 0.2 0.1 0 17 © Chandu Visweswariah, 2004 18 19 20 21 Statistical Analysis and Design: From Picoseconds to Probabilities 22 37 of 80 Case study • Consider a critical path of 50 identical gates • Old: assume delay of each gate is N(20,1) ps (corner delays are 17 and 23 ps) • New: assume delay of each gate is N(20,2/3) ps + N(0,1/3) ps (same corner delays) • Old: critical path delay (3) = 2350 = 1150 ps • New: critical path delay (3) = 2250 + 31/350 = 1100 + 7.1 = 1107.1 • Improvement in critical path delay = 3.7% • This case study can be generalized © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 38 of 80 Generalization of case study • As N↑, the benefit ↑ • As v↑, the benefit ↑ • As f↑, the benefit ↑ © Chandu Visweswariah, 2004 Rule of thumb: for 50 stages and 5% variability (), each percent of independent variability buys 0.1% of critical path delay improvement Statistical Analysis and Design: From Picoseconds to Probabilities 39 of 80 Plot of benefit for N=50 v=5% v=10% v=15% v=20% v=25% v=0% v=30% 40 35 % benefit 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 f = % independent variability © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 40 of 80 What about shorter paths (=5%)? 10 9 % path delay change 8 7 6 5 4 3 2 1 0 8 10 12 14 16 18 20 22 24 26 28 N = # stages of logic © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 30 f=0% f=5% f=10% f=15% f=20% f=25% f=30% f=35% f=40% f=45% f=50% f=55% f=60% f=65% f=70% f=75% f=80% f=85% f=90% 41 of 80 M equally critical paths • Basic issue – suppose there are M equally critical paths – each of these paths has already received RMS credit, so the delay of each path consists of • a constant which is the nominal/intrinsic delay of the path plus the corner-based systematic variability • an independent variability part for which we have received an RMS credit, so there is a small probability that the delay is beyond the 3 limit – with a large number of equally critical paths, the 3 of the MAX delay of all M paths is not equal to the 3 delay of each of the M paths – question: how big is this sigma shift? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 42 of 80 A little analysis • Example: with M=50, we have to use a 4.037 value on the random part instead of 3 to get a “true 3” delay on the maximum delay of 50 paths; this diminishes RSS credit • The benefit after taking this into account is plotted in general versus M and N on the next page, assuming f=1/3, v=5% © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 43 of 80 Benefit of RMS credit + equally crit. paths N=8 3.6 N=10 N=12 3.4 N=14 N=16 N=18 Percent benefit 3.2 3 N=20 N=22 2.8 N=24 N=26 N=28 2.6 2.4 N=30 N=32 N=34 2.2 Equally critical paths © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 990 920 850 780 710 640 570 500 430 360 290 220 N=40 N=42 N=44 150 1.8 80 N=36 N=38 10 2 N=46 N=48 44 of 80 N=50 Statistical timing experiment N(10,1) N(10,1) N(10,1) Arrival time=0 Data Latch with zero setup guard time Clock N(10,1) N(10,1) N(10,1) Arrival time=0 • How will slack change with ? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 45 of 80 1.0 0.8 Probability Timing experiment result =1 =0.5 =0 0.6 0.4 0.2 Slack 0.0 -7 -6 -5 -4 -3 -2 -1 0 1 © Chandu Visweswariah, 2004 2 3 4 5 Statistical Analysis and Design: From Picoseconds to Probabilities 6 7 46 of 80 There’s no question: correlation’s a pain Of neat math. formulas, it’s the bain! Though your timer becomes a morass It’s correlation that saves your … (chip) © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 47 of 80 Section 3: Statistical Timing Tools … can they rise to the challenge? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 48 of 80 Statistical timing tools • Path-based – conduct a nominal timing analysis – list a representative set of critical paths (question: how may paths? question: which paths?) – model the delay/slack of each path as a function of random variables (the underlying sources of variation) – predict the parametric yield curve (statistical MIN of all path slacks), as well as generate diagnostics • Block-based – propagate arrival times and required arrival times in the form of probability distributions – linear time – approximate, quick-and-dirty © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 49 of 80 Statistical timing tools Path-based Slow and accurate Non-incremental; for sign-off Parameter-space methods More general (usually Monte-Carlo-based) Fabrication-parameter diagnostics © Chandu Visweswariah, 2004 Block-based Quick and dirty Incremental; for (robust) optimization Performance-space methods Assumes symmetry and linearity Criticality probabilities useful to circuit designer Statistical Analysis and Design: From Picoseconds to Probabilities 50 of 80 Feasible region in parameter-space t ox Yield improvement or line-tailoring vector JPDF of global parameters Feasible region • Integration of the JPDF over the feasible region is the parametric yield © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities Leff 51 of 80 Path-based statistical timing Repeated EinsTimer runs Monte Carlo Parallelepi peds © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 68 hours 855 seconds 141 seconds 52 of 80 Block-based statistical timing • Deterministic a + c + MAX b • Statistical a + + c MAX b © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 53 of 80 Canonical variational delay model • Correlations are the problem – in a circuit with 1M nodes and 2M edges and 12 timing values per node/edge, we DO NOT want to store or manipulate a 36M x 36M covariance matrix! – instead, parameterize all timing quantities by the sources of variation – first-order canonical model: a0 a1X1 a2X 2 an X n an1Ra Sensitivities Constant (nominal value) © Chandu Visweswariah, 2004 Deviation of global sources of variation from their nominal values Random uncertainty (deviation from nominal value) Statistical Analysis and Design: From Picoseconds to Probabilities 54 of 80 Procedure • Express all delays, slews, arrival times, required arrival times and slacks in canonical form • Propagate arrival times forward through the timing graph while preserving correlations • Propagate required arrival times backward while preserving correlations • Slack is the difference of arrival and required arrival times • Each path, node and edge has a probability of being critical; these criticality probabilities can be computed easily • All results are also available in canonical form; these diagnostics are extremely useful! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 55 of 80 Interpreting statistical timing results • Critical path is not unique • Critical paths can be listed in order of probability of being critical – this should be the order in which the timing of paths is “fixed” or optimized • In deterministic timing, slack is identical along the critical path • This property does not hold in the case of statistical timing • Slacks reflect not only timing shortfalls, but also robustness shortfalls © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 56 of 80 Probability Latch timing considerations © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 57 of 80 Sample comparison to Monte Carlo Monte Carlo, 14 hours CPU time Block-based statistical timer, 18 seconds CPU time Test chip (3K gates) © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 58 of 80 Overhead of statistical calculations • Run time overhead – about 20% on batch operation – about 50% on the actual arrival time propagation • Memory overhead – about 100% depending on the number of sources of variation and complexity of the models • Capacity – able to time 2M+ gate ASIC chips on 64-bit machines © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 59 of 80 Methods of handling ACLV/OCV • ACLV/OCV is traditionally handled by heuristic derating coefficients – an early/late delay split is applied, and late data is compared to early clock and vice versa • However, we want to give credit to compactly laid out launching/capturing path pairs and penalize path pairs that snake all over the chip • By taking advantage of spatial correlation, we can obtain proximity credit © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 60 of 80 Path-based solution The setup and hold test can be penalized by an early/late split based on the size of this bounding box © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 61 of 80 Block-based solution #1 From A. Agarwal et al, TAU ’02 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 62 of 80 Block-based solution #2 From H. Chang et al, ICCAD ’03 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 63 of 80 Section 4: Robust Design … sure, the process is all over the place, but can I use design techniques to attenuate the effect? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 64 of 80 Remember these? • In addition to correctness, power, signal integrity and area, please welcome robustness to variation as a first-class design metric © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 65 of 80 First order model Robust design P( x, y ) mean p 2 p 2 x 2 x x x2 p p 2 y 2 y y y • Tremendously valuable if the statistical timer produces timing results in 1st order canonical form: Constant (nominal part) © Chandu Visweswariah, 2004 a0 a1X1 a2X 2 an1Ra Sensitivities Global variations Random uncertainty Statistical Analysis and Design: From Picoseconds to Probabilities 66 of 80 Opportunities for robust design • Find out which sources of variation are the biggest yield detractors; quantify robustness of a design • Any commonality between data and clock cancels out to first order – voltage islands, gate types, device types, metal levels used for interconnect, proximity of launching and capturing paths • Robustness-enhancing design decisions – high sensitivity to N/P mistrack resynthesize with fewer tall P stacks, for example – high sensitivity to a particular metal level re-route – high sensitivity to Vt mistrack try to balance use of low/high Vt devices in capturing and launching paths – high sensitivity to wire/gate mistrack try to rebalance delay • Producing timing results in canonical form can help with line tailoring © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 67 of 80 How synthesis techniques will evolve • Phase 1 – true 3 timing sign-off with statistical timing • Phase 2 – use statistical timing to guide the physical synthesis and routing optimization (implicit robustness credit) • Phase 3 – further reduce performance by actively targeting robustness (explicit robustness credit) • Phase 4 – with the mainstream availability of at-speed test, enable yield/performance tradeoffs © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 68 of 80 Section 5: Methodology … will ASICs benefit? processors? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 69 of 80 ASICs vs. microprocessors Microprocessor ASIC Large, less hierarchy Huge, hierarchical Limited abstraction (except for IP blocks on SoCs) No speed binning Requires timing abstraction Library-based Custom circuits + librarybased synthesized macros Focus on worst-case timing with ACLV/OCV penalty Focus on nominal timing © Chandu Visweswariah, 2004 Sorted and binned Statistical Analysis and Design: From Picoseconds to Probabilities 70 of 80 3 BEOL Check front-end corners: possible escapes 2 1 -3 -2 -1 1 2 3 FEOL -1 1 GHz -2 -3 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 71 of 80 3 BEOL Check all corners: no escapes, pessimistic 2 1 -3 -2 -1 1 2 3 FEOL -1 1 GHz -2 -3 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 72 of 80 3 BEOL Statistical timing: no escapes, less pessimism 2 1 -3 -2 -1 1 2 3 FEOL -1 1 GHz -2 -3 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 73 of 80 ASIC timing methodology • • • • Checking “all corners” is very pessimistic Checking “all corners” is intractable Statistical timing fits in “naturally” With the same area/power targets and the same tool suite, but a statistical timer to guide the placement, routing and optimization, the estimated performance improvement is of the order of 20% in 90nm technology • Test coverage can be improved by exploiting statistical timing results • With at-speed test, arbitrary performance vs. yield tradeoffs can be made based on business needs © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 74 of 80 Technology characterization + delay model generation Canonical variational delay model MHC, line tailoring Model-to-hardware correlation and/or line tailoring Statistical timing Path report file with criticality probabilities + process coverage Test vector generation Path sensitivities Correlation analysis and diagnosis At-speed test Good chips © Chandu Visweswariah, 2004 Bad chips with failing path signatures Statistical Analysis and Design: From Picoseconds to Probabilities 75 of 80 Possible microprocessor methodology Individual macros Assertions (Mostly) FEOL variability models Other macros (Mostly) BEOL variability models © Chandu Visweswariah, 2004 Robustness budget Update timing and robustness budgets Statistical timing for optimization “Sign-off” statistical timing and abstraction Global wires Unit or chip-level statistical timing for optimization Unit or chip-level statistical “sign-off” timing Statistical Analysis and Design: From Picoseconds to Probabilities 76 of 80 Probability Vt variations Good chips Too leaky Too slow Vt • Requires simultaneous power/timing sign-off © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 77 of 80 Section 6: Propositions © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 78 of 80 Propositions 1. Variability is proportionately increasing; therefore, a new paradigm is required 2. Correlations matter 3. Statistical timing tools are rising to the challenge 4. Robustness is an important metric 5. Statistical treatment of variability will pervade all aspects of chip design and manufacturing • ASICs and processors will both benefit © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 79 of 80 Quotable quotes* • Statistical thinking will one day be as necessary for efficient (chip-design) citizenship as the ability to read and write. -- H. G. Wells • There are three kinds of lies: lies, damned lies and statistics. -- Disraeli • It ain’t so much the things we don’t know that get us in trouble. It’s the things we know that ain’t so. -- Artemus Ward • Round numbers are always false. -- Samuel Johnson *From “How to Lie with Statistics,” by Darrell Huff, Norton, 1954 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities 80 of 80