CDP1878C CMOS Dual Counter-Timer March 1997 Features Description • Compatible with General Purpose and CDP1800 Series Microprocessor Systems The CDP1878C is a dual counter-timer consisting of two 16bit programmable down counters that are independently controlled by separate control registers. The value in the registers determine the mode of operation and control functions. Counters and registers are directly addressable in memory space by any general industry type microprocessors, in addition to input/output mapping with the CDP1800 series microprocessors. • Two 16-Bit Down Counters and Two 8-Bit Control Registers • 5 Modes Including a Versatile Variable-Duty Cycle Mode • Programmable Gate-Level Select • Two-Complemented Output Pins for Each CounterTimer • Software-Controlled Interrupt Output • Addressable in Memory Space or CDP1800-Series I/O Space Ordering Information PART NUMBER TEMP. RANGE PACKAGE PKG. NO. CDP1878CE -40oC to +85oC PDIP E28.6 CDP1878CD -40oC to +85oC SBDIP N28.6 Each counter-timer can be configured in five modes with the additional flexibility of gate-level control. The control registers in addition to mode formatting, allow software start and stop, interrupt enable, and an optional read control that allows a stable readout from the counters. Each countertimer has software control of a common interrupt output with an interrupt status register indicating which counter-timer has timed out. In addition to the interrupt output, true and complemented outputs are provided for each counter-timer for control of peripheral devices. This type is supplied in 28-lead dual-in-line ceramic packages (D suffix), and 28-lead dual-in-line plastic packages (E suffix). Pinout CDP1878C (DIP) TOP VIEW TABLE 1. MODE DESCRIPTION MODE INT 1 28 VDD TAO 2 27 DB7 TAO 3 26 DB6 TAG 4 25 DB5 TACL 5 24 DB4 RD 6 23 DB3 7 22 DB2 TPB/WR 8 21 DB1 TPA 9 20 DB0 CS 10 19 TBO A0 11 18 TBO A1 12 17 TBG A2 13 16 TBCL IO/MEM VSS 14 15 RESET APPLICATION 1 Timeout Outputs change when clock decrements counter to “0” Event counter 2 Timeout Strobe One clockwide output pulse when clock decrements counter to “0” Trigger pulse 3 Gate-Controlled One Shot Outputs change when clock decrements counter to “0”. Retriggerable Time-delay generation 4 Rate Generator Repetitive clockwide output pulse Time-base generator 5 Variable-Duty Cycle Motor control CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-91 FUNCTION Repetitive output with programmed duty cycle File Number 1341.2 CDP1878C Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1878C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 50 12 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions PARAMETER At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: SYMBOL MIN MAX UNITS 4 6.5 V VSS VDD V tR, tF - 5 µs tWL, tWH 200 - ns fCL DC 1 MHz DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time Minimum Clock Pulse Width Maximum Clock Input Frequency Static Electrical Specifications At TA = -40oC to +85oC, VDD ± 5% Except as noted: CONDITIONS LIMITS SYMBOL VO (V) VIN (V) VDD (V) MIN (NOTE 1) TYP MAX UNITS Quiescent Device Current IDD - 0, 5 5 - 0.02 200 µA Output Low Drive (Sink) Current IOL 0.4 0, 5 5 1.6 3.2 - mA Output High Drive (Source) Current IOH 4.6 0, 5 5 -1.15 -2.3 - mA Output Voltage Low-Level (Note 2) VOL - 0, 5 5 - 0 0.1 V Output Voltage High-Level (Note 2) VOH - 0, 5 5 4.9 5 - V Input Low Voltage VIL 0.5, 4.5 - 5 - - 1.5 V Input High Voltage VIH 0.5, 9.5 - 5 3.5 - - V Input Leakage Current IIN Any Input 0, 5 5 - - ±1 µA Operating Current (Note 3) IDD1 - 0, 5 5 - 1.5 3 mA Input Capacitance CIN - - - - 5 7.5 pF COUT - - - - 10 15 pF PARAMETER Output Capacitance NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. IOL = IOH = 1µA 3. Operating current measured at 200kHz for VDD = 5V, with open outputs (worst-case frequencies for CDP1802A system operating at maximum speed of 3.2MHz). 4-92 CDP1878C Functional Diagram JAM REGISTER A RESET RD TPB/WR IO/MEM TPA CS A2 A1 A0 GATE A I-O CONTROL AND LOGIC COUNTER A CONTROL REGISTER A AND MODE CONTROL TAO TAO CLOCK A HOLDING REGISTER A VDD VSS 8-BIT EXTERNAL BUS INT AND STATUS REGISTER DATA BUS DRIVERS INT JAM REGISTER B GATE B COUNTER B CONTROL REGISTER B AND MODE CONTROL TBO TBO CLOCK B HOLDING REGISTER B FUNCTIONAL DEFINITIONS FOR CDP1878C TERMINALS TERMINAL USAGE TERMINAL USAGE VDD - VSS Power TAO, TAO Complemented outputs of Timer A DB0-DB7 Data to and from device TBO, TBO Complemented outputs of Timer B TPB/WR, RD A0, A1, A2 TACL, TBCL TAG, TBG Directional Control Signals TPA Used with CDP1800-series processors, tied high otherwise Addresses that select counters or registers CS Active high input that enables device Clocks used to decrement counters INT Low when counter is “0” Gate inputs that control counters 4-93 RESET When active, TAO, TBO are low, TAO, TBO are high. Interrupt status register is cleared. IO/MEM Tied high in CDP1800 input/output mode, otherwise tied low CDP1878C REGISTER TRUTH TABLE ADDRESS ACTIVE A2 A1 A0 TPB/WR 1 1 0 X RD REGISTER COUNTER 1 1 0 0 1 0 0 1 0 1 0 0 X Control Register A 1 1 1 X Write Counter B MSB 1 1 1 0 1 1 0 1 1 1 0 1 1 0 0 X 1 0 1 X 0 0 0 Not Used 0 0 1 Not Used Write Counter A MSB X Read Counter A MSB X Write Counter A LSB X Read Counter A LSB X Read Counter B MSB X Write Counter B LSB X Read Counter B LSB X Control Register B Interrupt Status Register Programming Model BUS 7 BUS 7 BUS 0 BUS 0 CONTROL REGISTER CONTROL REGISTER WRITE ONLY WRITE ONLY HOLDING REGISTER LSB JAM REGISTER LSB HOLDING REGISTER LSB JAM REGISTER LSB READ ONLY WRITE ONLY READ ONLY WRITE ONLY HOLDING REGISTER MSB JAM REGISTER MSB HOLDING REGISTER MSB JAM REGISTER MSB COUNTER A REGISTERS COUNTER B REGISTERS BUS 7 X X BUS 0 0 0 0 0 0 READ ONLY TIMER A TIMER B INTERRUPT STATUS REGISTER 4-94 0 CDP1878C Functional DescriptIon (most significant and least significant byte in any order), and then the control register be accessed and loaded with the control word. The trailing edge of the TPB/WR pulse will latch the control word into the control register. The trailing edge of the first clock to occur with gate valid will cause the counter to be jammed with its initial value. The counter will decrement on the trailing edge of succeeding clocks as long as the gate is valid, until it reaches zero. The output levels will then change, and if enabled, the interrupt output will become active and the appropriate timer bit will be set in the interrupt status register. The interrupt output and the interrupt status register can be cleared (to their inactive state) by addressing the control register with the TPB/WR line active For example, if counter A times out, control register A must be accessed to reset the interrupt output high and reset the timer A bit in the status register low. Timer B bit in the status register will be unaffected. The dual counter-timer consists of two programmable 16-bit down counters, separately addressable and controlled by two independent 8-bit control registers. The word in the control register determines the mode and type of operation that the counter-timer performs. Writing to or reading from a counter or register is enabled by selective addressing during a write or read cycle. The data is placed on the data bus by the microprocessor during the write cycle or read from the counter during the read cycle. Data to and from the counters and to the control registers is in binary format. Each counter-timer consists of three parts. The first is the counter itself, a 16-bit down counter that is decremented on the trailing edge of the clock input. The second is the jam register that receives the data when the counter is written to. The word in the control register determines when the jam register value is placed into the counter. The third part is the holding register that places the counter value on the data bus when the counter is read. Read Operation Each counter has a holding register that is continuously being updated by the counter and is accessed when the counter is addressed during read cycles. Counter reads are accomplished by halting the holding register and then reading it, or by reading the holding register directly. If the holding register is read directly, data will appear on the bus if the counters are addressed with the RD line active. However, if the clock decrements the counter between the two read operations (most and least significant byte), an inaccurate value will be read. To preclude this from happening, writing a “1” into bit 6 of the control register and then addressing and reading the counter will result in a stable reading. This operation prevents the holding register from being updated by the counter and does not affect the counter’s operation. When the counter has decremented to zero, three events occur. The first involves the common interrupt output pin that, if enabled, becomes active low. The second is the setting of a bit in the interrupt status register. This register can be read to determine which counter-timer has timed out. The third event is the logic change of the complemented output pins. In addition to the clock input used to decrement the counter, a gate input is available to enable or initiate operation. The counter-timers are independent and can have different mode operations. Write Operation The interrupt status register is read by addressing either control register with the RD line active. A “1” in bit 7 indicates Timer A has timed out and a “1” in bit 6 indicates Timer B has timed out. Bits 0-5 are zeros. The counters and registers are separately addressable and are programmed via the data bus when the chip is selected with the TPB/WR pin active. Normal sequencing requires that the counter jam register be loaded first with the required value Control Register 7 6 5 4 JAM ENABLE 1 = ENABLE 0 = DISABLE 3 2 1 0 GATE LEVEL SELECT 1 = POSITIVE (HIGH) 0 = NEGATIVE (LOW) HOLDING REGISTER CONTROL 1 = FREEZE HOLDING REGISTER 0 = UPDATE CONTINUOUSLY INTERRUPT ENABLE 1 = ENABLE 0 = DISABLE START/STOP CONTROL 1 = START COUNTER 0 = STOP COUNTER MODE SELECT 001 = MODE 1 010 = MODE 2 †011 = MODE 3 100 = MODE 4 101 = MODE 5 †PLUS BIT 7 = 0 Bits 0, 1 and 2 BIT 7 BIT 2 BIT 1 BIT 0 Mode Selects - See Mode Timing Diagrams (Figures 1, 2, 3, 4, and 5). Mode 1 - Timeout - 0 0 1 Mode 2 - Timeout Strobe - 0 1 0 Note: When selecting a mode, the timer outputs TAO and TBO are set low, and TAO and TBO are set high. If bits 0, 1 and 2 are all zero’s when the control register is loaded, no mode is selected, and the counter-timer outputs are unaffected. Issuing mode 6 will cause an indeterminate condition of the counter, issuing mode 7 is equivalent to issuing mode 5. Mode 3 - Gate Controlled One Shot 0 0 1 1 Mode 4 - Rate Generator - 1 0 0 Mode 5 - Variable-Duty Cycle - 1 0 1 No Mode selected. Counter outputs unaffected - 0 0 0 4-95 CDP1878C Bit 3 - Gate Level Select - All modes require an enabling signal on the gate to allow counter operation. This enabling signal is either a level or a pulse (edge). Positive gate level or edge enabling is selected by writing a “1” into this bit and negative (low) enabling is selected when bit 3 is “0”. tion will hold a stable value in the hold register for subsequent read operations. Rewriting a “1” into bit 6 will cause an update in the holding register on the next trailing clock edge. If this location contains a “0”, the holding register will be updated continuously by the value in the counter. Bit 4 - Interrupt Enable - Setting this bit to “1” enables the INT output, and setting it to “0” disables it. When reset, the INT output is at a high level. If the interrupt enable bit in the control register is enabled and the counter decrements to zero, the INT output will go low and will not return high until the counter-timer is reset or the selected control register is written to. Example: If timer B times out, control register B must be accessed to reset the INT output high. If the interrupt enable bit is set to “0”, the counter’s timeout will have no effect on the lNT output. Bit 7 - Jam Enable - When this bit is set to “1 “during a write to the control register, the 16-bit value in the jam register will be available to the counter; TAO and TBO are reset low and TAO and TBO are set high. On the trailing edge of the first input clock signal with the gate valid this value will be latched in the counter, the counter outputs TAO and TBO will be set high and the TAO and TBO will be reset low. Setting bit 7 to “0” will leave the counter value unaffected. This location should be set to “0” any time a write to the control register must be performed without changing the present counter value. If the value in the jam register has not been changed, writing a “1” into bit 7 of the control register with zeros in bits 0,1, and 2 (mode select) will reload the counter with the old value and leave the mode unchanged. If the value in the jam register is changed, then the next write to the control register (with bit 7 a “1”) must include a valid mode select (i.e., at least 1 of the bits 0,1, or 2 must be a ”1”). In mode 5, the variable-duty cycle mode, the lNT pin will become active low when the MSB in the counter has decremented to zero. Bit 5 - Start/Stop Control - This bit controls the clock input to the counter and must be set to “1” to enable it. Writing a “0” into this location will halt operation of the counter. Operation will not resume until the bit is set to “1”. Bit 6 - Holding Register Control - Since the counter may be decrementing during a read cycle, writing a “1” into this loca- In mode 3, the hardware start is enabled by writing a “0” into bit 7. If a “1” is written to bit 7, the timeout will start immediately and mode 3 will resemble mode 1. Mode Descriptions MODE 1 CONTROL REGISTER GATE CONTROL Timeout Selectable High or Low Level Enables Operation X X X X X 0 0 1 BUS 7 BUS 0 Mode 1 After the count is loaded into the jam register and the control register is written to with the jam-enable bit high on the trailing edge of the first clock after the gate is valid, TXO goes high and TXO goes low. The input clock decrements the counter as long as the gate remains valid. When it reaches zero TXO goes low and TXO goes high, and if enabled, the COUNTER VALUE 5 interrupt output is set low. Writing to the counter while it is decrementing has no effect on the counter value unless the control register is subsequently written to with the jamenable bit high. After timeout the counter remains at FFFF unless reloaded. 4 3 2 1 1 0 CLOCK 5 4 3 2 WR CONTROL REGISTER 1 1 STALL COUNTER GATE TXO INT LOAD COUNT = 5 FIGURE 1. TIMEOUT (MODE 1) TIMING WAVEFORMS 4-96 0 FFFF CDP1878C MODE 2 CONTROL REGISTER GATE CONTROL Timeout Strobe Selectable High or Low Level Enables Operation X X X X X 0 1 0 BUS 7 BUS 0 Mode 2 Operation of this mode is the same as mode 1, except the outputs will change for one clock period only and then return COUNTER VALUE 3 2 1 0 2 1 0 3 to the condition of TXO high and TXO low, and the counter is reloaded 3 3 2 1 3 2 1 0 CLOCK 3 SEE NOTE WR CONTROL REGISTER GATE TXO INT LOAD COUNT = 3 FIGURE 2. TIMEOUT STROBE (MODE 2) TIMING WAVEFORMS NOTE: Write to control register with mode selects = 0 MODE 3 CONTROL REGISTER GATE CONTROL Gate Controlled One-Shot Selectable Positive or Negative Going Edge Initiates Operation 0 X X X X 0 1 1 BUS 7 BUS 0 Mode 3 After the jam register is loaded with the required value, the gate edge will initiate this mode. TXO will be set high, and TXO will be set low. The clock will decrement the counter. When zero is reached, TXO will go low and TXO will be high, and the interrupt output will be set low. The counter is retrig- gerable: While the counter is decrementing, a gate edge or write to the control register with the jam-enable bit high, will load the counter with the jam register value and restart the one-shot operation. 3 COUNTER VALUE 2 1 0 3 3 2 CLOCK 3 2 1 0 3 3 WR CONTROL REGISTER GATE TXO INT LOAD COUNT = 3 FIGURE 3. GATE CONTROLLED ONE-SHOT (MODE 3) TIMING WAVEFORMS 4-97 2 1 CDP1878C MODE 4 CONTROL REGISTER Rate Generator X X X X X 1 0 0 BUS 7 GATE CONTROL Selectable High or Low Level Enables Operation BUS 0 Mode 4 A repetitive clock-wide output pulse will be output, with the time between pulses equal to the counter’s value, (trailing edge to leading edge). This model is software started with a write to the control register if the gate level is valid. If the counter is written to while decrementing, the new value will COUNTER VALUE 3 2 not affect the counter’s operation until the present timeout has concluded, unless the control register is written to with the jam-enable bit high. If the gate input (TAG or TBG) is used to start this mode, the first cycle following the gate going true is indeterminate. 1 0 3 2 1 0 3 2 1 0 0 3 N CLOCK 3 2 1 3 N WR CONTROL REGISTER GATE TXO LOAD COUNT = 3 INT FIGURE 4. RATE GENERATORS (MODE 4) TIMING WAVEFORMS MODE 5 CONTROL REGISTER Variable Duty Cycle X X X X X 1 0 1 BUS 7 GATE CONTROL Selectable High or Low Level Enables Operation BUS 0 Mode 5 After the mode is initiated, the outputs will remain at one level until the clock decrements the least significant byte of the counter to N+1. The outputs will then change level and the counter decrements the most significant byte to N+1. The process will then repeat, resulting in a repetitive output 2 COUNTER VALUE with a duty cycle directly controlled by the value in the counter. The output period will be equal to LSB+MSB+2. The interrupt output will become active after the MSB is loaded into the counter and decrements to zero. 1 0 1 0 2 1 0 2 1 0 1 CLOCK 2 1 0 1 0 WR CONTROL REGISTER GATE TXO INT LSB MSB LSB LOAD COUNT LSB = 2 AND MSB = 1 FIGURE 5. VARIABLE-DUTY CYCLE (MODE 5) TIMING WAVEFORMS NOTE: In order to avoid unwanted starts when selecting mode 3 or 4, the gate signal must be set to the opposite level that will be programmed. 4-98 1 CDP1878C Setting the Control Register Function Pin Description The following will illustrate a counter write and subsequent reads that places stable, accurate values on the data bus from the counter-timer. DB7 - DB0 - 8-bit bidirectional bus used to transfer binary information between the microprocessor and the dual counter-timer. The counter is addressed and the required values are loaded with a write operation. The control register is addressed next and loaded with B9H. VDD , VSS - Power and ground for device. BUS 7 1 0 BUS 0 1 1 1 0 0 1 CONTROL REGISTER = B9H MODE 1 SELECTED A0, A1, and A2 - Addresses used to select counters or registers. TPB/WR, RD - Directional signals that determine whether data will be placed on the bus from a counter or the interrupt status register (RD active) (memory mapped), or data on the bus will be placed into a counter or control register (TPB/WR active). The following connections are required between the microprocessor and the counter-timer in the CDP1800series input/output mapping mode. POSITIVE GATE ENABLING REQUIRED LOAD COUNTER WITH JAM REGISTER MICROPROCESSOR COUNTER-TIMER MRD RD TPB TPB/WR TPA TPA N Lines Address Lines and IO/MEM to VDD INTERRUPT OUTPUT ENABLED HOLDING REGISTER CONTINUOUSLY UPDATED BY COUNTER COUNTER START FIGURE 6. The counter will now decrement with each input clock pulse while the gate is valid. Assuming the counter has not decremented to zero and its value is to be read without affecting the counter’s operation, a write to the control register is performed. 78H is loaded into the control register. During an output instruction, data from the memory is strobed into the counter-timer during TPB when RD is active, and latched on TPB’s trailing edge. Data is read from the counter-timer when RD is not active between the trailing edges of TPA and TPB. See Figures 11, 12, and 13. TACL, TBCL - Clocks used to decrement the counter. TAG, TBG - Gate inputs used to control counter. TAO, TAO - Complemented outputs of Timer A. BUS 7 0 1 TBO, TBO - Complemented outputs of Timer B. BUS 0 1 1 1 0 0 INT - Common interrupt output. Active when counter decrements to zero. 0 CONTROL REGISTER = 78H COUNTER VALUE UNAFFECTED UNCHANGED RESET - Active low signal that resets counter outputs (TAO, TBO low, TAO, TBO high). The interrupt output is set high and the status register is cleared. COUNTER OUTPUTS UNAFFECTED IO/MEM - Tied high in CDP1800-series input/output mode, otherwise tied low. FREEZE HOLDING REGISTER FIGURE 7. The counter is addressed and read operations are performed. TPA - Tied to TPA of the CDP1800-series microprocessors. During memory mapping, it is used to latch the high order address bit for the chip select. In the CDP1800 input/output mode, it is used to gate the N lines. When the counter-timer is used with other microprocessors, or when the high order address of the CDP1800-series microprocessors is externally latched, it is connected to VDD . CS - An active high signal that enables the device. 4-99 CDP1878C CLOCK XTAL TACL, TBCL ADDRESS LINES MWR TPB/WR MRD RD TPA TPA MAO A0 MA1 A1 MA2 A2 MA7 GATE INPUTS TBG TAO TAO TIMER OUTPUTS TBO CS VSS IO/MEM INT INT TBO COUNTER - TIMER DB0 - DB7 CDP1802 MEMORY TAG RESET CLEAR DATA BUS FIGURE 8. TYPICAL CDP1802 MEMORY-MAPPED SYSTEM LATCH HIGH-ORDER ADDRESS FOR CS TPA ADDRESS HIGH BYTE LOW BYTE TPB/WR DATA LATCHED DATA FROM CPU TO COUNTER-TIMER VALID DATA FIGURE 9. CDP1800-SERIES MEMORY-MAPPING WRITE CYCLE TIMING WAVEFORMS TPA ADDRESS HIGH BYTE LOW BYTE OUTPUT DRIVERS RD ENABLED DATA FROM COUNTER-TIMER TO CPU DISABLED VALID DATA FIGURE 10. CDP1800-SERIES MEMORY-MAPPING READ CYCLE TIMING WAVEFORMS 4-100 CDP1878C CLOCK XTAL TACL, TBCL ADDRESS LINES TPA TPA MRD RD TPB TPB/WR N0 A0 N1 A1 N2 A2 GATE INPUTS TBG TAO TAO TIMER OUTPUTS CS VDD INT TBO IO/MEM INT TBO COUNTER - TIMER DB0 - DB7 CDP1802 MEMORY TAG RESET CLEAR DATA BUS FIGURE 11. TYPICAL CDP1802 INPUT/OUTPUT-MAPPED SYSTEM TPA RD N LINES DATA LATCHED TPB/WR DATA FROM MEMORY TO COUNTER-TIMER VALID DATA FIGURE 12. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION TPA OUTPUT DRIVERS ENABLED RD OUTPUT DRIVERS DISABLED TPB/WR N LINES DATA FROM COUNTER-TIMER TO MEMORY VALID DATA FIGURE 13. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION 4-101 CDP1878C Dynamic Electrical Specifications at TA = -40 to +85oC, VDD = 5V ± 5%, Input tR, tF = 10ns, CL = 50pF and 1 TTL Load SYMBOL (NOTE 1) MIN (NOTE 2) TYP MAX UNITS Data Access from Address tDA - 350 - ns Read Pulse Width tRD 400 - - ns Data Access from Read tDR - 250 - ns Address Hold after Read tRH 0 - - ns Output Hold after Read tDH 50 - - ns Chip Select Setup to TPA tCS 50 - - ns PARAMETER READ CYCLE TIMES (See Figure 14) NOTES: 1. Time required be a limit device to allow for the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. TPA tCS tRH ADDRESS/CHIP SELECT tRD READ DATA TO CPU tDR tDA tDH FIGURE 14. READ CYCLE TIMING WAVEFORMS 4-102 CDP1878C Dynamic Electrical Specifications at TA = -40 to +85oC, VDD = 5V ± 5%, Input tR, tF = 10ns, CL = 50pF and 1 TTL Load SYMBOL (NOTE 1) MIN (NOTE 2) TYP MAX UNITS Address Setup to Write tAS 150 - - ns Write Pulse Width tWR 150 - - ns Data Setup to Write tDS 200 - - ns Address Hold after Write tAH 50 - - ns Data Hold after Write tWH 50 - - ns Chip Select Setup to TPA tCS 50 - - ns PARAMETER WRITE CYCLE TIMES (See Figure 15) NOTES: 1. Time required by a limit device to allow for the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. TPA tCS tAH ADDRESS/CHIP SELECT tAS tWR WRITE DATA TO COUNTER-TIMER tDS tWH FIGURE 15. WRITE CYCLE TIMING WAVEFORMS C All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-103