HIN232A ® Data Sheet March 13, 2006 High Speed +5V Powered RS-232 Transmitters/Receivers FN4316.12 Features • Meets All RS-232E and V.28 Specifications The HIN232A high-speed RS-232 transmitter/receiver interface circuit meets all ElA high-speed RS-232E and V.28 specifications, and is particularly suited for those applications where ±12V is not available. They require a single +5V power supply and feature onboard charge pump voltage converters which generate +10V and -10V supplies from the 5V supply. • Requires Only 0.1µF or Greater External Capacitors • High Data Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 230kbit/s • Requires Only Single +5V Power Supply • Onboard Voltage Doubler/Inverter • Low Power Consumption (Typ) . . . . . . . . . . . . . . . . . 5mA The drivers feature true TTL/CMOS input compatibility, slew rate-limited output, and 300Ω power-off source impedance. The receivers can handle up to ±30V input, and have a 3kΩ to 7kΩ input impedance. The receivers also feature hysteresis to greatly improve noise rejection. • Multiple Drivers - ±10V Output Swing for +5V lnput - 300Ω Power-Off Source Impedance - Output Current Limiting - TTL/CMOS Compatible Ordering Information • Multiple Receivers - ±30V Input Voltage Range - 3kΩ to 7kΩ Input Impedance - 0.5V Hysteresis to Improve Noise Rejection PART NO. PART MARKING TEMP. RANGE (oC) PACKAGE PKG. DWG. # HIN232ACB 232ACB 0 to 70 16 Ld SOIC M16.3 HIN232ACB-T 232ACB 0 to 70 16 Ld SOIC Tape and Reel M16.3 HIN232ACBZ (See Note) 232ACBZ 0 to 70 16 Ld SOIC (Pb-free) M16.3 HIN232ACBZ-T (See Note) 232ACBZ 0 to 70 16 Ld SOIC Tape and Reel (Pb-free) M16.3 HIN232ACBN 232ACBN 0 to 70 16 Ld SOIC (N) M16.15 HIN232ACBN-T 232ACBN 0 to 70 16 Ld SOIC (N) M16.15 Tape and Reel HIN232ACBNZ (See Note) 232ACBNZ 0 to 70 16 Ld SOIC (N) M16.15 (Pb-free) HIN232ACBNZ-T 232ACBNZ (See Note) 0 to 70 16 Ld SOIC (N) M16.15 Tape and Reel (Pb-free) HIN232ACP HIN232ACP 0 to 70 16 Ld PDIP E16.3 HIN232ACPZ (See Note) 232ACPZ 0 to 70 16 Ld PDIP* (Pb-free) E16.3 • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Any System Requiring High-Speed RS-232 Communication Ports - Computer - Portable, Mainframe, Laptop - Peripheral - Printers and Terminals - Instrumentation, UPS - Modems *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Selection Table PART POWER SUPPLY NUMBER VOLTAGE HIN232A NUMBER OF RS-232 DRIVERS NUMBER OF RS-232 RECEIVERS NUMBER OF 0.1µF EXTERNAL CAPACITORS LOW POWER SHUTDOWN/TTL THREESTATE NUMBER OF RECEIVERS ACTIVE IN SHUTDOWN 2 2 4 Capacitors No/No 0 +5V 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HIN232A Pinout HIN232A (PDIP, SOIC) TOP VIEW C1+ 1 16 VCC V+ 2 15 GND C1- 3 14 T1OUT C2+ 4 13 R1IN C2- 5 12 R1OUT 6 11 T1IN T2OUT 7 10 T2IN V- +5V 16 1 0.1µF 3 4 0.1µF 9 R2OUT R2IN 8 + T1IN T2IN + 5 VCC C1+ C1C2+ C2- +5V TO 10V VOLTAGE INVERTER +10V TO -10V VOLTAGE INVERTER V+ 2 + +5V 400kΩ T1 11 +5V 400kΩ T2 10 14 7 12 0.1µF V- 6 0.1µF T1OUT T2OUT 13 R1IN R1OUT 5kΩ R1 R2OUT + 9 8 R2IN 5kΩ R2 GND 15 Pin Descriptions PIN VCC FUNCTION Power Supply Input 5V ±10%. V+ Internally generated positive supply (+10V nominal). V- Internally generated negative supply (-10V nominal). GND Ground Lead. Connect to 0V. C1+ External capacitor (+ terminal) is connected to this lead. C1- External capacitor (- terminal) is connected to this lead. C2+ External capacitor (+ terminal) is connected to this lead. C2- External capacitor (- terminal) is connected to this lead. TIN Transmitter Inputs. These leads accept TTL/CMOS levels. An internal 400kΩ pull-up resistor to VCC is connected to each lead. TOUT RIN ROUT Transmitter Outputs. These are RS-232 levels (nominally ±10V). Receiver Inputs. These inputs accept RS-232 input levels. An internal 5kΩ pull-down resistor to GND is connected to each input. Receiver Outputs. These are TTL/CMOS levels. 2 HIN232A Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) <VCC < 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . (VCC -0.3V) <V+ < 12V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . -12V < V- < (GND +0.3V) Input Voltages TIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V < VIN < (V+ +0.3V) RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . .(V- -0.3V) < VTXOUT < (V+ +0.3V) ROUT . . . . . . . . . . . . . . . . . (GND -0.3V) < VRXOUT < (V+ +0.3V) Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Classification . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical, Note 1) θJA (oC/W) 16 Ld SOIC (N) Package . . . . . . . . . . . . . . . . . . . . . 105 16 Ld SOIC (W) Package. . . . . . . . . . . . . . . . . . . . . 110 16 Ld PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Package) . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range HIN232ACX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Test Conditions: VCC = +5V ±10%, C1-C4 = 0.1µF; TA = Operating Temperature Range Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 5 10 mA - 0.8 V SUPPLY CURRENTS No Load, TA = 25oC Power Supply Current, ICC LOGIC AND TRANSMITTER INPUTS, RECEIVER OUTPUTS Input Logic Low, VlL TIN 2.0 - - V - 15 200 µA Input Logic High, VlH TIN Transmitter Input Pullup Current, IP TIN = 0V TTL/CMOS Receiver Output Voltage Low, VOL IOUT = 3.2mA - 0.1 0.4 V TTL/CMOS Receiver Output Voltage High, VOH IOUT = -1mA 3.5 4.6 - V -30 - +30 V RECEIVER INPUTS RS-232 Input Voltage Range, VIN 3.0 5.0 7.0 kΩ - 1.2 - V Receiver Input High Threshold, VIN (L-H) VIN = ±3V, TA = 25oC VCC = 5V, TA = 25oC VCC = 5V, TA = 25oC - 1.7 2.4 V Receiver Input Hysteresis, VHYST VCC = 5V 0.2 0.5 1.0 V Receiver Input Impedance, RIN Receiver Input Low Threshold, VIN (H-L) TIMING CHARACTERISTICS Transmitter, Receiver Propagation Delay, tPD Transition Region Slew Rate, SRT RL = 3kΩ, CL = 1000pF, Measured from +3V to -3V or -3V to +3V, (Note 2) 1 Transmitter Switching - 0.5 10 µs 3 20 45 V/µs TRANSMITTER OUTPUTS Output Voltage Swing, TOUT Transmitter Outputs, 3kΩ to Ground ±5 ±9 ±10 V Output Resistance, TOUT VCC = V+ = V- = 0V, VOUT = ±2V 300 - - Ω RS-232 Output Short Circuit Current, ISC TOUT Shorted to GND - ±10 - mA Human Body Model - ±15 - kV IEC1000-4-2 Contact Discharge - ±8 - kV IEC1000-4-2 Air Gap (Note 3) - ±15 - kV Human Body Model - ±2 - kV ESD PERFORMANCE RS-232 Pins (TOUT, RIN) All Other Pins NOTES: 2. Guaranteed by design. 3. Meets level 4. 3 HIN232A Test Circuits (HIN232A) +4.5V TO +5.5V INPUT 2 V+ + + 0.1µF C1 1 C1+ - 0.1µF C3 - 0.1µF + C2 - - + 0.1µF C4 3kΩ 1 C1+ VCC 16 2 V+ GND 15 3 C13kΩ VCC 16 GND 15 T1OUT 14 4 C2+ R1IN 13 5 C2- R1OUT 12 3 C1- T1OUT 14 4 C2+ R1IN 13 RS-232 ±30V INPUT 6 V- T1IN 11 5 C2- R1OUT 12 TTL/CMOS OUTPUT 7 T2OUT T2IN 10 8 R2IN T1 OUTPUT 6 V- T1IN 11 TTL/CMOS INPUT 7 T2OUT T2IN 10 TTL/CMOS INPUT 8 R2IN TTL/CMOS OUTPUT R2OUT 9 ROUT = VIN /I T2 OUTPUT R2OUT 9 T2OUT T1OUT RS-232 ±30V INPUT VIN = ±2V FIGURE 2. POWER-OFF SOURCE RESISTANCE CONFIGURATION FIGURE 1. GENERAL TEST CIRCUIT VOLTAGE DOUBLER S1 VOLTAGE INVERTER S2 C1+ A V+ = 2VCC S5 C2+ S6 VCC GND + - + C1 - + C3 VCC GND C1- S3 S4 + C2 - GND C4 V- = - (V+) S7 C2- S8 RC OSCILLATOR FIGURE 3. CHARGE PUMP Detailed Description The HIN232A is a high-speed RS-232 transmitter/receiver that is powered by a single +5V power supply, features low power consumption, and meets all ElA RS232C and V.28 specifications. The circuit is divided into three sections: the charge pump, transmitter, and receiver. Charge Pump An equivalent circuit of the charge pump is illustrated in Figure 3. The charge pump contains two sections: The voltage doubler and the voltage inverter. Each section is driven by a two phase, internally generated clock to generate +10V and -10V. The nominal clock frequency is 125kHz. During phase one of the clock, capacitor C1 is charged to VCC . During phase two, the voltage on C1 is added to VCC , producing a signal across C3 equal to twice VCC . During phase two, C2 is also charged to 2VCC , and then during phase one, it is inverted with respect to ground to produce a signal across C4 equal to -2VCC . The charge pump accepts input voltages up to 5.5V. The output impedance of the 4 voltage doubler section (V+) is approximately 200Ω, and the output impedance of the voltage inverter section (V-) is approximately 450Ω. A typical application uses 0.1µF capacitors for C1-C4, however, the value is not critical. Increasing the values of C1 and C2 will lower the output impedance of the voltage doubler and inverter, increasing the values of the reservoir capacitors, C3 and C4, lowers the ripple on the V+ and V- supplies. Transmitters The transmitters are TTL/CMOS compatible inverters which translate the inputs to RS-232 outputs. The input logic threshold is about 26% of VCC, or 1.3V for VCC = 5V. A logic 1 at the input results in a voltage of between -5V and V- at the output, and a logic 0 results in a voltage between +5V and (V+ -0.6V). Each transmitter input has an internal 400kΩ pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RS-232C specifications of ±5V minimum with the worst case conditions of: all transmitters driving 3kΩ minimum load HIN232A impedance, VCC = 4.5V, and maximum allowable operating temperature. The transmitters have an internally limited output slew rate which is less than 30V/µs. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a minimum of 300Ω with ±2V applied to the outputs and VCC = 0V. TIN OR RIN TOUT OR ROUT Receivers The HIN232A may be used for all RS-232 data terminal and communication links. It is particularly useful in applications where ±12V power supplies are not available for conventional RS-232 interface circuits. The applications presented represent typical interface configurations. 300Ω TOUT GND < TXIN < VCC V- < VTOUT < V+ In applications requiring four RS-232 inputs and outputs (Figure 8), note that each circuit requires two charge pump capacitors (C1 and C2) but can share common reservoir capacitors (C3 and C4). The benefit of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. V- FIGURE 4. TRANSMITTER VCC ROUT GND < VROUT < VCC GND FIGURE 5. RECEIVER +5V + 16 1 C1 + 0.1µF - 3 HIN232A 6 4 C2 + 0.1µF TD INPUTS OUTPUTS TTL/CMOS RTS 5 + T1 11 14 T2 10 7 13 12 RD CTS 9 R2 R1 15 8 CTR (20) DATA TERMINAL READY DSRS (24) DATA SIGNALING RATE SELECT RS-232 INPUTS AND OUTPUTS TD (2) TRANSMIT DATA RTS (4) REQUEST TO SEND RD (3) RECEIVE DATA CTS (5) CLEAR TO SEND SIGNAL GROUND (7) FIGURE 7. SIMPLE DUPLEX RS-232 PORT WITH CTS/RTS HANDSHAKING 5 2 A simple duplex RS-232 port with CTS/RTS handshaking is illustrated in Figure 7. Fixed output signals such as DTR (data terminal ready) and DSRS (data signaling rate select) is generated by driving them through a 5kΩ resistor connected to V+. TXIN 5kΩ tPHL + tPLH Application Information VCC RXIN tPLH FIGURE 6. PROPAGATION DELAY DEFINITION V+ -30V < RXIN < +30V VOL tPHL AVERAGE PROPAGATION DELAY = The receiver inputs accept up to ±30V while presenting the required 3kΩ to 7kΩ input impedance even if the power is off (VCC = 0V). The receivers have a typical input threshold of 1.3V which is within the ±3V limits, known as the transition region, of the RS-232 specifications. The receiver output is 0V to VCC. The output will be low whenever the input is greater than 2.4V and high whenever the input is floating or driven between +0.8V and -30V. The receivers feature 0.5V hysteresis (except during shutdown) to improve noise rejection. 400kΩ VOH HIN232A 1 C1 + 0.1µF TD INPUTS OUTPUTS TTL/CMOS RTS 4 HIN232A 3 T1 11 14 T2 10 + C2 - 0.1µF 5 TD (2) TRANSMIT DATA 7 RTS (4) REQUEST TO SEND 13 12 RD (3) RECEIVE DATA RD R2 9 CTS R1 8 CTS (5) CLEAR TO SEND 15 VCC 16 - 2 C3 + + C4 6 V- V+ 0.2µF RS-232 INPUTS AND OUTPUTS 0.2µF 2 6 +5V - 16 VCC HIN232A C1 + 0.1µF DTR INPUTS OUTPUTS TTL/CMOS DSRS 1 4 3 5 T1 11 14 T2 10 7 13 12 DCD R1 R2 9 R1 15 8 + C2 - 0.1µF DTR (20) DATA TERMINAL READY DSRS (24) DATA SIGNALING RATE SELECT DCD (8) DATA CARRIER DETECT R1 (22) RING INDICATOR SIGNAL GROUND (7) FIGURE 8. COMBINING TWO HIN232As FOR 4 PAIRS OF RS-232 INPUTS AND OUTPUTS Typical Performance Curves 12 0.1µF SUPPLY VOLTAGE (V) V- SUPPLY VOLTAGE (V) 12 10 8 6 4 V+ (VCC = 5V) 8 6 V+ (VCC = 4V) V- (VCC = 4V) 4 TA = 25oC TRANSMITTER OUTPUTS OPEN CIRCUIT 2 2 0 3.0 10 3.5 4.0 4.5 5.0 5.5 VCC FIGURE 9. V- SUPPLY VOLTAGE vs VCC 6 6.0 0 0 5 10 15 V- (VCC = 5V) 20 25 30 |ILOAD| (mA) FIGURE 10. V+, V- OUTPUT VOLTAGE vs LOAD 35 HIN232A Die Characteristics DIE DIMENSIONS 160 mils x 140 mils METALLIZATION Type: Al Thickness: 10kÅ ±1kÅ SUBSTRATE POTENTIAL V+ PASSIVATION Type: Nitride over Silox Nitride Thickness: 8kÅ Silox Thickness: 7kÅ TRANSISTOR COUNT 238 PROCESS CMOS Metal Gate 7 HIN232A Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 18.66 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC eB - 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 N 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 8 5 E 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 0.355 19.68 D1 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 0.204 16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 16 6 7 4 9 Rev. 0 12/93 HIN232A Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N INDEX AREA 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE H 0.25(0.010) M B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e α B S 0.050 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 9 - 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 16 0° 16 8° 0° 7 8° Rev. 1 6/05 HIN232A Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INCHES INDEX AREA H 0.25(0.010) M B M SYMBOL E -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e B 0.25(0.010) M C 0.10(0.004) C A M B S MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 - D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4 e µα A1 MIN 0.050 BSC 1.27 BSC - H 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 16 0o 16 7 8o Rev. 1 02/02 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 10