UNISONIC TECHNOLOGIES CO., LTD L8001 Preliminary CMOS IC FET BIAS CONTROLLER DESCRIPTION The UTC L8001 is specially designed integrated circuit for satellite receiver front-end block. It provides stable drain and gate bias conditions for GaAs or HEMT FETs. The UTC L8001, provide six FETs bias control respectively. By adjusting two external resistors, it can change the FET’s bias current to optimize the satellite receiver front end block performances. It generates the required negative voltage to bias the gate of GaAs FET, and internally provides protection circuit that can protect the FET devices during supply voltage transient. So it is very popular in satellite receiver front end block. FEATURES * Built in FET device protection circuit * Adjustable FET device operating current * Stable bias control for GaAs and HEMT FETs * Drive up to six FETs * Wide supply voltage range ORDERING INFORMATION Ordering Number L8001G-R20-R Package SSOP-20 Packing Tape Reel L8001G-R20-R (1)Packing Type (1) R: Tape Reel (2)Package Type (2) SSOP-20 (3)Green Package (3) G: Halogen Free and Lead Free www.unisonic.com.tw Copyright © 2016 Unisonic Technologies Co., Ltd 1 of 6 QW-R502-938.c L8001 Preliminary CMOS IC PIN CONFIGURATION VD1 1 20 VCC VG1 2 19 VD4 VD2 3 18 VG4 VG2 4 17 VD5 VD3 5 16 VG5 VG3 6 15 VD6 GND 7 14 VG6 NC 8 13 RCAL2 CNB1 9 12 RCAL1 CNB2 10 11 CSUB PIN DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME VD1 VG1 VD2 VG2 VG3 VD3 GND NC CNB1 CNB2 CSUB RCAL1 RCAL2 VG6 VD6 VG5 VD5 VG4 VD4 VCC DESCRIPTION 1st Drain output voltage 1st Gate output voltage 2nd Drain output voltage 2nd Gate output voltage 3rd Gate output voltage 3rd Drain output voltage Ground No connect OSC output Rectifier Input Negative voltage output VD1/VD2/VD3 current set resistor connect VD4/VD5/VD6 current set resistor connect 6th Gate output voltage 6th Drain output voltage 5th Gate output voltage 5th Drain output voltage 4th Gate output voltage 4th Drain output voltage Supply voltage UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 6 QW-R502-938.c L8001 Preliminary CMOS IC BLOCK DIAGRAM UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 6 QW-R502-938.c L8001 Preliminary CMOS IC ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT Supply Voltage VCC -0.6 ~ 8 V Supply Current ICC 100 mA Maximum Drain Current 15 mA Maximum CSUB Sink Current -500 uA Operating Temperature TOPR -40 ~ 80 °C Storage Temperature TSTG -50 ~ 150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. ELECTRICAL CHARACTERISTICS (VCC=3.3V, ID=10mA, RCAL1=8.2KΩ, RCAL2=8.2KΩ, TA=25°C, unless otherwise stated) PARAMETER Supply Voltage Supply Current Negative Voltage Oscillator Freq. Drain Current Drain Current Change with VCC VD1/VD2(VD3/VD4) Drain Offset Current Drain Current Change with Temp. Drain Voltage Drain Voltage Change with VCC Drain Voltage Change Dynamic Gate Voltage Range Drain Output Noise Voltage Gate Output Noise Voltage SYMBOL TEST CONDITIONS VCC ICC No FET ISUB=0uA, VCC=6V VSUB ISUB=-200uA fO ID ∆IDV VCC=3.3~6V UNIT V mA V V KHz mA %/V 0.2 mA ∆IDC ∆IDT VD ∆VDV ∆VDT VG Vdn VGN T=-40~80°C ID=10mA VCC=3.3~6V T=-40~80°C Csub without loading With drain bypass capacitor=10nF With gate bypass capacitor=10nF UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN TYP MAX 3.3 6 10 -3.0 -2.5 -1 -1 200 350 800 8 10 12 0.2 1.8 -2.5 0.1 2 0.5 50 %/°C V %/V ppm 0.7 V 0.05 VPP 0.03 VPP 2.2 4 of 6 QW-R502-938.c L8001 Preliminary CMOS IC TYPICAL APPLICATION CIRCUIT There are three major functions provided by L8001G: support negative voltage, bias control circuit, and FET protesting circuit. The negative voltage is generated using internal oscillator. It only needs an ac coupled capacitor CNB 47nF and a negative voltage bypass capacitor CSUB 47nF. The bias control circuit is used to establish a stable bias current for FETs. It’s bias current can be adjusted by external resistor Rcal.Rcal1 resistor is used to set ID1, ID2, ID3 in L8001G. Rcal2 resistor is used to set ID4, ID5, ID6 in L8001G. if the same drain current is required for all FETs then pins Ical1 and Ical2 can be wired together and shunted to ground by a single resistor of half normal value. The L8001G devices have been designed to protect the external FETs from adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -2.5V to 0.7V, under any conditions including powerup and powerdown transients. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current. The following diagrams show the L8001G in typical LNB applications. Within each FET gain stage the numbering system indicates how the bias stages relate to the application circuits. This is important when RCAL values are used to set differing drain currents. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 6 QW-R502-938.c L8001 Preliminary CMOS IC TYPICAL APPLICATION CIRCUIT UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 6 QW-R502-938.c