CA3083 Data Sheet September 1998 File Number 481.4 General Purpose High Current NPN Transistor Array Features The CA3083 is a versatile array of five high current (to 100mA) NPN transistors on a common monolithic substrate. In addition, two of these transistors (Q1 and Q2) are matched at low current (i.e., 1mA) for applications in which offset parameters are of special importance. • Low VCE sat (at 50mA) . . . . . . . . . . . . . . . . . . 0.7V (Max) • High IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Max) Independent connections for each transistor plus a separate terminal for the substrate permit maximum flexibility in circuit design. Ordering Information PART NUMBER (BRAND) TEMP. RANGE (oC) PKG. NO. PACKAGE • Matched Pair (Q1 and Q2) - VIO (VBE Match) . . . . . . . . . . . . . . . . . . . . ±5mV (Max) - IIO (at 1mA). . . . . . . . . . . . . . . . . . . . . . . . 2.5µA (Max) • 5 Independent Transistors Plus Separate Substrate Connection Applications • Signal Processing and Switching Systems Operating from DC to VHF • Lamp and Relay Driver CA3083 -55 to 125 16 Ld PDIP E16.3 • Differential Amplifier CA3083M (3083) -55 to 125 16 Ld SOIC M16.15 • Temperature Compensated Amplifier CA3083M96 (3083) -55 to 125 16 Ld SOIC Tape and Reel M16.15 Pinout • Thyristor Firing • See Application Note AN5296 “Applications of the CA3018 Circuit Transistor Array” for Suggested Applications CA3083 (PDIP, SOIC) TOP VIEW 16 1 2 3 15 Q1 14 Q2 13 4 SUBSTRATE Q5 5 12 11 6 Q3 7 Q4 10 9 8 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CA3083 Absolute Maximum Ratings Thermal Information The following ratings apply for each transistor in the device: Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . 20V Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . . . 20V Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Base Current (IB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 135 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 200 N/A Maximum Power Dissipation (Any One Transistor) . . . . . . . 500mW Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3083 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors, the substrate Terminal (5) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. 2. θJA is measured with the component mounted on an evaluation PC board in free air. For Equipment Design, TA = 25oC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS FOR EACH TRANSISTOR Collector-to-Base Breakdown Voltage V(BR)CBO IC = 100µA, IE = 0 20 60 - V Collector-to-Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 15 24 - V Collector-to-Substrate Breakdown Voltage V(BR)CIO ICI = 100µA, IB = 0, IE = 0 20 60 - V Emitter-to-Base Breakdown Voltage V(BR)EBO IE = 500µA, IC = 0 5 6.9 - V Collector-Cutoff-Current ICEO VCE = 10V, IB = 0 - - 10 µA Collector-Cutoff-Current ICBO VCB = 10V, IE = 0 - - 1 µA DC Forward-Current Transfer Ratio (Note 3) (Figure 1) hFE VCE = 3V IC = 10mA 40 76 - IC = 50mA 40 75 - Base-to-Emitter Voltage (Figure 2) VBE VCE = 3V, IC = 10mA 0.65 0.74 0.85 V VCE SAT IC = 50mA, IB = 5mA - 0.40 0.70 V fT VCE = 3V, IC = 10mA - 450 - MHz Absolute Input Offset Voltage (Figure 6) |VIO| VCE = 3V, IC = 1mA - 1.2 5 mV Absolute Input Offset Current (Figure 7) |IIO| VCE = 3V, IC = 1mA - 0.7 2.5 µA Collector-to-Emitter Saturation Voltage (Figures 3, 4) Gain Bandwidth Product FOR TRANSISTORS Q1 AND Q2 (As a Differential Amplifier) NOTE: 3. Actual forcing current is via the emitter for this test. 2 CA3083 100 0.9 VCE = 3V VCE = 3V 90 BASE-TO-EMITTER VOLTAGE (V) DC FORWARD CURRENT TRANSFER RATIO Typical Performance Curves TA = 70oC TA = 25oC 80 TA = 0oC 70 60 1 10 COLLECTOR CURRENT (mA) TA = 25oC 0.7 TA = 70oC 0.6 0.5 0.1 50 0.1 TA = 0oC 0.8 100 FIGURE 1. hFE vs IC 1.2 hFE = 10, TA = 25oC hFE = 10, TA = 70oC 0.8 0.6 0.4 MAXIMUM 0.2 1 0.8 0.6 0.4 0 1 10 1 BASE-TO-EMITTER SATURATION VOLTAGE (V) hFE = 10, TA = 25oC 0.9 0.8 0.7 0.6 0.5 FIGURE 5. VBE SAT vs IC 3 10 COLLECTOR CURRENT (mA) 100 FIGURE 4. VCE SAT vs IC ABSOLUTE INPUT OFFSET VOLTAGE (mV) FIGURE 3. VCE SAT vs IC 10 COLLECTOR CURRENT (mA) TYPICAL 0 100 COLLECTOR CURRENT (mA) 1 MAXIMUM 0.2 TYPICAL 1 100 FIGURE 2. VBE vs IC COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) 1 1 10 COLLECTOR CURRENT (mA) 100 6 VCE = 3V, TA = 25oC 5 4 3 2 1 0 0.1 1 COLLECTOR CURRENT (mA) FIGURE 6. VIO vs IC (TRANSISTORS Q1 AND Q2 AS A DIFFERENTIAL AMPLIFIER) 10 CA3083 ABSOLUTE INPUT OFFSET CURRENT (µA) Typical Performance Curves (Continued) 10 VCE = 3V, TA = 25oC 1 0.1 0.1 1 COLLECTOR CURRENT (mA) 10 FIGURE 7. IIO vs IC (TRANSISTORS Q1 AND Q2 AS A DIFFERENTIAL AMPLIFIER) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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