INTERSIL EL1881CN

EL1881
®
October 20, 2004
Data Sheet
FN7018.1
Sync Separator, Low Power
Features
The EL1881 video sync separator is manufactured using
Elantec’s high performance analog CMOS process. This
device extracts sync timing information from both standard
and non-standard video input. It provides composite sync,
vertical sync, burst/back porch timing, and odd/even field
detection. Fixed 70mV sync tip slicing provides sync edge
detection when the video input level is between 0.5VP-P and
-2VP-P (sync tip amplitude 143mV to 572mV). A single
external resistor sets all internal timing to adjust for various
video standards. The composite sync output follows video in
sync pulses and a vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical preequalizing string. For non-standard vertical inputs, a default
vertical pulse is output when the vertical signal stays low for
longer than the vertical sync default delay time. The
odd/even output indicates field polarity detected during the
vertical blanking interval. The EL1881 is plug-in compatible
with the industry-standard LM1881 and can be substituted
for that part in 5V applications with lower required supply
current.
• NTSC, PAL, SECAM, non-standard video sync separation
The EL1881 is available in the 8-pin PDIP and SO packages
and is specified for operation over the full -40°C to +85°C
temperature range.
PKG.
DWG. #
PACKAGE
TAPE & REEL
EL1881CN
8-Pin PDIP
-
MDP0031
EL1881CS
8-Pin SO
-
MDP0027
EL1881CS-T7
8-Pin SO
7”
MDP0027
EL1881CS-T13
8-Pin SO
13”
MDP0027
EL1881CSZ
(See Note)
8-Pin SO
(Pb-free)
-
MDP0027
EL1881CSZ-T7
(See Note)
8-Pin SO
(Pb-free)
7”
MDP0027
EL1881CSZ-T13
(See Note)
8-Pin SO
(Pb-free)
13”
MDP0027
• Single +5V supply
• Composite, vertical sync output
• Odd/even field output
• Burst/back porch output
• Available in 8-pin PDIP and SO packages
• Pb-free available
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High-speed communications
• Broadcast equipment
• Active filtering
Demo Board
A dedicated demo board is available.
Pinout
EL1881
(8-PIN PDIP, SO)
TOP VIEW
COMPOSITE SYNC OUT 1
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
1
• Low supply current - 1.5mA typ.
• RGB applications
Ordering Information
PART NUMBER
• Fixed 70mV slicing of video input levels from 0.5VP-P to
2VP-P
8
VDD 5V
COMPOSITE VIDEO IN 2
7 ODD/EVEN OUTPUT
VERTICAL SYNC OUT 3
6
GND
4
RSET
5 BUST/BACK
PORCH OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL1881C
Absolute Maximum Ratings (TA = 25°C)
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VDD = 5V, TA = 25°C, RSET = 681kΩ, unless otherwise specified.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
IDD, Quiescent
VDD = 5V
0.75
1.5
3
mA
Clamp Voltage
Pin 2, ILOAD = -100µA
1.35
1.5
1.65
V
Clamp Discharge Current
Pin 2 = 2V
6
12
16
µA
Clamp Charge Current
Pin 2 = 1V
-1.3
-1
0.7
mA
RSET Pin Reference Voltage
Pin 6
1.1
1.22
1.35
V
VOL Output Low Voltage
IOL = 1.6mA
0.24
0.5
V
VOH Output High Voltage
IOH = -40µA
4
4.8
IOH = -1.6mA
3
4.6
MIN
TYP
MAX
UNIT
V
Dynamic Specifications
PARAMETER
DESCRIPTION
Comp Sync Prop Delay, tCS
See Figure 2
20
35
75
ns
Vertical Sync Width, tVS
Normal or Default Trigger, 50%-50%
190
230
300
µs
Vertical Sync Default Delay, tVSD
See Figure 3
35
62
85
µs
Burst/Back Porch Delay, tBD
See Figure 2
120
200
300
ns
Burst/Back Porch Width, tB
See Figure 2
2.5
3.5
4.5
µs
Input Dynamic Range
Video Input Amplitude to Maintain 50% Slice Spec
0.5
2
VP-P
Slice Level
VSLICE/VCLAMP
55
85
mV
2
70
FN7018.1
EL1881C
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
Composite Sync
Out
Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge
2
Composite Video
In
AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)
3
Vertical Sync Out
Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period
4
GND
Supply ground
5
Burst/Back Porch
Output
Burst/back porch output; low during burst portion of composite video
6
RSET (Note 1)
An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for
NTSC signals
7
Odd/Even Output
Odd/even field output; high during odd fields, low during even fields; transitions occur at start of vert sync
pulse
8
VDD 5V
Positive supply (5V)
NOTE:
1. RSET must be a 1% resistor
3
FN7018.1
EL1881C
Typical Performance Curves
1.65
Supply Current vs Temperature
RSET=681kΩ
5.5V
5.5V
1.6
1.525
5V
1.55
VCLAMP (V)
Supply Current (mA)
1.535
VCLAMP Voltage vs Temperature
RSET=681kΩ
4.5V
1.5
1.45
5V
4.5V
1.515
1.505
1.495
1.4
1.35
-50
-25
25
0
50
75
1.485
-50
100
-25
0
Temperature (°C)
Clamp Discharge Current vs Temperature
RSET=681kΩ
1.24
11.3
5.5V
5V
4.5V
11
75
100
4.5V
1.22
1.215
1.21
10.8
1.205
10.7
-50
-25
0
25
50
75
1.2
-50
100
-25
0
Clamp Charge Current vs Temperature
RSET=681kΩ
1.05
50
RSET vs Horizontal Frequency
1000
800
RSET (kΩ)
5.5V
1
5V
4.5V
0.95
0.9
0.85
-50
25
Temperature (°C)
Temperature (°C)
Clamp Charge Current (mA)
100
5V
1.225
10.9
1.1
75
5.5V
1.23
11.2
11.1
50
VRSET vs Temperature
RSET=681kΩ
1.235
VRSET (V)
Clamp Discharge Current (µA)
11.4
25
Temperature (°C)
600
400
200
-25
0
25
50
Temperature (°C)
4
75
100
0
10
15
20
25
30
35
40
45
Frequency (kHz)
FN7018.1
EL1881C
Typical Performance Curves
Burst/Back Porch Width vs RSET
VDD=5V, TA=25°C
350
Burst/Back Porch Delay (ns)
6
(Continued)
Burst Width (µS)
5
4
3
2
1
200
400
600
800
Burst/Back Porch Delay vs RSET
VDD=5V, TA=25°C
300
250
200
150
100
50
0
200
1000
400
600
RSET (kΩ)
Vertical Sync Width vs RSET
VDD=5V, TA=25°C
120
Vertical Sync Default Delay (µS)
350
Vertical Sync Width (µS)
300
250
200
150
100
50
0
200
400
600
80
60
40
20
0
200
1000
800
100
400
600
800
1000
RSET (kΩ)
Composite Sync Prop Delay vs Temperature
Burst/Back Porch Width vs Temperature
3.9
Burst/Back Porch Width (µS)
41
Composite Sync Prop Delay (ns)
1000
Vertical Default Delay vs RSET
VDD=5V, TA=25°C
RSET (kΩ)
39
37
35
33
31
-50
800
RSET (kΩ)
-25
0
25
50
Temperature (°C)
5
75
100
3.8
3.7
3.6
5.5V
3.5
5V
3.4
4.5V
3.3
3.2
3.1
-50
-25
0
25
50
75
100
Temperature (°C)
FN7018.1
EL1881C
Typical Performance Curves
Burst/Back Porch Delay vs Temperature
RSET=681kΩ
239
5.5V
Vertical Sync Pulse Width (µs)
Burst/Back Porch Delay (ns)
250
(Continued)
200
150
5V
4.5V
100
50
0
-50
-25
25
0
75
50
Vertical Sync Pulse Width vs Temperature
RSET=681kΩ
5.5V
237
5V
235
233
4.5V
231
229
-50
100
0
-25
64.5
Vertical Sync Default Delay Time vs Temperature
RSET=681kΩ
63.5
5.5V
62.5
5V
61.5
4.5V
20
-25
0
25
50
75
16
5V
14
5.5V
10
-50
100
-25
0
50
75
100
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity
1.4
1.2
Power Dissipation (W)
4.5V
23
25
Temperature (°C)
25
tCS-OE (ns)
100
12
Composite Sync to Odd/Even Delay Time
RSET=681kΩ
5V
21
19
5.5V
17
15
-50
75
4.5V
Temperature (°C)
27
50
Composite Sync to Vertical Sync Delay Time
RSET=681kΩ
18
60.5
59.5
-50
25
Temperature (°C)
tCS-VS (ns)
Vertical Sync Default Delay Time (µS)
Temperature (°C)
1.25W
Θ
PD
IP
8
10
0°
C/
JA
=
1
0.8
781mW
Θ
0.6
JA =
0.4
SO
8
16
0
°C
/
0.2
0
-25
0
25
50
Temperature (°C)
6
75
100
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
FN7018.1
EL1881C
Timing Diagrams
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a
propagation delay.
d. Odd-even output is low for even field, and high for odd field.
e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note
that for serration pulses during vertical, the back porch starts on the rising edge of the serration
pulse (with propagation delay).
* Signal 1a drawing reproduced with permission from EIA.
FIGURE 1. STANDARD (NTSC INPUT) TIMING
7
FN7018.1
EL1881C
Expanded Timing Diagrams
FIGURE 2. STANDARD VERTICAL TIMING
FIGURE 3. NON-STANDARD VERTICAL TIMING
8
FN7018.1
EL1881C
FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL
Applications Information
Video In
A simplified block diagram is shown following page.
An AC coupled video signal is input to Video In pin 2 via, C1
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about
1mA. A clamp discharge current of about 10µA is always
attempting to discharge C1 to Sync Tip Ref, thus charge is
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from IT = CV, where V is the droop voltage, I is the discharge
current, T is the time between sync pulses (sync period sync tip width), and C is C1.
An NTSC video signal has a horizontal frequency of
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time T = 58.9µs. The droop voltage will then
9
be V = 5.9mV. This is less than 2% of a nominal sync tip
amplitude of 286mV. The charge represented by this droop
is replaced in a time given by T = CV/I, where I = clamp
charge current = 1mA. Here T = 590ns, about 12% of the
sync pulse width of 4.7µs. It is important to choose C1 large
enough so that the droop voltage does not approach the
switching threshold of the internal comparator.
Fixed Gain Buffer
The clamped video signal then passes to the fixed gain
buffer which places the sync slice level at the equivalent
level of 70mV above sync tip. The output of this buffer is
presented to the comparator, along with the slice reference.
The comparator output is level shifted and buffered to TTL
levels, and sent out as Composite Sync to pin 1.
Burst
A low-going Burst pulse follows each rising edge of sync,
and lasts approximately 3.5µs for an RSET of 681kΩ.
FN7018.1
EL1881C
Vertical Sync
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the EL1881 on the first rising edge during the vertical
serration phase. In the absence of vertical serration pulses,
a vertical sync pulse will be forced out after the vertical sync
default delay time, approximately 60µS after the last falling
edge of the vertical equalizing phase for RSET = 681kΩ.
Odd/Even
Because a typical television picture is composed of two
interlaced fields, there is an odd field that includes all the
odd lines, and an even field that consists of the even lines.
This odd/even field information is decoded by the EL1881
during the end of picture information and the beginning of
vertical information. The odd/even circuit includes a T-flipflop that is reset during full horizontal lines, but not during
half lines or vertical equalization pulses. The T-flip-flop is
clocked during each falling edge of these half hperiod
pulses. Even fields will toggle until a low state is clocked to
the odd/even pin 7 at the beginning of vertical sync, and odd
fields will cause a high state to be clocked to the odd/even
pin at the start of the next vertical sync pulse. Odd/even can
be ignored if using non-interlaced video, as there is no
change in timing from one field to the next.
RSET
An external RSET resistor, connected from RSET pin 6 to
ground, produces a reference current that is used internally
as the timing reference for vertical sync width, vertical sync
default delay, burst gate delay and burst width. Decreasing
the value of RSET increases the reference current, which in
turn decreases reference times and pulse widths. A higher
frequency video input necessitates a lower RSET value.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is
shown in Figure 5. It can be implemented very simply and
inexpensively with a series resistor of 620Ω and a parallel
capacitor of 500pF, which gives a single pole roll-off
frequency of about 500kHz. This sufficiently attenuates the
3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet
passes the approximately 15kHz sync signals without
appreciable attenuation. A chroma filter will increase the
propagation delay from the composite input to the outputs.
FIGURE 5.
10
FN7018.1
EL1881C
Simplified Block Diagram
CLAMP
SYNC TIP
REF
1.5V
VDD
C1
RF
620Ω
SLICE
1.57V
510pF
RSET
C3
RSET*
0.1µF
5V
C2
COMP.
0.1µF
GND
VDD
0.1µF
COMPOSITE
VIDEO IN
2
CF
8
+
1
COMPOSITE
SYNC
5
BURST/BACK
PORCH OUT
3
VERTICAL
SYNC OUT
7
ODD/EVEN
4
BURST
6
REF
GEN
SYNC
TIP
70mV
SLICE
VERT SYNC
ODD/EVEN
NOTE: * RSET MUST BE AT 1% RESISTOR
FIGURE 6.
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11
FN7018.1