Datasheet

UNISONIC TECHNOLOGIES CO., LTD
M62364
CMOS IC
8-BIT 8-CH MULTIPLYING
D-A CONVERTER WITH
BUFFER AMPLIFIERS
SOP-24

DESCRIPTION
The UTC M62364 is a CMOS 8-bit, 8-ch D/A converter
having a multiplying function and output buffer amplifiers. It
has a serial data input and can easily communicate with a
microcontroller by the simple three-wiring method (DIN, CLK,
LD).
The output buffer amplifiers operating in AB-class has
both sinking and driving capabilities of 1.0mA or more and
can operate in a whole supply range from VDD to GND.
The IC is suitable for a use in automatic adjustment
applications in conjunction with a MCU by utilizing the
terminal Do for a cascading connection.

SSOP-24 (209mil)
FEATURES
*Three-wiring serial data transmission
*Doubled precision 8-ch D/A converter employing an R-2R
with higher-order segment method
*8 buffer amplifiers operating in a whole supply voltage range
from VDD to GND
*4-quadrant multiplication

ORDERING INFORMATION
Ordering Number
M62364G-R24-R
M62364G-S24-R

Package
SSOP-24
SOP-24
Packing
Tape Reel
Tape Reel
MARKING
SOP-24
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Copyright © 2015 Unisonic Technologies Co., Ltd
SSOP-24
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CMOS IC
PIN CONFIGURATION (TOP VIEW)

VIN1
VOUT1
1
2
3
4
VOUT2
VIN2
VDD
LD
CLK
DIN
VIN3
VOUT3
5
6
7
8
9
10
11
VOUT4
VIN4 12
24
23
22
21
20
VIN8
VOUT8
VOUT7
VIN7
GND
19
18
17
16
RESET
VDA(REF)
DOUT
VIN6
15
VOUT6
14
VOUT5
VIN5
13
EXPLANATION OF TERMINALS

PIN NO
8
17
SYMBOL
DIN
DOUT
7
CLK
6
LD
19
RESET
2
3
10
11
14
15
22
23
5
20
1
4
9
12
13
16
21
24
18
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VDD
GND
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VDA(REF)
FUNCTION
Serial data input
Serial data output
Shift clock input. Input data of DIN are taken into the 12-bit shift register on a rising edge of
the clock
A low state enables data loading to the 12-bit shift register. During a rising edge of LD, the
data will be loaded to the output register
Reset 8-bit latches
D/A Converter Output with8-bit resolution
Power Supply
Ground
D/A Converter Input
D/A Converter Reference Voltage Input
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
CMOS IC
BLOCK DIAGRAM
VDD
5
12-bit 12
SHIFT
REGISTER
bit SHIFT REGISTER
DIN 8
D0D0 D1
CLK 7
D23
D3
D3
D4
D4
D
D5
D
D6
D7
D
D
D8
17 DOUT
D9D
10
D10
11
D11
6
LD
ADDRESS DECODER
RESET 19
8-bit Latch
8-bit Latch
D-A CONVERTER
D-A CONVERTER
18 VDA(REF)
-
+
-
+
1
2
24
23
20
VIN1
VOUT1
VIN8
VOUT8
GND
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
ABSOLUTE MAXIMUM RATING
PARAMETER
Supply Voltage
Digital Input Voltage
Analog Input Voltage
Analog Output Voltage
D-A Reference Voltage
Operating Temperature
Storage Temperature

CMOS IC
SYMBOL
VDD
VIND
VIN
VOUT
VDA(REF)
TOPR
TSTG
RATINGS
-0.3 ~ +7.0
-0.3 ~ +7.0
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
-20 ~ +75
-40 ~ +125
UNIT
V
V
V
V
V
C
C
ELECTRICAL CHARACTERISTICS
(VDD=5V±10%, VDD≥VIN, GND, VDA(REF) =0V, TA= -20 ~ 85C, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDUCTION
MIN
ANA/DIG COMMON PART
Supply Voltage
VDD
2.7
Supply Current
IDD
CLK=1MHz, VCC=3V, IAO=0μA
Digital Part
Digital Input “Low” Voltage
IIL
Digital Input “High” Voltage
IIH
0.8VDD
DOUT Terminal Output “Low” Voltage
VOL
IOL=2.5mA
DOUT Terminal Output “High” Voltage
VOH
IOH= -400μA
VDD-0.4
Input Leak Current
IILK
VIN=0 ~VDD
-10
ANALOG PART
IAO= ±100μA
0.1
Buffer Amplifier Output Voltage Range
VAO
IAO= ±500μA
0.2
VIN=3V, VDA(REF) =0V,
* Proportional to max. input
Input Current
IIN
current condition (VIN- VDA(REF))
and digital data of each channels.
VIN=3V, VDA(REF) =0V,
* Proportional to max. input
-1.44
D-A Reference Input Current
IDA(REF) current condition
(VIN - VDA(REF)) and digital data of
each channels
Upper Saturation Voltage=0.4V
-1
Buffer Amplifier Output Current Range
IAO
Lower Saturation Voltage=0.4V
Buffer Amplifier Output Impedance
RO
Resolution
RES VDD=2.61V,VDA(REF) =0.050V
Differential Nonlinearity
DNL (10mV/1LSB)
-1
Without Load (IAO= ±0)
Nonlinearity
NL
-1.5
Output Capacitative Load
CO
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TYP
MAX
UNIT
3.5
V
mA
3.0
0.2 VDD
0.4
10
V
V
V
V
μA
VCC-0.1
VCC-0.2
V
0.18
mA
mA
1
mA
1
1.5
0.1
Ω
bit
LSB
LSB
μF
5
8
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CMOS IC
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
AC CHARACTERISTICS
Clock “L” Pulse Width
Clock “H” Pulse Width
Clock Rise Time
Clock Fall Time
Data Set Up Time
Data Hold Time
LD Set Up Time
LD Hold Time
LD “H” Pulse Duration Time
Data Output Delay Time
D-A Output Setting Time
SYMBOL
tCKL
tCKH
tCR
tCF
tDCH
tCHD
tCHL
tLDC
tLDH
tDOUT
tLDD
TEST CONDUCTION
TYP
MAX
200
200
CL=100pF
CL≤100pF,VAO : 0.1<=>2.6V
This Time Until The Output
Becomes
The final Value Of 1/2 LSB
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MIN
60
100
200
100
100
70
UNIT
ns
ns
200
ns
350
ns
ns
ns
ns
ns
ns
300
μs
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CMOS IC
DIGITAL FORMAT
( LSB )
DATA
1
2
3
4
5
6
7
8
9
10
11
12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
CLK
( MSB )
( LSB )
D8
: DAC DATA
D9
D11
D10
: DAC SELECT DATA
Dac Select Data
D8
D9
D10
D11
Dac Selection
0
0
0
0
Don't Care
0
0
0
1
VOUT1 Selection
0
0
1
0
VOUT2 Selection
0
0
1
1
VOUT3 Selection
0
1
0
0
VOUT4 Selection
0
1
0
1
VOUT5 Selection
0
1
1
0
VOUT6 Selection
0
1
1
1
VOUT7 Selection
1
0
0
0
1
0
0
1
Don't Care
1
0
1
0
Don't Care
1
0
1
1
Don't Care
1
1
0
0
Don't Care
1
1
0
1
Don't Care
1
1
1
0
Don't Care
1
1
1
1
Don't Care
VOUT8 Selection
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
DIGITAL FORMAT(Cont.)

TIMING CHART
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CMOS IC
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CMOS IC
TIMING CHART(Cont.)

tCF
tCKH
tCR
CLK
tCKL
tLDC
DIN
tLDH
tDCH
tCHD
tCHL
LD
tLDD
D - A OUTPUT
tDo
DOUT OUTPUT
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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