L DESIGN FEATURES PD Interface for PoE+ Includes 25.5W Classification and Protection Features in a Low Profile 4mm × 3mm DFN by Kirk Su Introduction Overview of the Third Generation Power over Ethernet System (PoE+) The Power over Ethernet (PoE) standard specifies how DC power can be distributed alongside high speed data through a single RJ45 connector. The second generation standard (IEEE 802.3af) allows Powered Devices (PDs) to draw 12.95W from Power Sourcing Equipment (PSEs). The popularity of the standard has PD equipment vendors running up against the 12.95W power limit. To answer the call for more power, the newer IEEE 802.3at standard (also called PoE+) establishes a high power allocation while maintaining compatibility with the existing IEEE 802.3af systems. In the new standard, PSEs and PDs are distinguished as Type-1 if they comply with the IEEE 802.3af power levels, or Type-2 if they comply with the IEEE 802.3at power levels. The maximum available power to a Type-2 PD is 25.5W. The IEEE 802.3at standard also establishes a new method for Type-2 equipment to mutually identify each other while maintaining compatibility with the existing PoE systems. A Type-2 PSE has the option of declaring the presence of high power by performing 2-event classification (Layer 1) or by communicating with the PD over the data line (Layer 2). In turn, a Type-2 PD must recognize both layers of communications and identify a Type-2 PSE before beginning 25.5W operations. L 26 GND (V) 40 1st CLASS 2nd CLASS 30 ON UVLO 20 10 DETECTION V1 DETECTION V2 1st MARK 2nd MARK INRUSH PD CURRENT No additional external components are required to program the LTC4265 since all features (signature resistance, UVLO, OVLO, inrush current, and thermal protection) are built in and programmed into the LTC4265 50 LOAD, ILOAD 1st CLASS 2nd CLASS 40mA TIME DETECTION V1 DETECTION V2 50 GND – VOUT (V) The LTC4265 is a PoE PD interface that can identify 2-event classification protocol and present an active signal as required for operation in an IEEE 802.3at-compliant PD. In addition, the LTC4265 may be configured for a variety of auxiliary power options with the aid of the shutdown and signature corrupt features. to guarantee a smooth power-up transition and PD operation with any Power Sourcing Equipment (PSE). This eliminates additional component costs and cumbersome calculations that 1st MARK 2nd MARK dV = INRUSH dt C1 40 30 UVLO ON UVLO 20 T = RLOAD C1 10 TIME GND – T2PSE (V) The third generation Power over Ethernet standard increases the power available to PDs to 25.5W, up from the earlier standard’s 12.95W (see sidebar). In the new standard, a Type-2 (high power) PD must communicate via handshake with Type-2 power sourcing equipment (PSE) to determine that the PSE is capable of providing high power. Type-2 PSEs are backwards compatible to the old standard. The LTC4265 is a PoE PD interface that can identify 2-event classification (see sidebar) protocol and present an active signal as required for operation in an IEEE 802.3at-compliant PD. In addition, the LTC4265 may be configured for a variety of auxiliary power options with the aid of the shutdown and signature corrupt features. The LTC4265 is highly integrated and easy to apply, requiring only one classification programming resistor. TIME –10 –20 –30 –40 TRACKS VIN –50 INRUSH = 100mA ILOAD = RCLASS = 30.9Ω VIN RLOAD GND LTC4265 IIN PSE RCLASS GND RCLASS RLOAD C1 VOUT T2PSE VIN VOUT Figure 1. Example of 2-event classification waveform Linear Technology Magazine • January 2009 DESIGN FEATURES L are required in other power interface products to set thresholds, signature resistance, and current limits. The LTC4265 comes in a low profile, thermally enhanced, 4mm × 3mm DFN package. input voltage into the Mark voltage range of 6.9V to 10V, signaling the 1st Mark event. The PD in the Mark voltage range presents a load current between 0.25mA to 4mA. A Type-2 PSE repeats this sequence, signaling What is 2-Event Classification? ACTIVE-HIGH ENABLE The IEEE 802.3at establishes two ways to communicate the presence of a Type-2 PSE. The Layer 1 approach requires a PSE to perform 2-event classification, where classification probing is performed twice. The Layer 2 approach requires the PSE to communicate over the high speed data line. A Type-2 PD is required to recognize a Type-2 PSE using either layer of communication. Layer 1 communication using 2-event classification is included in the IEEE 802.3at standard for the benefit of PSEs/power injectors which do not have access to the high speed data line. Since Layer 2 communications takes place directly between the PSE and the LTC4265 load, the LTC4265 concerns itself only with recognizing 2-event classification. Figure 1 shows an example of a 2-event classification. The 1st classification event occurs when the PSE presents an input voltage between 14.5V to 20.5V and the LTC4265 presents a class 4 load current. A Type-2 PSE then drops the GND TO PSE V+ VIN OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT GND LTC4265 TO PSE PWRGD –54V VIN VOUT R9 100k RS 10k D9 5.1V MMBZ5231B GND LTC4265 TO PSE PWRGD –54V RS 10k VIN Figure 2. Interfacing with the Type-2 PSE via the T2PSE pin Linear Technology Magazine • January 2009 V+ PD LOAD Q1 FMMT2222 VOUT 4265 F08 Figure 3. Examples of enabling/disabling the PD load via the complementary power good pins 2 3 8 OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT SHDN R10 100k D9 MMBD4148 7 TO PD LOAD PD LOAD ACTIVE-LOW ENABLE TX+ T1 + TX– RX+ TO PHY TVS 0.1µF 100V BR1 C1 – RX– SPARE+ + 5 RP VOUT VOUT ACTIVE-LOW ENABLE 4 T2PSE VIN VIN RUN 100k GND –54V PWRGD –54V 6 V+ TO PSE PD LOAD LTC4265 TO PSE 1 TO PD LOAD T2PSE LTC4265 GND RJ45 RP LTC4265 –54V the 2nd Classification and 2nd Mark event occurrence. The Type-2 PSE then applies power to the PD and the LTC4265 charges up the reservoir capacitor C1 with a controlled inrush current. When C1 is fully charged, and the LTC4265 BR2 SPARE– 36V GND LTC4265 10k SHDN 10k – ISOLATED WALL ADAPTER PD LOAD VIN VOUT + – D1 T1 = COILCRAFT ETHI-230LD BR1, BR2 = DF1501S Figure 4. Auxiliary power supply. Auxiliary power takes precedence over PoE power (using the SHDN pin). 27 3.65k VCC 1.2k PS2801-1-L T2P (TO MICROCONTROLLER) TLV431A 10nF 4.7nF 2k 2.2nF 2kV FDS8880 5.1Ω 158k 158k 100pF 332k 82k GND BLANK 10.0k PGND SD_VSEC VOUT T2PSE VIN SHDN 1.5 0.1µF 100V 2 2.5 3 3.5 4 LOAD CURRENT (A) 4.5 42V 50V 57V 5 30.9Ω 1 0.5 70 75 80 85 90 95 65 SMAJ58A RCLASS GND LTC4265 –54V FROM SPARE PAIR –54V FROM DATA PAIR B1100 s 8 PLCS Figure 5. PoE-based self-driven synchronous forward power supply PS22801-1-L 20k 5V 51k GND 0.22µF 22.1k ROSC SS_MAXDC DELAY FB VREF LT1952 SOUT VIN BAS516 10µF 100V + 10µH 2.2µF 100V 237k 10µF 16V 33k VCC 0.1µF BC857BF 33k COMP OC ISENSE 133Ω OUT 10k BAS516 0.1µF BAS516 IRF6217 1.5k 4.7nF 250V 22k FDS2582 • 50mΩ • • PA2431NL BAS516 1mH DO1608C-105 18V PDZ18B GND EFFICIENCY (%) 28 5.1Ω 1nF Interfacing to the LTC4265 The LTC4265 has three output signals that interface to other blocks within a PD. The Type-2 PSE indicator bit (T2PSE) alerts the PD load that it may consume the full 25.5W available in the new IEEE 802.3at specification. Two complementary power good pins (PWRGD and PWRGD) are typically used to enable a DC/DC converter after the PD is fully powered. When a Type-2 PSE completes the 2-Event classification sequence, the LTC4265 recognizes this sequence, and provides an indicator bit, declaring the presence of a Type-2 PSE. The open drain output provides the capability to use this signal to communicate to the PD load. Figure 2 shows two interface options using the T2PSE pin and an optoisolator. The T2PSE pin is active low and connects to the optoisolator to communicate across the isolation barrier. The pull up resistor RP is sized according to the requirements of the optoisolator operating current, the pull-down capability of the T2PSE pin, and the choice of V+. V+ can come from the PoE supply rail (which the LTC4265 GND is tied to), or from the voltage source that supplies power to the DC/DC converter. The former has the advantage of not drawing power unless T2PSE is declared active. Figure 3 shows options for interfacing the LTC4265 power good pin to the PD load, usually via the run/ enable/shutdown pins of a DC/DC converter. The active high PWRGD pin features an open collector output referenced to VOUT, which can interface directly with the run/enable pin of a DC/DC converter. When the PD is powered 5.1Ω FDS8880 1nF 6.8µH PG0702.682 + declares power good, the T2PSE output presents an active low signal, or low impedance output with respect to VIN, which alerts the PD load that a Type-2 PSE is present and 25.5W applications may operate. In essence, a Type-2 PSE recognizes a Type-2 PD when the PSE classifies the PD and sees a class 4 load current. A Type-2 PD recognizes a Type-2 PSE when the PSE classifies twice. 11.3k 5V 5A 220µF 6.3V PSLVOJ227M(12) L DESIGN FEATURES Linear Technology Magazine • January 2009 T2P (TO MICROCONTROLLER) 47µF 16V + Linear Technology Magazine • January 2009 10k PE-68386 4 5 • LTV357TA 1 • 51k GND Figure 6. High efficiency 12V isolated power supply 10k 33pF 0.1µF 38.3k 2.2k PGDLY tON SYNC RCMP VIN 29.4k 3.01k FB VCC 100k ENDLY LT3825 UVLO SHDN SG SG 20Ω 12k VC GND OSC SFST CCMP SENSE– 4.7nF 33mΩ PG SENSE+ FDS2582 15µF 16V 8 1nF 1µF 100Ω SG 2.2nF 2kV 47pF BAS21 BAT54 15Ω 2.2nF FDS3572 15Ω 470pF 2kV • • 150Ω 39k 2.2µF 100V 77 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) 79 81 83 85 87 91 93 89 42V 48V 57V EXCLUDING BRIDGES T2PSE VOUT –54V FROM SPARE PAIR 30.9Ω RCLASS LTC4265 GND 14k 383k 10µF 100V + 10µH SMAJ58A 0.1µF 100V B1100 s 8 PLCS –54V FROM DATA PAIR continued on page 34 GND In many applications, the PD can run from the PoE port and/or from an auxiliary power source such as a wall adapter. Auxiliary power can be injected into an LTC4265-based PD at the input of the LTC4265, the output of the LTC4265, or even the output of the DC/DC converter. Some PD applications may also prioritize the auxiliary supply or the PoE supply, and/or require a seamless transition between PoE and auxiliary power. Figure 4 shows the most common auxiliary power method where auxiliary power is injected between the PD interface and the DC/DC converter. In this example, the auxiliary port injects 48V onto the line via diode D1. The components surrounding the SHDN pin are selected so that the LTC4265 disconnects power to the output when the auxiliary supply reaches 36V. This configuration is an auxiliarydominant configuration. That is, the auxiliary power source supplies the power even if PoE power is already present. When the auxiliary power is applied, the PoE channel stops drawing power. The PSE at this point recognizes that the PD does not draw any current and may cease power delivery to the PD. This configuration also provides a seamless transition from PoE to auxiliary power when auxiliary power MMBT3906 MMBT3904 1µF 16V 20k 10µF 16V 0.33µH • PA2467NL Configuring a PD for Auxiliary Power EFFICIENCY (%) up by the PSE, the PWRGD pin is high impedance with respect to VOUT. An internal 14V clamp protects the DC/DC converter from excessive voltage. The PWRGD pin is also designed to become high impedance when the SHDN pin is invoked in an auxiliary power application. This prevents the PWRGD pin from interfering with the converter operation when auxiliary power is present. The active low PWRGD pin connects to an internal, open drain MOSFET referenced to VIN and can interface directly to the shutdown pin of a DC/ DC converter. When the PD is powered up by the PSE, the PWRGD pin is low impedance with respect to VIN. 12V 2A DESIGN FEATURES L 29 L DESIGN IDEAS VIN 20V/DIV VIN 20V/DIV VIN 20V/DIV VOUT 1V/DIV VOUT 1V/DIV VOUT 1V/DIV RUN/SS2 2V/DIV RUN/SS2 2V/DIV RUN/SS2 2V/DIV FAULT 2V/DIV FAULT 2V/DIV FAULT 2V/DIV TIME 100µs/DIV Figure 5. Transition to ride-through mode by software perhaps, from the time FAULT goes away until full current is demanded. The LT3509 prevents inrush currents at start-up with a current limiting soft-start feature, which allows the available output current to ramp up slowly. Both the peak current limit and the valley current limit (the one sensed through the catch diodes) are controlled by the voltage on the RUN/SS pins, so as capacitors C6 and C7 charge up, the output current slowly increases to its normal maximum value. An example of the soft-start characteristic is shown in Figure 3. LTC4265, continued from page 29 is applied. That is, the DC/DC converter continues to operate through the power transition. But the transition from auxiliary power to PoE power (when the auxiliary is removed) is not seamless since a PSE must redetect the PD before applying power. Guidelines for Pairing the LTC4265 with a DC/DC Converter The LTC4265 can be paired with just about any DC/DC converter, but two are particularly well suited to Type-2 Power over Ethernet Applications: the LT3825 flyback controller and LT1952 forward controller. Forward and flyback converters satisfy the electronic isolation requirement in the IEEE 802.3af and IEEE 802.3at specifications. In addition to the topology requirements, the LT3825 and LT1952 controllers are selected based on their ability to tolerate the wide PoE line voltage range, which varies from 36V to 57V. 34 TIME 2ms/DIV TIME 100ms/DIV Figure 6. Complete ride-through event Demonstration and Test Results The ride-through performance the application of Figure 1 is tested using the setup shown in Figure 4. A switched supply produces either a normal input or an overvoltage transient. The output is connected to an active load circuit with ON/OFF controlled by the FAULT signal. Figure 5 shows the start of the overvoltage event on a fast time base to show the step that occurs as the regulator shuts off, but before the load is reduced. Figure 6 shows the entire 400ms transient and the droop that happens when there is no output but also very little load. Figure 7 shows As PoE power levels increase, the Schottky diode typically placed at the output of the secondary winding becomes an efficiency drain as it dissipates more power with increased output current. In addition, the output diode requires a considerably large heat sink and board area to displace the heat. For these reasons, many powerhungry PDs are better served by synchronous DC/DC topologies, where the output diode is replaced with an active switch synchronized to the operation of the controller. Both the LT3825 and LT1952 include built-in synchronous drivers, enabling the use of an active switch. Figure 5 shows the LTC4265 paired with an LT1952 in a self-driven synchronous forward power supply configuration. Figure 6 shows the LTC4265 paired with a LT3825. This is a synchronous flyback power supply configuration with no optoisolator Figure 7. End of ride-through event the end of the event on an expanded timescale. Conclusion Overvoltage transients are a fact of life in automobile and industrial power systems. The LT3509, combined with a small, low cost capacitor, can be used to both protect components from overvoltage transients and allow the downstream systems to ride through the event without having to completely reset. It is possible to ride through an overvoltage transient of even several hundred milliseconds, provided a brief interruption of service can be tolerated. L feedback. The LT3825 may also be configured for a forward topology. These are not the only DC/DC converter solutions that work well with the LTC4265. The LTC4265 can be easily applied in applications that already have a DC/DC converter. Conclusion The LTC4265 PD interface provides the features required in a PD interface to operate under the IEEE 802.3at standard with minimum component count. Since all of the features (signature resistance, UVLO, OVLO, inrush current, and thermal protection) are built in, little is needed around its low profile 4mm × 3mm DFN package to create a complete PoE Type-2 interface. Simply pair it with a PoE-ready DC/DC converter by hooking up the Type-2 and power good indicator pins, and a high power PD is ready to go. Add to this the ability to handle auxiliary power, and the LTC4265 proves a versatile PoE+ tool. L Linear Technology Magazine • January 2009