MULTI-ISSUE 64-BIT MICROPROCESSOR IDT RC5000 Integrate d Device Technology, Inc. FEATURES • • Dual issue super-scalar execution core, executing at high-frequency - 250 MHz frequency - Dual issue floating-point ALU operations with other instruction classes - Traditional 5-stage pipeline, minimizes load and branch latencies - Single cycle repeat rate for most floating point ALU operations • High level of performance for a variety of applications - High-performance 64-bit integer unit achieves 330 dhrystone MIPS (dhrystone 2.1) - Ultra high-performance floating-point accelerator, directly implementing single- and double-precision operations achieves 500mflops - Extremely large on-chip primary caches - On-chip secondary cache controller • Large, efficient on-chip caches - 32KB Instruction Cache, 32KB Data Cache - 2-set associative in each cache - Virtually indexed and physically tagged to minimize cache flushes - Write-back and write-through selectable on a per page basis - Critical word first cache miss processing - Supports back-to-back loads and stores in any combination at full pipeline rate • • • • • High-performance memory system - Large primary caches integrated on-chip - Secondary cache control interface on-chip - High-frequency 64-bit bus interface runs up to 100MHz - Aggregate bandwidth of on-chip caches, system interface of 5GB/s - High-performance write protocols for graphics and data communications MIPS-IV 64-bit ISA for improved computation - Compound floating-point operations for 3D graphics and floating-point DSP - Conditional move operations Compatible with a variety of operating systems - Windows™ CE - Numerous MIPS-compatible real-time operating systems Uses input system clock, with processor pipeline clock multiplied by a factor of 2-8 Large on-chip TLB Active power management, including use of WAIT operation BLOCK DIAGRAM Phase Lock Loop Data Set A Instruction Set A Data Tag A Store Buffer DTLB Physical Instruction Select SysAD Integer Instruction Register Address Buffer Write Buffer FP Instruction Register Instruction Tag A Read Buffer ITLB Physical Data Set B Instruction Set B Instruction Tag B DBus FPIBus IntIBus Control Tag AuxTag Load Aligner Unpacker/Packer Joint TLB Integer Register File Coprocessor 0 System/Memory Control DVA IVA PC Incrementer Branch Adder Instruction TLB Virtual Integer Control Floating Point MAdd,Add,Sub, Cvt Div, SqRt Floating-point Control Floating Point Register File Integer/Address Adder Data TLB Virtual Shifter/Store Aligner Logic Unit ABus Integer Multiply, Divide Program Counter The IDT logo is a registered trademark and ORION, R4600, R4640, R4650, R4700, R5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc. MIPS is a registered trademark of MIPS Computer Systems, Inc. COMMERCIAL TEMPERATURE RANGE 1998 Integrated Device Technology, Inc. June, 1998 1 IDT RC5000 COMMERCIAL TEMPERATURE RANGE DESCRIPTION Integer Pipeline The RC5000 is a limited dual-issue machine that The RC5000 serves many performance critical utilizes a traditional 5-stage integer pipeline. This basic embedded applications, such as high-end internetinteger pipeline of the RC5000 is illustrated in Figure 1. working systems, color printers, and graphics terminals. The integer instruction execution speed is tabulated The RC5000 is optimized for high-performance appli(in number of pipeline clocks) as follows: cations, with special emphasis on system bandwidth and floating point operations, through integration of highOperation Latency Repeat performance computational units and a high-performance Load 2 1 memory hierarchy. For this class of application, the result is a relatively low-cost CPU capable of approximately 330 Store 2 1 Dhrystone MIPS. MULT/MULTU 8 8 IDT’s objectives in offering the RC5000 include: DMULT/DMULTU 12 12 • Offering a high performance upgrade path to existing DIV/DIVU 36 36 embedded customers in the internetworking, office DDIV/DDIVU 68 68 automation and visualization markets. Other Integer ALU 1 1 • Providing a significant improvement in the floatingBranch 2 2 point performance currently available in a moderately priced MIPS CPU. Jump 2 2 • Providing improvements in the memory hierarchy of The RC5000’s short pipeline keeps the load and desktop systems by using large primary caches and integrating a secondary cache controller. branch latencies very low. The caches contain special • Enabling improvements in performance through the logic that allows any combination of loads and stores to use of the MIPS-IV ISA. execute in back-to-back cycles without requiring pipeline slips or stalls. (This presumes, of course, that the operaInstruction Issue Mechanism The RC5000 recognizes two general classes of tion does not miss in the cache.) instructions for multi-issue: • Floating-point ALU • All others These instruction classes are pre-decoded by the RC5000, as they are brought on-chip. The pre-decoded information is stored in the instruction cache. Assuming that there are no pending resource conflicts, the RC5000 can issue one instruction per class per pipeline clock cycle. Note that this broad separation of classes insures that there are no data dependencies to restrict multi-issue. However, long-latency resources in either the floatingpoint ALU (e.g. DIV or SQRT instructions) or instructions in the integer unit (such as multiply) can restrict the issue of instructions. Note that the R5000 does not perform outof-order or speculative execution; instead, the pipeline slips until the required resource becomes available. There are no alignment restrictions on dual-issue instruction pairs. The RC5000 fetches two instructions from the cache per cycle. Thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, since the instruction cache only performs aligned fetches. Instruction Set Architecture The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and CP1X functional units (and their instruction set). 2 IDT RC5000 I0 I1 COMMERCIAL TEMPERATURE RANGE 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W 1I 2I 1R 2R 1A 2A 1D 2D 1W ••• 1I 2I 1R 2R 1A 2A 1D ••• 1I 2I 1R 2R 1A ••• I2 I3 I4 one cycle Key to Figure 1I-1R Instruction cache access 2I Instruction virtual to physical address translation 2A-2D Data cache access and load align 1D Data virtual to physical address translation 1D-2D Virtual to physical address translation 2R Register file read 2R Bypass calculation 2R Instruction decode 2R Branch address calculation 1A Issue or slip decision 1A-2A Integer add, logical, shift 1A Data virtual address calculation 2A Store align 1A Branch decision 2W Register file write Figure 1. R5000 Integer Pipeline Stages RC5000 Computational Units The RC5000 contains the following computational units: Integer ALU. The RC5000 implements a full, single-cycle 64-bit ALU for all integer ALU functions other than multiply and divide. Bypassing is used to support back-to-back ALU operations at the full pipeline rate, without requiring stalls for data dependencies. Integer Multiply/Divide Unit. This unit is separated from the primary ALU, to allow these longer latency operations to run in parallel with other operations. The pipeline stalls only if an attempt to access the HI or LO registers is made before the operation completes. Floating-point ALU. This unit is responsible for all CP1/CP1X ALU operations other than DIV/SQRT. The unit is pipelined to allow a single-cycle repeat rate for single-precision operations Floating-point DIV/SQRT unit. This unit is separated from the other floating-point ALU, so that these long latency operations do not prevent the issue of other floating point operations. In addition, the RC5000 implements separate logical units to implement loads, stores, and branches. Electrical Specifications Operating Frequency The input clock operates in a frequency range of 33MHz to 100MHz. The pipeline frequency for the RC5000 is 2 to 8 times the input clock (up to the maximum for the speed grade of CPU). THERMAL CONSIDERATIONS The RC5000 utilizes special packaging techniques, to improve the thermal properties of high-speed processors. The RC5000 is packaged using cavity down packaging in a 223-pin PGA package with integral thermal slug, and a 272-pin BGA package. These packages effectively dissipate the power of the CPU, increasing device reliability. 3 IDT RC5000 COMMERCIAL TEMPERATURE RANGE The RC5000 utilizes an all-aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing. Due to the heat-spreading effect of the aluminum, the package allows for an efficient thermal transfer between the die and the case. The aluminum offers less internal resistance from one end of the package to the other, reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the PCB for a given temperature. Even nominal amounts of airflow will dramatically reduce the junction temperature of the die, resulting in cooler operation. The RC5000 is guaranteed in a case temperature range of 0° to +85° C. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient (∅CA) of the given package. The following equation relates ambient and case temperatures: TA = TC - P * ∅CA DATA SHEET REVISION HISTORY Changes to version dated January 1996: Pin Description section: - Corrected pin list for Clock/Control, Initialization, and Secondary Cache interfaces. Advance Pin-Out section: - Changed pins AA19 and AA21 from Vcc to Vss. Changes to version dated March 1997: - Upgraded data sheet status from “Preliminary” to Final. - Added section on thermal considerations - Added section on absolute maximum ratings Changes to version dated June 1997: - Revised Power Consumption and System Interface Parameters Changes to version dated September 1997: - Added user notation on Boot Mode Bits 20 and 33 for 200 MHz frequency Changes to version dated June 1998: - Added 250 MHz; changed naming conventions where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for ∅CA at various airflows are shown in Table 1. ∅CA Airflow (ft/min) 0 200 400 600 800 1000 PGA 16 7 5 3 2.5 2 BGA 14 6 4 3 2.5 2 Table 1. Thermal Resistance (∅CA) at Various Airflows Note: The RC5000 implements advanced power management to substantially reduce the average power dissipation of the device. This operation is described in Reference the IDT79RV5000 RISC Microprocessor Manual. 4 IDT RC5000 COMMERCIAL TEMPERATURE RANGE LOGIC SYMBOL ScTCE* 9 SysCmd(8:0) ScTDE* SysCmdP ScTOE* ValidIn* ScCLR* ValidOut* ScDCE* ExtRqst* ScDOE* Release* ScCWE* 16 RdRdy* WrRdy* ScLine (15:0) ScMATCH ScVALID RC5000 Logic Symbol SysClock VccP 6 Int (5:0)* NMI* VssP Vcc Vss 34 BigEndian 34 ModeClock ModeIN VccOk ColdReset* Initialization Interface Clock Interface ScWord (1:0) Secondary Cache Interface 2 8 Reset* JTDI JTDO JTMS JTAG Interface System Interface SysADC(7:0) 64 Interrupt Interface SysAD(63:0) JTCK Figure 1. RC5000 Logic Symbol 5 IDT RC5000 COMMERCIAL TEMPERATURE RANGE Pin Description RC5000 implements a bus similar to that of the RC4700. Table 2 lists and describes the RC5000 signals. Pin Name Type Description System interface: ExtRqst* Input Release* Output RdRdy* Input Read Ready. Signals that an external agent can now accept a processor read. WrRdy* Input Write Ready. Signals that an external agent can now accept a processor write request. ValidIn* Input Valid Input. Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ValidOut* Output External Request. Signals that the system interface needs to submit an external request. Release Interface. Signals that the processor is releasing the system interface to slave state Valid Output. Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. SysAD(63:0) Input/Output System Address/Data bus. A 64-bit address and data bus for communication between the processor and an external agent. SysADC(7:0) Input/Output System Address/Data check bus. An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. SysCmd(8:0) Input/Output System Command/data identifier bus. A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmdP Input/Output Reserved System Command/data identifier bus parity. For the RC5000, unused on input and zero on output. Clock/control interface: SysClock Input Master Clock. Master clock input at the bus frequency. The pipeline clock is derived by multiplying this clock up. VCCP Input Quiet VCC for PLL. Quiet VCC for the internal phase locked loop. VSSP Input Quiet VSS for PLL. Quiet VSS for the internal phase locked loop. Int(5:0)* Input Interrupt. Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. NMI* Input Non-maskable interrupt. Non-maskable interrupt, ORed with bit 6 of the interrupt register. JTDI Input JTAG Data In. Connected directly to JTDO. No JTAG implemented; should be pulled High. JTCK Input JTAG Clock Input. Unused input; should be pulled High. JTDO Output Interrupt interface: JTAG interface: JTAG Data Out. Connected directly to JTDI. If no external scan used, this is a no connect. Table 2. RC5000 Signal Names and Descriptions (Page 1 of 2) 6 IDT RC5000 COMMERCIAL TEMPERATURE RANGE Pin Name Type Description JTMS Input JTAG Command. Unused input. Should be pulled High. VCCOk Input VCC is OK. When asserted, this signal indicates to the RC5000 that the power supply has been aboveVcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream. ColdReset* Input Cold Reset. This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset* Input Reset. This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be synchronously deasserted with SysClock. Output Boot Mode Clock. Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. Initialization interface: ModeClock ModeIn Input Boot Mode Data In. Serial boot-mode data input. BigEndian Input Endian mode select. Allows the system to change the processor addressing mode without rewriting the mode ROM. If endianness is to be specified by using the BigEndian pin, program mode ROM bit 8 to 0; if endianness is to be specified by the mode ROM, ground the BigEndian pin. Secondary cache interface: ScCLR* Output Secondary Cache Block Clear. Clears all valid bits in those Tag RAM’s which support this function. ScCWE*(1:0) Output Secondary Cache Write Enable. Asserted during writes to the secondary cache ScDCE*(1:0) Output Data RAM Chip Enable. Chip Enable for Secondary Cache Data RAM ScDOE* ScLine (15:0) ScMATCH Input Output Input Data RAM Output Enable. Asserted by the external agent to enable data onto the SysAD bus Data RAM Output Enable. Cache line index for secondary cache Secondary cache Tag Match. Asserted by Tag RAM on Secondary cache tag match ScTCE* Output Secondary cache Tag RAM Chip Enable. Chip enable for secondary cache tag RAM. ScTDE* Output Secondary cache Tag RAM Data Enable. Data Enable for Secondary Cache Tag RAM. ScTOE* Output Secondary cache Tag RAM Output Enable. Tag RAM Output enable for Secondary Cache Tag RAM’s ScWord (1:0) Input/Output Secondary cache Word Index. Determines correct double-word of Secondary cache Index ScValid Input/Output Secondary cache Valid. Always driven by the CPU except during a cache probe operation, when it is driven by the tag RAM. Table 2. RC5000 Signal Names and Descriptions (Page 2 of 2) 7 IDT RC5000 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS1 RC5000 3.3V±5% Symbol Rating Commercial Unit VTERM Terminal Voltage with respect to GND –0.5(2) to +4.6 V TC Operating Temperature (case) 0 to +85 °C TBIAS Case Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –55 to +125 °C IIN DC Input Current 20(3) mA IOUT DC Output Current 50(4) mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN minimum = –2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts. 3. When VIN < 0V or VIN > VCC. 4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. RECOMMENDED OPERATION TEMPERATURE AND SUPPLY VOLTAGE RC5000 Grade Temperature GND VCC Commercial 0°C to +85°C (Case) 0V 3.3V±5% 8 IDT RC5000 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC= 3.3V± 5%; Tcase = 0°C to +85°C ) Clock Parameters—RC5000 180MHz 200MHz† 250MHz†# Parameter Symbol Min Max Min Max Min Max SysClock HIGH tSCHIGH 3 — 3 — 2.5 — ns SysClock LOW tSCLOW 3 — 3 — 2.5 — ns 33 90 33 100 33 125 MHz 11.1 30 10 30 8 30 ns SysClock Frequency — Units SysClock Period tSCP SysClock Rise Time tSCRise — 2.5 — 2 — 2 ns SysClock Fall Time tSCFall — 2.5 — 2 — 2 ns ModeClock Period tModeCKP — 256 tSCP — 256 tSCP — 256 tSCP ns Capacitive Load Deration—RC5000 180MHz 200MHz† 250MHz†# Parameter Symbol Test Conditions Min Max Min Max Min Max Units Load Derate CLD — — 2 — 2 — 2 ns/25pF Power Consumption—RC5000 180MHz 200MHz† 250MHz†# Max Max Max Parameter System Condition Icc 180/45MHz 200/50MHz Conditions 250/62.5MHz — Standby 120mA 120mA 120mA CL = 50 pF Active 1100mA 1300mA 1800mA CL = 50pF Pipelined writes or write re-issue Tc = 25oC System Interface Parameters—RC5000 180MHz Parameter Data Output Symbol tDM= Min tDO = Max Test Conditions 200MHz† 250MHz†# Min Max Min Max Min Max Units mode14..13 = 10 (fastest) 1.5* 7 1.5* 5 1.5* 5 ns mode14..13 = 01 (slowest) 1.5* 11 1.5* 11 1.5* 11 ns 9 IDT RC5000 COMMERCIAL TEMPERATURE RANGE 180MHz Parameter Symbol Test Conditions tDS Data Input tDH 200MHz† 250MHz†# Min Max Min Max Min Max Units trise = 3ns 1.5 — 1.5 — 1.5 — ns tfall = 3ns 0.5 — 0.5 — 0.5 — ns *Guaranteed by design Boot Time Interface Parameters—RV5000 180MHz Parameter 200MHz† 250MHz†# Symbol Test Conditions Min Max Min Max Min Max Mode Data Setup tDS — 4 — 4 — 4 — Master Clock Cycle Mode Data Hold tDH — 0 — 0 — 0 — Master Clock Cycle Units † Boot Mode Bits 20 and 33 must be set to “1” for operation at this frequency. # Preliminary information for 250MHz. 10 IDT RC5000 COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS (Vcc = 3.3V± 5%; Tcase = 0°C to +85°C) 180MHz Parameter Min Max 200MHz† Min Max 250MHz†# Min Max VOL — 0.1V — 0.1V — 0.1V VOH VCC — VCC — VCC — - 0.1V - 0.1V Conditions |IOUT|= 20uA - 0.1V VOL — 0.4V — 0.4V — 0.4V |IOUT|= 4mA VOH 2.4V — 2.4V — 2.4V — VIL –0.5V 0.2VCC –0.5V 0.2VCC –0.5V 0.2VCC — VIH 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V — IIN — ±10uA — ±10uA — ±10uA CIN — 10pF — 10pF — 10pF — CIO — 10pF — 10pF — 10pF — Cclk — 10pF — 10pF — 10pF I/OLEAK — 20uA — 20uA — 20uA 0 ≤ VIN ≤ VCC Input/Output Leakage † Boot Mode Bits 20 and 33 must be set to “1” for operation at this frequency. # Preliminary information for 250MHz. 11 IDT RC5000 COMMERCIAL TEMPERATURE RANGE PHYSICAL SPECIFICATIONS The RC5000 is available in two packages, the 223-pin CPGA and the 272-ball SBGA. Information on the CPGA package is shown in Figure 2 and Table 3; information on the SBGA package is shown in Figure 3 and Table 4. V U T R P N M L K 223-Pin CPGA J H G F E D C B A 1 2 3 4 5 Figure 2. 6 7 8 9 10 11 12 13 14 15 16 17 18 RC5000 CPGA Pin Orientation (Bottom View) 12 IDT RC5000 COMMERCIAL TEMPERATURE RANGE 223-Pin CPGA Pinout Pkg Pin Function Pkg Pin Function Pkg Pin Function Pkg Pin A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 Vcc Vss Vcc Vss Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vss Vcc Vss Vss Vss Vss Vcc SysADC[4] SysADC[0] SysAD[18] SysAD[20] SysAD[54] SysAD[26] SysAD[58] SysAD[30] SysAD[46] SysAD[12] SysAD[40] SysAD[6] Vss Vcc Vcc Vcc Vcc ValidOut* NMI* C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E15 E16 E17 SysADC[6] SysAD[16] SysAD[50] SysAD[22] SysAD[24] SysAD[28] SysAD[62] SysAD[44] SysAD[10] SysAD[38] SysAD[4] SysAD[34] SysAD[2] Vss Vss INT3* INT5* Release* Vcc SysADC[2] SysAD[48] SysAD[52] SysAD[56] SysAD[60] SysAD[14] SysAD[42] SysAD[8] SysAD[36] ColdReset* SysAD[0] ScTOE* Vcc Vss INT[0]* INT[2]* INT[4]* SysAD[32] ScDCE[1]* ScCWE[1]* E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H15 H16 H17 H18 J1 J2 J3 J4 J15 J16 J17 J18 K1 K2 K3 K4 K15 K16 Vcc K17 Vcc K18 Reserved L1 ScValid L2 INT[1]* L3 ScDCE[0]* L4 ScCWE[0]* L15 ScTDE* L16 Vss L17 Vss L18 Reserved M1 Reserved M2 Reserved M3 ScCLR* M4 ScTCE* M15 ModeIn M16 Vcc M17 Vcc M18 Reserved N1 Reserved N2 Reserved N3 VccOK N4 ModeClock N15 SysClock N16 Vss N17 Vss N18 WrRdy* P1 ValidIn* P2 ExtReq* P3 JTDO P4 JTDI P15 JTCK P16 Vcc P17 Vcc P18 ScMatch R1 RdRdy* R2 ScDOE* R3 JTMS R4 VccP R5 Function Pkg Pin Function VssP Vss Vss SysCmd[8] SysCmd[7] SysCmd[5] ScLine[12] ScLine[14] ScLine[15] Vcc Vcc SysCmd[6] SysCmd[4] SysCmd[1] ScLine[8] ScLine[10] ScLine[13] Vss Vss SysCmd[3] SysCmd[2] SysADC[7] ScLine[5] ScLine[7] ScLine[11] Vcc Vcc SysCmd[0] SysCmdP SysADC[1] ScLine[2] ScLine[4] ScLine[9] Vss Vcc SysADC[5] SysADC[3] BigEndian SysAD[49] R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 SysAD[51] SysAD[55] SysAD[27] SysAD[31] SysAD[43] SysAD[39] SysAD[35] SysAD[1] ScWord[1] ScLine[0] ScLine[3] ScLine[6] Vss Vss SysAD[15] SysAD[47] SysAD[17] SysAD[19] SysAD[23] SysAD[57] SysAD[29] Vcc SysAD[45] SysAD[41] SysAD[7] SysAD[5] SysAD[33] Reset* ScLine[1] Vcc Vcc Vcc Vcc Vss SysAD[21] SysAD[53] SysAD[25] SysAD[59] SysAD[61] Pkg Pin Function U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 SysAD[63] SysAD[13] SysAD[11] SysAD[9] SysAD[37] SysAD[3] ScWord[0] Vcc Vss Vss Vss Vss Vcc Vss Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vcc Vss Vss Vcc Vss Table 3. 223-Pin CPGA Pinout 13 IDT RC5000 COMMERCIAL TEMPERATURE RANGE 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K 272-Ball SBGA L M N P R T U V W Y AA Figure 3. Ball Grid Array Package (Bottom View) 14 IDT RC5000 COMMERCIAL TEMPERATURE RANGE 272-Ball SBGA Pinout Pkg Pin Function Pkg Pin Function Pkg Pin Function Pkg Pin Function Pkg Pin Function AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 Vss Vcc Vss ValidOut* Vss Int*0 Vss Reserved Vss WrRdy* Vss ScMatch Vss SysCmd6 Vss SysCmd2 Vss SysADC3 Vss Vcc Vss Vss Vcc Vss SysAD32 Vss ScCWE*1 Vss VCCOK Vss MasterClk Vss ScLine15 Vss ScLine12 Vss ScLine7 Vss ScLine2 Vss Vcc Vss Vcc Vcc Vcc SysAD2 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 D1 D2 D3 D4 D5 D6 D7 D8 SysAD0 ScTOE* ScCLR* ScTDE* ModeClock JTDI JTCK N/C ScLine14 ScLine10 ScLine9 ScLine6 ScLine3 ScLine1 Vcc Vcc Vcc Vss Vcc ColdReset* SysAD34 ScDCE*1 ScDCE*0 ScCWE*0 ScTCE* ModeIn JTDO Vssp JTMS ScLine13 ScLine11 ScLine8 ScLine5 ScLine4 ScLine0 Reset* Vcc Vss Vcc Vcc Vcc Vss Vcc Vss Vcc Vcc D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 E1 E2 E3 E4 E18 E19 E20 E21 F1 F2 F3 F4 F18 F19 F20 F21 G1 G2 G3 G4 G18 G19 G20 G21 H1 H2 H3 H4 H18 H19 H20 H21 J1 Vss Vcc Vccp Vcc Vss Vcc Vcc Vss Vcc Vss Vcc Vcc Vcc Vss SysAD36 SysAD4 Vcc Vcc ScWord1 ScWord0 Vss SysAD8 SysAD38 SysAD6 Vss Vss SysAD1 SysAD33 SysAD3 Vss SysAD10 SysAD40 Vcc Vcc SysAD35 SysAD5 Vss SysAD42 SysAD44 SysAD12 Vcc Vcc SysAD7 SysAD39 SysAD37 Vss J2 J3 J4 J18 J19 J20 J21 K1 K2 K3 K4 K18 K19 K20 K21 L1 L2 L3 L4 L18 L19 L20 L21 M1 M2 M3 M4 M18 M19 M20 M21 N1 N2 N3 N4 N18 N19 N20 N21 P1 P2 P3 P4 P18 P19 P20 SysAD46 SysAD14 Vss Vss SysAD9 SysAD41 Vss SysAD60 SysAD30 SysAD62 Vcc Vcc SysAD11 SysAD43 SysAD13 Vss SysAD58 SysAD28 Vcc Vcc SysAD45 SysAD63 Vss SysAD26 SysAD56 SysAD24 Vcc Vcc SysAD29 SysAd61 SysAD31 Vss SysAD54 SysAD22 Vss Vss SysAD27 SysAD59 Vss SysAD50 SysAD52 SysAD20 Vcc Vcc SysAD25 SysAD57 P21 R1 R2 R3 R4 R18 R19 R20 R21 T1 T2 T3 T4 T18 T19 T20 T21 U1 U2 U3 U4 U18 U19 U20 U21 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 SysAD55 Vss SysAD18 SysAD48 Vcc Vcc SysAD53 SysAD23 Vss SysAD16 SysADC0 SysADC2 Vss Vss SysAD19 SysAD51 SysAD21 Vss SysADC4 SysADC6 Vcc Vcc SysAD17 SysAD49 Vss Vcc Vcc Vcc Vss NMI* Vss Vcc Vcc Vss Vcc Vcc Vcc Vss Vcc Vcc Vss Vcc Vss Vcc Vcc Vcc Pkg Pin Function W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Vss Vcc Vcc Vcc Int*5 Int*4 Int*1 Reserved Reserved Reserved ValidIn* ScDOE* SysCmd7 SysCmd4 SysCmd1 SysADC7 SysADC5 SysAD47 BigEndian Vcc Vss Vcc Vcc Vcc Release* Int*3 Int*2 ScValid Reserved Reserved Reserved ExtRqst* RdRdy* SysCmd8 SysCmd5 SysCmd3 SysCmd0 SysCmdP SysADC1 SysAD15 Vcc Vcc Table 4. 272-Ball SBGA Pinout 15 IDT RC5000 COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT79 YY Operating Voltage XXXX 999 Device Type Speed A Package A Temp range/ Process Blank Commercial (0°C to +85°C Case) G BS 223-pin CPGA 272-pin SBGA 180 200 250 180 MHz PClk 200 MHz PClk 250 MHz PClk 5000 Multi-Issue 64-bit Microprocessor RV 3.3+/-5% VALID COMBINATIONS IDT79RV5000 - 180, 200MHz G IDT79RV5000 - 180, 200, 250MHz BS CPGA package SBGA package Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product. Integrated Device Technology, Inc. 2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 FAX 408-492-8674 16