CA3260, CA3260A ® Data Sheet February 7, 2006 4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output CA3260A and CA3260 are integrated circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA3260 series circuits are dual versions of the popular CA3160 series. FN1266.6 Features • MOSFET Input Stage provides - Very High ZI = 1.5TΩ (1.5 x 1012Ω) (Typ) - Very Low II . . . . . . . . . . . . 5pA (Typ) at 15V Operation . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation • Ideal for Single Supply Applications Gate protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. • Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail A complementary symmetry MOS (CMOS) transistor pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. Applications The CA3260 Series circuits operate at supply voltages ranging from 4V to 16V, or ±2V to ±8V when using split supplies. The CA3260A offers superior input characteristics over those of the CA3260. • Long Duration Timers/Monostables PART MARKING TEMP. RANGE (°C) • Pb-Free Plus Anneal Available (RoHS Compliant) • Ground Referenced Single Supply Amplifiers • Fast Sample-Hold Amplifiers • Ideal Interface with Digital CMOS • High Input Impedance Wideband Amplifiers • Voltage Followers (e.g. Follower for Single Supply D/A Converter) Ordering Information PART NUMBER • CMOS Output Stage Permits Signal Swing to Either (Or Both) Supply Rails PACKAGE PKG. DWG. # • Voltage Regulators (Permits Control of Output Voltage Down to 0V) CA3260E CA3260E -55 to 125 8 Ld PDIP E8.3 • Wien Bridge Oscillators CA3260EZ (Note) CA3260EZ -55 to 125 8 Ld PDIP* (Pb-free) E8.3 • Voltage Controlled Oscillators CA3260AE CA3260AE -55 to 125 8 Ld PDIP E8.3 -55 to 125 8 Ld PDIP* (Pb-free) E8.3 CA3260AEZ 3260AEZ (Note) • Photo Diode Sensor Amplifiers Pinout CA3260, CA3260A (PDIP) TOP VIEW *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 OUTPUT (A) 1 8 V+ 7 OUTPUT (B) 6 INV. INPUT (B) 5 NON INV. INPUT (B) A INV. INPUT (A) 2 - + B NON INV. INPUT (A) 3 V- 4 + - CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA3260, CA3260A Absolute Maximum Ratings Thermal Information DC Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . 16V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Operating Conditions *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25°C, Typical Values Intended Only for Design Guidance TYPICAL VALUES PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 UNITS Input Resistance RI VS = ±7.5V 1.5 1.5 TΩ Input Capacitance CI f = 1MHz, VS = ±7.5V 4.3 4.3 pF Unity Gain Crossover Frequency fT VS = ±7.5V 4 4 MHz SR VS = ±7.5V Slew Rate Transient Response Rise Time tr Overshoot OS Settling Time (to <0.1%, VIN = 4VP-P) tS 10 10 V/µs CL = 25pF, RL = 2kΩ, AV = +1, VS = ±7.5V 0.09 0.09 µs 10 10 % CL = 25pF, RL = 2kΩ, AV = +1, VS = ±7.5V 1.8 1.8 µs Input Offset Voltage VIO V+ = 5V, V- = 0V 2 6 mV Input Offset Current IIO V+ = 5V, V- = 0V 0.1 0.1 pA II V+ = 5V, V- = 0V 2 2 pA CMRR V+ = 5V, V- = 0V 70 60 dB VO = 4VP-P, RL = 20kΩ, V+ = 5V, V- = 0V 100 100 kV/V 100 100 dB 0 to 2.5 0 to 2.5 V 1 1 mA Input Current Common Mode Rejection Ratio Large Signal Voltage Gain AOL Common Mode Input Voltage Range VICR Supply Current I+ Power Supply Rejection Ratio PSRR Electrical Specifications V+ = 5V, V- = 0V VO = 5V, RL = ∞, V+ = 5V, V- = 0V VO = 2.5V, RL = ∞, V+ = 5V, V- = 0V 1.2 1.2 mA ∆VIO/∆V+, V+ = 5V, V- = 0V 200 200 µV/V For Each Amplifier at TA = 25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage |VIO| VS = ±7.5V - 2 5 - 6 15 mV Input Offset Current |IIO| VS = ±7.5V - 0.5 20 - 0.5 30 pA II VS = ±7.5V - 5 30 - 5 50 pA 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB CMRR 80 95 - 70 90 - dB VlCR 0 -0.5 to 12 10 0 -0.5 to 12 10 V Input Current Large Signal Voltage Gain AOL Common Mode Rejection Ratio Common Mode Input Voltage Range 2 VO = 10VP-P, RL = 10kΩ FN1266.6 February 7, 2006 CA3260, CA3260A Electrical Specifications For Each Amplifier at TA = 25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) PARAMETER CA3260A TEST CONDITIONS SYMBOL CA3260 MIN TYP MAX MIN TYP MAX UNITS Power Supply Rejection Ratio PSRR ∆VIO/∆V+ V+ = 17.5V - 32 150 - 32 320 µV/V Maximum Output Voltage VOM+ RL = 10kΩ 11 13.3 - 11 13.3 - V - 0.002 0.01 - 0.002 0.01 V 14.99 15 - 14.99 15 - V - 0 0.01 - 0 0.01 V 12 22 45 12 22 45 mA 12 20 45 12 20 45 mA VO (Amplifier A) = 7.5V VO (Amplifier B) = 7.5V - 9 15.5 - 9 15.5 mA VO (Amplifier A) = 0V VO (Amplifier B) = 0V - 1.2 3 - 1.2 3 mA VO (Amplifier A) = 0V VO (Amplifier B) = 7.5V - 5 8.5 - 5 8.5 mA - 6 - - 8 - µV/°C - 120 - - 120 - dB VOMRL = ∞ VOM+ VOMMaximum Output Current IOM+ Source VO = 7.5V IOM- Sink Total Supply Current RL = ∞ I+ ∆VIO/∆T Input Offset Voltage Temperature Drift Crosstalk f = 1kHz Schematic Diagram 8 V+ AMPLIFIER A Q11 AMPLIFIER B Q7 Q6 Q10 Q21 Q9 D2 D6 D4 R5 2K Q1 Q2 Q14 R6 200K Q13 R4 1K R3 1K D8 Q16 Q15 C2 30pF R11 1K Q18 R2 1K R9 1K 2 1 7 6 Q26 R10 Q27 1K Q19 Q4 R1 1K 3 Q22 Q5 Q3 R7 300K Q8 Q24 D7 D5 R12 2K C1 30pF Q25 Q23 D3 D1 Q12 Q20 Q17 Q28 R14 300Ω R8 1K 5 R13 200K 4 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 3 FN1266.6 February 7, 2006