EL4511 ® Data Sheet July 21, 2005 FN7009.7 Super Sync Separator Features The EL4511 sync separator IC is designed for operation in the next generation of DTV, HDTV, and projector applications, as well as broadcast equipment and other applications where video signals need to be processed. • Composite, component, HDTV, and PC signal-compatible The EL4511 accepts sync on green, separate sync, and H/V sync inputs, automatically selecting the relevant format. It is also capable of detecting and decoding tri-level syncs used with the latest HD systems. Unlike standard sync separators, the EL4511 can automatically detect the line rate and locks to it, without the use of an external RSET resistor. • 150kHz max line rate The EL4511 is available in a 24-pin QSOP package and operates over the full 0°C to 70°C temperature range. • Auto sync detection • Low power • Small package outline • 3.3V and 5V operation • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • HDTV/DTV analog inputs Ordering Information PART NUMBER • Tri-level & bi-level sync-compatible • Video projectors PACKAGE TAPE & REEL PKG. DWG. # EL4511CU 24-Pin QSOP - MDP0040 • Set top boxes EL4511CU-T7 24-Pin QSOP 7” MDP0040 • Security video EL4511CU-T13 24-Pin QSOP 13” MDP0040 • Broadcast video equipment EL4511CUZ (See Note) 24-Pin QSOP (Pb-Free) - MDP0040 EL4511CUZ-T7 (See Note) 24-Pin QSOP (Pb-Free) 7” MDP0040 EL4511CUZ-T13 (See Note) 24-Pin QSOP (Pb-Free) 13” MDP0040 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 • Computer monitors Pinout EL4511 (24-PIN QSOP) TOP VIEW XTAL 1 VBLANK 2 SYNCLOCK 3 PDWN 4 SDENB 5 24 XTALN 23 ODD/EVEN 22 VERTOUT 21 HOUT 20 BACKPORCH SCL 6 19 SYNCOUT SDA 7 18 VCCD GNDD1 8 17 GNDD2 HIN 9 16 GNDA2 SYNCIN 10 15 VCCA2 VERTIN 11 14 VCCA1 LEVEL 12 13 GNDA1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303 Manufactured under License, U.S. Patents 5,486,869; 5,754,250 EL4511 Absolute Maximum Ratings (TA = 25°C) Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS to GND) +6V Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V, VS +0.3V VCCA1, VCCA2 & VCCD . . . . . . . . . . . . . . . .Must Be Same Voltage Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT (Note 1) 15 20 mA Standby PDWN = VCCD (Note 2) 4 20 µA Rate Acquisition Oscillator Supply Current (Note 1) 3 20 mA 2.5 20 µA Analog Processing Supply Current (Note 1) 3 20 mA Standby PDWN = VCCD (Note 2) 3 20 µA 600 mV GENERAL ISD ISA2 ISA1 Digital Supply Current Standby PDWN = VCCD COMPOSITE SYNC INPUT AT SYNCIN VSYNC Sync Signal Amplitude AC coupled to SYNCIN pin (Notes 1 & 3) VSLICE Slicing Level of Sync Signal After sync lock is attained, see description 140 50 % 1.4 V HORIZONTAL AND VERTICAL INPUT AT HIN, VERTIN HSLICE, VSLICE Slice Level of HIN and VERTIN THINL H Sync Width (Bi-Level) 3 (Tri-Level) Minimum Sync Width 12.8 1.4 % of H time % of H time FHINH H Sync Frequency 10.75 150 kHz TVINL V Sync Width 2 7 H lines FVINH V Sync Frequency 23 100 Hz 1.6mA, VCCD = 5V GNDD+0.4 V 1.6mA, VCCD = 3.3V GNDD+0.5 LOGIC OUTPUT SIGNALS, HOUT, VOUT, VBLANK, BACKPORCH, ODD/EVEN, SYNCLOCK O/PLOW O/PHI Logic Low State Logic High State 1.6mA, VCCD = 5V VCCD-0.4 1.6mA, VCCD = 3.3V VCCD-0.5 TdHOUT HOUT Timing Relative to Input TdSYNCOUT SYNCOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 TdBACKPORCH BACKPORCH Timing Relative to Input V See timing diagrams 1, 2, 3 & 4 See timing diagrams 1, 2, 3 & 4 LEVEL OUTPUT DRIVER, LEVEL VLEVEL 2 X Amplitude of VSYNC ZLEVEL O/P Resistance of Driver Stage 2 Refer to description of operation 1.9x 2.15x 450 2.4x Ω FN7009.7 July 21, 2005 EL4511 Electrical Specifications PARAMETER VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 50 kHz REFERENCE OSCILLATOR FIN Reference Input Frequency Refer to description of operation FXTAL Crystal Frequency Watch crystal (optional) 32.768 kHz CONTROL INTERFACE SIGNALS PDWN, SDENB, SCL AND SDA VHIGH Input Logic High Threshold VCCD-1V VLOW Input Logic Low Threshold O/PVHI SDA O/P Logic High State @ 1mA O/PVLOW SDA O/P Logic Low State @ 1mA FSCL Serial Control Clock Frequency 5 MHz TCLS Setup Time 30 ns TCLH Hold Time 30 ns TLC Load to Clock Time 30 ns TDC Hold to Clock Time 30 ns TCD Clock to Data Out Time 30 ns VGNDD+1V VCCD-0.4 V GNDD+0.4 V NOTES: 1. NTSC signal; see curves for other rates. 2. XTAL pin must be low, otherwise 70µA. 3. I/P range reduces if VS of 3.3V - 4.5V (see Timing Diagram 1). 3 FN7009.7 July 21, 2005 EL4511 Pin Descriptions PIN NUMBER PIN NAME PIN TYPE PIN DESCRIPTION 1 XTAL Input 2 VBLANK Logic Output Vertical blank output 3 SYNCLOCK Logic Output Indicates that the EL4511 has locked to the line rate and has found three consecutive “good H lines” 4 PWDN Logic Input Power-down = hi 5 SDENB Logic Input Serial interface enable = low 6 SCL Logic Input Serial clock 7 SDA Logic BIDIR Serial data (input for chip setup, output for diagnostic information) 8 GNDD1 Power Digital ground 1 9 HIN Input Horizontal sync 10 SYNCIN Input Video input, which may incorporate sync signal; connect to Y or G 11 VERTIN Input Vertical sync input 12 LEVEL Output Indicates 2x amplitude of sync tip vs. back porch; referred to ground 13 GNDA1 Power Analog ground 1 14 VCCA1 Power Analog power supply 1 15 VCCA2 Power Analog power supply 2 16 GNDA2 Power Analog ground 2 17 GNDD2 Power Digital ground 2 18 VCCD1 Power Digital power supply 1 19 SYNCOUT Logic Output Composite sync output 20 BACKPORCH Logic Output Back porch output 21 HOUT Logic Output Horizontal sync output 22 VERTOUT Logic Output Vertical sync output 23 ODD/EVEN Logic Output Odd-Even field indicator output 24 XTALN Output Crystal input (see Table 2 for details) Crystal output (see Table 2 for details) Typical Performance Curves 1.2 1.2 1.136W 1 θ JA 0.8 0.6 Q =8 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD SO P2 8° 4 C/ W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 4 1 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 870mW 0.8 θ JA 0.6 0.4 Q SO = 1 P2 4 15 °C /W 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7009.7 July 21, 2005 EL4511 VCCA1 VERTICAL SYNC VCCD VERTIN COMPOSITE SYNC SYNCIN HORIZONTAL SYNC HIN SLICING & ANALOG PROCESSING DIGITAL PROCESSING POWER DOWN PDWN LOW ACTIVE SERIAL DATA ENABLE SDENB SERIAL CLOCK SCL SERIAL DATA SDA RESET SERIAL I/F GNDA1 RATE ACQUISITION OSCILLATOR REFERENCE OSCILLATOR LEVEL SYNC LEVEL HOUT HORIZONTAL O/P SYNCOUT COMP SYNC O/P VERTOUT VERTICAL O/P VBLANK VERTICAL BLANKING O/P BACKPORCH BACK PORCH O/P ODD/EVEN ODD/EVEN O/P SYNCLOCK SYNC LOCK O/P GNDD1 GNDD2 VCCA2 GNDA2 XTALIN XTAL MODE CONTROL PINS FIGURE 3. BLOCK DIAGRAM 5 FN7009.7 July 21, 2005 EL4511 COMPOSITE VIDEO INPUT, FIELD ONE 1 H Sync Interval 3H 2 3 Start of H Field One Pre-Equalizing Pulse Interval .H 4 3H 5 6 7 3H 8 9 10 .5H H V Sync Pulse Interval 9 Line Vertical Interval 19 20 21 H Post-Equalizing Pulse Interval SYNC OUT OUTPUT VOUT OUTPUT tVS ODD/EVEN OUTPUT BACKPORCH OUTPUT HOUT OUTPUT VBLANK Notes: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). FIGURE 4. EXAMPLE OF VERTICAL INTERVAL (525) 6 FN7009.7 July 21, 2005 EL4511 COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE START OF FIELD ONE 622 623 624 625 1 2 3 4 5 6 7 23 24 SYNCOUT OUTPUT VOUT OUTPUT TVS ODD/EVEN OUTPUT BACKPORCH OUTPUT HOUT OUTPUT V BLANK OUTPUT Notes: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). FIGURE 5. EXAMPLE OF VERTICAL INTERVAL (625) 7 FN7009.7 July 21, 2005 EL4511 SYNCIN 1123 1124 1125 1 2 3 4 5 6 7 8 ... 21 569 570 ... 583 SYNCOUT HOUT BACKPORCH VOUT VBLANK DEFAULT 20 LINES ODD FIELD ODD/EVEN SYNCIN 560 561 562 563 564 565 566 567 568 SYNCOUT HOUT BACKPORCH VOUT VBLANK DEFAULT 20 LINES ODD/EVEN EVEN FIELD FIGURE 6. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD 8 FN7009.7 July 21, 2005 EL4511 Default 20 Lines Default 20 Lines FIGURE 7. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED ODD & EVEN FIELD (1250 LINES) 9 FN7009.7 July 21, 2005 EL4511 Timing Diagram 1 - Example of Horizontal Interval 525/625 Line Composite CONDITIONS: VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NO FILTER (REGISTER 2 BIT 4 = 0) WHITE LEVEL COLOR BURST INPUT DYNAMIC SYNC LEVEL RANGE 0.5V-2V (@VCCA1=5V) SYNC IN 0.5V-1V (@VCCA1=3.3V) VIDEO VBLANK (BLANKING LEVEL VOLTAGE) VSLICE 50% SYNC TIP tdSYNCOUT SYNC VSYNC (SYNC TIP VOLTAGE) DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL SYNC OUT HOUT tdHOUT THOUT TBACKPORCH BACKPORCH tdBACKPORCH No Filter PARAMETER DESCRIPTION CONDITIONS TYP (Note 1) UNIT tdSYNCOUT SYNCOUT Timing Relative to Input See Timing Diagram 1 65 ns tdHOUT HOUT Timing Relative to Input See Timing Diagram 1 470 ns tdBACKPORCH BACKPORCH Timing Relative to Input See Timing Diagram 1 525 ns THOUT Horizontal Output Width See Timing Diagram 1 1545 ns TBACKPORCH BACKPORCH (Clamp) Width See Timing Diagram 1 3345 ns NOTE: 1. Delay variation is less than 2.5ns over temperature range. 10 FN7009.7 July 21, 2005 EL4511 Timing Diagram 2 - Example of Horizontal Interval 525/625 Line Composite CONDITIONS: VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, FILTER IN (REGISTER 2 BIT 4 = 1) WHITE LEVEL COLOR BURST INPUT SYNC LEVEL DYNAMIC RANGE 0.5V-2V (@VCCA1=5V) SYNC IN 0.5V-1V (@VCCA1=3.3V) 50% VIDEO VBLANK (BLANKING LEVEL VOLTAGE) VSLICE SYNC TIP tdSYNCOUT SYNC VSYNC (SYNC TIP VOLTAGE) DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL SYNC OUT HOUT tdHOUT THOUT TBACKPORCH BACKPORCH tdBACKPORCH Filter In PARAMETER DESCRIPTION CONDITIONS TYP (Note 1) UNIT tdSYNCOUT SYNCOUT Timing Relative to Input See Timing Diagram 2 220 ns tdHOUT HOUT Timing Relative to Input See Timing Diagram 2 470 ns tdBACKPORCH BACKPORCH Timing Relative to Input See Timing Diagram 2 525 ns THOUT Horizontal Output Width See Timing Diagram 2 1545 ns TBACKPORCH BACKPORCH (Clamp) Width See Timing Diagram 2 3345 ns NOTE: 1. Delay variation is less than 2.5ns over temperature range. 11 FN7009.7 July 21, 2005 EL4511 Timing Diagram 3 - Example of Horizontal Interval (HDTV) (720p) CONDITIONS: VCCA1 = VCCA2 = VCCD = +3.3V/+5V, TA = 25°C, NO FILTER (REGISTER 2 BIT 4 = 0) SYNCIN tdSYNCOUT SYNC OUT HOUT tdHOUT THOUT TBACKPORCH BACKPORCH tdBACKPORCH H Timing for HDTV, No Filter (using 720p input signal) PARAMETER DESCRIPTION CONDITIONS TYP TYP @ 5V @ 3.3V (Note 1) (Note 1) UNIT tdSYNCOUT SYNCOUT Timing Relative to Input See Timing Diagram 3 56 50 ns tdHOUT HOUT Timing Relative to Input See Timing Diagram 3 48 36 ns tdBACKPORCH BACKPORCH Timing Relative to Input See Timing Diagram 3 150 140 ns THOUT Horizontal Output Width See Timing Diagram 3 275 275 ns TBACKPORCH BACKPORCH (Clamp) Width See Timing Diagram 3 300 300 ns NOTE: 1. Delay variation is less than 2.5ns over temperature range. 12 FN7009.7 July 21, 2005 EL4511 Timing Diagram 4 - Example of Horizontal Interval (HDTV) CONDITIONS: VCCA1 = VCCA2 = VCCD = +3.3V/+5V, TA = 25°C, FILTER (REGISTER 2 BIT 4 = 1) SYNCIN SYNC OUT tdSYNCOUT HOUT tdHOUT THOUT TBACKPORCH BACKPORCH tdBACKPORCH H Timing for HDTV, With Filter (using 720p input) PARAMETER DESCRIPTION CONDITIONS TYP TYP @ 5V @ 3.3V (Note 1) (Note 1) UNIT tdSYNCOUT SYNCOUT Timing Relative to Input See Timing Diagram 4 120 110 ns tdHOUT HOUT Timing Relative to Input See Timing Diagram 4 112 100 ns tdBACKPORCH BACKPORCH Timing Relative to Input See Timing Diagram 4 155 140 ns THOUT Horizontal Output Width See Timing Diagram 4 300 300 ns TBACKPORCH BACKPORCH (Clamp) Width See Timing Diagram 4 300 300 ns NOTE: 1. Delay variation is less than 2.5ns over temperature range. 13 FN7009.7 July 21, 2005 Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 OPERATING STANDARD PINS 1 & 24 XTAL, DEFAULT XTALN DIGITAL FILTER ENABLED SYNC LOCK V BLANK O/E VOUT HOUT BACK PORCH SYNC OUT COMMENTS SDTV (Clean signals) 14 525 NTSC Yes 00 default Correct Correct Correct Correct Correct Correct Correct 625 PAL Yes 00 default Correct Correct Correct Correct Correct Correct Correct 625 SECAM Yes 00 default Correct Correct Correct Correct Correct Correct Correct 525 NTSC Yes 00 default Correct Correct Correct Correct Correct Correct Will break up with Fast Forward and Fast Reverse modes. 625 PAL Yes 00 default Correct Correct Correct Correct Correct Correct Will break up with Fast Forward and Fast Reverse modes. 625 SECAM Yes 00 default Correct Correct Correct Correct Correct Correct Will break up with Fast Forward and Fast Reverse modes. Macrovision VHS O/P Yes 00 default Macrovision DVD O/P Yes 00 default SDTV (VHS tape signals) See Note See Note Bad See Note See Note See Note See Note See Note See Note This operation works on most machines, but some combinations will fail See Note See Note See Note See Note See Note Short drop out on one field, likely some machines will fail. EDTV Bi-Level Sync No O/E output for some of these standards, because no serrations during vertical 480 I / (29/30) Yes 00 default Correct Correct Always H Correct Correct Correct Correct 480 I / (59/60) Yes 00 default Correct Correct Always H Correct Correct Correct Correct 480 P / (59/60) Yes 00 default Correct Correct Always H Correct Correct Correct Correct 576 P / (50) Yes 00 default Correct Correct Always H Correct Correct Correct Correct 720 P / (59/60) Yes 00 default Correct Correct Always H (correct) Correct Correct Correct Correct 1080 I /24 Yes 00 default Correct Correct Correct Correct Correct Correct Correct 1080 I / 25 Yes 00 default Correct Correct Correct Correct Correct Correct Correct HDTV Tri-Level Sync EL4511 SDTV (525 only) FN7009.7 July 21, 2005 Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 (Continued) PINS 1 & 24 XTAL, DEFAULT XTALN OPERATING STANDARD DIGITAL FILTER ENABLED SYNC LOCK V BLANK O/E VOUT HOUT BACK PORCH SYNC OUT 15 1080 I / (29/30) Yes 00 default Correct Correct Correct Correct Correct Correct Correct 1080 I / (48/50) Yes 00 default Correct Correct Correct Correct Correct Correct Correct 1080 I / (59/60) Yes 00 default Correct Correct Correct Correct Correct Correct Correct 1035 I / (29/30) Yes 00 default Correct Correct Correct Correct Correct Correct Correct 1080 P / (24/35/30/50/59/60) Yes 00 default Correct Correct Always H (correct) Correct Correct Correct Correct COMMENTS VGA All standards generated by the Quantum are supported except 1024@42Hz and work OK Yes 11 default Correct Correct Always H Correct Correct Correct Correct 720 Yes 11 default Correct Correct Always H Correct Correct Correct Correct 800/X (5 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct 1024/X (4 of 5 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct 1152 Yes 11 default Correct Correct Always H Correct Correct Correct Correct 1280/X (5 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct 1600/X (5 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct 1792/X (2 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct 1836/X (2 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct Max Line rate 112.5kHz 1920/X (2 standards) Yes 11 default Correct Correct Always H Correct Correct Correct Correct Max Line rate 112.5kHz 1024@42 not supported EL4511 640 /X (6 standards) FN7009.7 July 21, 2005 EL4511 Timing Diagram 5 - 720p Standard with Filter in Circuit This waveform shows the output jitter present on the HOUT signal. The oscilloscope is triggered from the positive reference edge of the composite sync output. Description of Operation The EL4511 has 3 modes of operation. The first is default mode with pins 1 and 24 connected to ground with 10K. Second is using pins 1 and 24 to provide simple mode control. The third is using the serial port to use a crystal or a clock into XTALN pin 24 to determine the video sync rate and/or more extensive mode control. The EL4511 incorporates the following functional blocks: • Analog I/Ps, processing, and slicing • Signal source and polarity detector • Signal & H rate acquisition block • Advanced sync separator which will detect both conventional and tri-level sync signals • Video lock and level indicators • Reference counter • Computer and control interface Analog I/Ps, Processing, and Slicing The EL4511 has three I/P pins which may be connected to a source of external sync signals. For YPrPb or RGB applications, Y or G should be connected to SYNCIN. For applications with separate horizontal and vertical sync inputs, these should be connected to HIN and VERTIN, respectively. (HIN may also be used for composite sync without video.) Composite video input signals should be connected to SYNCIN. This should be AC coupled from a low impedance source. The input resistance is in the order of 100kΩ. After H lock is obtained, this signal will be “soft clamped” (5kΩ) to approximately 20% of the VCCA1 voltage. In the default mode, the clamping action ensures that the correct slicing levels will be used throughout the field. (Serial Mode) This operation can be modified through Register 9. The soft clamp can be disabled by setting bit 3 to 16 Hi. Setting bit 1 to high will disconnect the input bias network. Once the acquisition process is complete (see below for description), the slice level will be adaptive. The sync signal is measured from sync tip to blanking level; (Tri-level is measured between negative and positive sync tips). The slice level is then set to 50% of these levels. (Serial Mode) It is possible to force the slicing level to remain at the fixed level of 78mV above the sync tip; Register 2, bit 5 is set High to do this. This can help when dealing with signal that have bursts of noise, or formats that have signals that will modify the sync amplitude measurement process. VGA type of signals will be connected to the HIN and VERTIN pins (use HIN for combined H & V). These are DC coupled signals; they will be sliced at a fixed level of approximately 1.4V. These inputs may be any combination of positive and negative polarities; the EL4511 will invert as required to keep the outputs in the correct polarity. (Serial Mode) This polarity correction process may be modified with Register 4 bits 3:0. Signal and Horizontal Rate Acquisition Block On power-up, if both HIN and SYNCIN are enabled; the EL4511 will slice the SYNCIN input at 78mV above the negative sync tip level and monitor the sliced signal for up to 320µs. If a periodic signal within the specified frequency limits is found to be present, this is assumed to be the horizontal frequency. If no signal is found, the EL4511 will switch to slice and monitor the HIN input at a TTL level. The EL4511 will continue to monitor these two signals in turn until an appropriate signal is detected. If only one of HIN and SYNCIN is enabled, the EL4511 will continuously monitor the selected signal until an appropriate signal is detected; this will give a shorter lock time where only one type of signal is used. At this point, the rate acquisition oscillator lock process (to the H rate signal) will begin. FN7009.7 July 21, 2005 EL4511 Video Format Switching The part should be powered down for at least 500µs to reset the internal registers when the input video signal is switched from one video format to another video format. It is possible the part will generate wrong outputs if it is not powered down between two different input video signals. USE OF THE POWER DOWN FUNCTION The Power down pin (pin 4) can be used to hard reset the internal circuit of the EL4511. To disable the internal circuit, just apply a 5V to the power down pin. To enable the internal circuit, just apply a 0V to the power down pin. The SYNCLOCK pin 3 minus edge can be used to generate a 5V 500µs pulse to the PDWN pin 4 to reset the internal digital registers automatically when the video input has a changed video format. VDD R2 10K R1 Sync_Lock pin 20K C1 Q1 MPS3906 0.022u POWERDOWN R3 100K 0 Horizontal Rate Acquisition Oscillator This oscillator is frequency locked to 512 times the horizontal rate. This clock signal generates the timing and gating signals that are employed internally by the EL4511. This operation is entirely automatic and requires no input from the external circuitry or microprocessor. (Serial Mode) It is possible to gain access to this oscillator O/P by changing the assignment of pin 2 (VBLANK) or pin 23 (ODD/EVEN). Register 6, bits 7:6 make this selection; see Table 1 for allocations. TABLE 1. ACQUISITION CLOCK MULTIPLEXER CmuxCtrl ACTION Reg6 b7 b6 0 0 Normal Operation 0 1 Clock multiplexed onto Odd/Even (pin 23) 1 0 Clock multiplexed onto VBLANK (pin 2) 1 1 Reserved 17 (Serial Mode) The oscillator frequency is adjusted at the beginning of the line. At the time of frequency adjustment the clock O/P may have a phase discontinuity. Advanced Sync Separator Once the line rate has been determined, the signal can be analyzed by the advanced sync separator. This has been designed to be compatible with a wide range of video standards, operating with horizontal line rates up to 150kHz. PAL/NTSC/SECAM; HDTV, including bi-level and tri-level sync Standards and computer display syncs. The EL4511 can be programmed to disable the detection of either bi-level or tri-level sync signals or to prioritize the detection of one sync signal type over the other. If the vertical sync input pin, VERTIN, is enabled, the EL4511 will automatically detect whether a valid signal is present on that pin, and incorporate that signal into the algorithm. Otherwise, the input signal on which the horizontal sync was detected will be treated as a composite sync. The sync separator also includes a qualification scheme which rejects high frequency noise and other video artifacts, such as color burst. The horizontal line rate is automatically acquired from the signal (see above.) A digital filter is included in the signal path to remove noise and glitches; this may be removed if the extra delay it incurs needs to be removed. (Serial Mode) Setting register 2, bit 4 to Low will remove the filter. After the signal has been identified and the qualification process is complete, the SYNCLOCK pin will go high and the output waveforms will be enabled. (Serial Mode) These may be enabled all the time by setting register 1, bit 6 to a high state. This can help noisy and varying signals as the revalidation does not have to take place before the signals are available at the outputs, See Figures 4 through 7 for examples of various types of input signal. Part of the signal recognition algorithm uses the number of horizontal lines between vertical pulses. A counter is clocked by the Hclock, this counter is also used to generate vertical timing pulses. (Serial Mode) This count information is available via the serial I/F; this is a 12 bit number. (Serial Mode) The lines per frame count is available at register 8, bits 7:4 for the MSBs; the LSBs are available at register 7, bits 7:0. Register 8, bit 2 indicates that the lines/frame counter has been updated when it is high. This counter also generates the VBLANK waveform. Using a look up table, the default blanking is based on number of lines in the field. (Serial Mode) This operation may be disabled by setting register 3, bit 7 to a low. As this is dependent on application and product usage, this may be modified. Register 3, bits 6:0 will set the number of horizontal lines after VERTOUT leading edge. Register 4, bits 7:4 sets the number of lines before the VERTOUT leading edge. FN7009.7 July 21, 2005 EL4511 Video Lock and Level Indicators Applications Examples Loss of video signal can be detected by monitoring the SYNCLOCK pin 3. This pin goes high once the sync separator has detected a valid sync signal and goes low if this signal is lost for more than 20 successive lines. (Serial Mode) This signal is also available at register 14 pin 5. Other lock acquisition signals available from the system are listed in Table 4. The following examples show how a system may be configured to operate the EL4511. The sync tip amplitude is buffered with a nominal gain of 2.15 to produce a positive, ground-referenced signal on the LEVEL pin. This output can be used for AGC applications. Decode Mode In order to allow more flexibility when operating without a serial interface, the XTAL and XTALN pins are decoded by default to enable four control modes. These modes could be used to over-ride sync type used. See Table 2 for details. (Serial Mode) The all-signal type allowed mode is the same as the default mode when the crystal oscillator is enabled (set bit 6 of Reg9 to 1) except the countsPerField function is disabled in Reg13 and Reg14. The bi-level mode is for bi-level sync only, such as NTSC and PAL. The tri-level mode is for tri-level sync only, such as HDTV signals. The VGA only mode is for computer digital types of signals signal only. TABLE 2. MODE CONTROL USING PINS 1 & 24 The internal pull-up resistors on XTAL & XTALN are very high, these pins should use 10kΩ pull-up/down to operate when not using a crystal. By default, the EL4511 will wake up with Register 9, bit 6 set to Low. This will allow the use of logic levels on pins 1 & 24 to drive register1, bits 5:3 and register 2 bit 0 into the combinations shown in Table 2. (Serial Mode) To define the mode through the serial interface, the register 9, bit 6 must be set to High, the logic levels on pins 1 & 24 are no longer valid; (most likely now being an AC signal for the reference clock). DESCRIPTION 0 1 0 1 1 Tri-Level Only 0 1 0 1 0 1 Bi-Level Only 0 1 1 1 1 1 VGA only 1 X X Set by Serial I/F Crystal Oscillator is operational TTL HORIZ SYNCS TTL VERT SYNCS 9 15 0.1µF HIN GNDA2 16 75Ω 11 VERTIN VERTOUT 75Ω 100nF 10 75Ω 4 1 24 HOUT PDWN 21 HORIZ TIMING TO SYSTEM XTAL XTALN 8 10kΩ EL4511 SYNCIN 22 VERT TIMING TO SYSTEM SDA 0 0.1µF VCCA2 All signals enabled 7 0 SCL 0 GNDD2 0 6 0 17 0 VCCD 4.7µF 0 +5V 18 +5V + GNDA2 Register1 b5 b4 b3 13 Register9 b6 MODE CONTROL As there is no Microcontroller connected in this example, there is no need for a XTAL at pins 1 & 24. These pins are tied low, this enables the EL4511 to check for either type of input signal (See Table 2 for details.) 14 PIN 24 XTALN The EL4511 has the advantage that the sync separation is carried out over a wide frequency range without the need to adjust "RSET" as required by earlier generations of sync separators. VCCA1 PIN 1 XTAL In this example, the requirement is for vertical and horizontal timing to be generated from either an NTSC/PAL composite video waveform, or a computer generated image with separate TTL level syncs. GNDD1 ENXTAL Application 1 (minimum circuitry application) FIGURE 8. APPLICATIONS DRAWING 1 18 FN7009.7 July 21, 2005 EL4511 Application 2 (application using mode setting logic signals) adjust "RSET" as required by earlier generations of sync separators. In this example, the requirement is to provide the synchronizing information in a small display device. In this example the incoming sync signals may come from one of three sources. Computer, HDTV Set-top Box or an NTSC/PAL tuner. As there is no Microcontroller connected in this example, there is no need for a XTAL at pins 1 & 24. These pins can be used to force the EL4511 to select the correct operation (and speed up acquisition). Note that a Low Pas Filter is in the NTSC/PAL signal path to reduce noise, glitches and subcarrier. (In signals with bad Croma/Luma gain balance, the subcarrier can extend into the sync slicing level) (See Table 2 for details.) The EL4511 has the advantage that the sync separation is carried out over a wide frequency range without the need to VIDEO SIGNALS (RGB) H SYNC V SYNC 75Ω 75Ω VIDEO SIGNALS (HDTV) HDTV COMPONENT SYNCS 75Ω 620Ω 510pF CVBS COMPOSITE VIDEO SIGNAL (CVBS) 75Ω 11 15 VCCA2 18 VERTIN VERTOUT 16 22 VERTICAL TIMING EL4511 XTAL XTALN SDA 24 HORIZONTAL TIMING PDWN SCL 10kΩ 21 7 1 8 10kΩ HOUT GNDD2 4 SYNCIN 6 10 17 VCC 0.1µF GNDA2 GNDA2 100nF HIN 13 COMPUTER HDTV NTSC/PAL VCCD 14 9 VCCA1 0.1µF GNDD1 4.7µF VCC VCC + FIGURE 9. APPLICATIONS DRAWING 2 19 FN7009.7 July 21, 2005 EL4511 Serial Mode Operation Example: See “Description of Operation” for more details of (Serial Mode). Using a 32.768kHz crystal, the count period is 30.52µs. With a 20ms vertical rate, there will be approximately 656 cycles (290 Hex) in the "counts per field" registers 13 and 14. With a 16.666'ms vertical rate, the count of 546 (222 Hex) will be seen. Using the Reference Oscillator and Counter A counter is provided for measuring the vertical time interval; this counts the clocks at the XTAL pin 1 between vertical pulses. Computer & Control Interface In addition to the mode control pins, the chips default operating mode may be changed by way of a serial interface. This is of the three-wire type, Data, clock and /enable. After the /ENABLE line (pin 5) is taken low, the 16 bits of data on the SDA pin 7 will be clocked into the chip by the clock signal SCL pin 6. See Figure 10. This information is not necessary for the operation of the chip; only for information to the system micro-control. The count value is read from register 14 at bits 7:6 for the MSBs, the LSBs are available in register 13, bits 7:0. Register 14, bit 4 should be a high to indicate that the read operation did not collide with the up-date timing. The first bit of the data determines whether it will be a read or write operation. When set to a "0", a write operation will take place. The following 7 bits, select the register to be written to. Finally, the last 8 bits are the data to be written or read. For a read operation, the first bit is a "1". If the crystal oscillator is enabled through the serial interface (Register 9, bit 6, ENXTAL), the XTAL and XTALN pins will become the crystal input and crystal output pins for the 32.7kHz crystal. It is also possible to drive the XTAL pin with a logic level clock up to a maximum of 50kHz; this signal is only used to measure the vertical rate. In general, when registers entries are changed, the unchanged register bits must have the “Reset Values” entered as defined by Table 5. TO SERIAL I/F 8 Q0 Q6 Q7 REGISTER 13 LD Q7 REGISTER 14 LD VERTOUT TIMING 8 Q0 R Q8 Q7 Q9 10 BIT COUNTER CLK ‘1’ ‘0’ XTAL (PIN 1) MODE DECODE (SEE TABLE 3) 3 REGISTER 1, BITS 5:3 REGISTER 2, BIT 0 XTALN (PIN 24) REGISTER 9 BIT 6 FIGURE 10. BLOCK DIAGRAM OF REFERENCE OSCILLATOR 20 FN7009.7 July 21, 2005 EL4511 TABLE 3. MODE CONTROL TRUTH TABLE (see also Table 2 for hardware over-ride) MODE CTRL EnTri EnBi Level Level TABLE 4. ACQUISITION CONTROL SIGNALS EnHin Vin TriLevel Priority Hin Priority HinVin Only Reg 1 b5 b4 b3 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync detection, two-level sync detection and separate H/V (VGA) sync detection, respectively. Other signals used to prioritize tri-level syncs (TriLevPriority), separate H/V (Hin Priority), or to only allow signals from HIN/VERTIN (HinVinOnly). 21 SIGNAL NAME REGISTER BIT DESCRIPTION 8 3 En50Slice 1 = Sample and Hold front end is in use 8 1 Progressive 1 = Progressive scan detected 8 0 Tri-Level Detected 1 = Tri-Level syncs detected 9 5 ENLEVEL BLANKING 1 = VLEVEL is available when system is not locked 9 4 ENLEVEL 1 = Disable VLEVEL Output 9 2 ENALOS 1 = Analog loss of signal not used in lock indication. 14 5 SYNCLOCK Same information as SYNCLOCK pin 3 16 4 RateLocked Line rate is locked 16 3 ALOS Sync Amplitude is below minimum FN7009.7 July 21, 2005 EL4511 TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS REGISTER REGISTER NUMBER BIT 1 General Control Reg 1 TYPE RESET VALUE R/W 00h DESCRIPTION AND COMMENTS 7 General Reset 0 Software reset. Does not affect serial interface. 6 AlwaysEnOutputs 0 Overrides internal qualification of outputs. ModeCtrl 0 Sync acquisition. Selects input signal. See Table 3. 5:3 2 General Control Reg 2 R/W 10h 5 Select Fixed Slicing (no S/H) 0 Necessary for SECAM. May be useful for VCRs. 4 FILTER_ENABLED 1 Set Hi to include digital filter on horizontal input. 1 OE_MODE 0 Set Hi for Odd/Even changes on rising edge of vertical. 3 VBLANK Control Reg 1 7 6:0 4 R/W EnVBlank 90h 1 VSTPlusBP VBLANK & Polarity Ctrl 7:4 10h R/W Enables vertical blank interval detection algorithm. Number of lines after vertical sync time. 4Fh VFrontPorch 4h Number of lines before vertical sync time. 3 DefaultHPolarity 1 HIN polarity on reset if EnHpolarityDet = Lo. 2 DefaultVPolarity 1 VERTIN polarity on reset and if EnVpolarityDet = Lo. 1 EnHPolarityDet 1 Allows EL4511 to detect and set polarity on HIN. 0 EnVPolarityDet 1 Allows EL4511 to detect and set polarity on VERTIN. 6 Oscillator Control 2 7:6 7 8 22h 0 R LinesPerFrame <7:0> VBLANK O/P Reg 2 & Misc 7:4 R/W CMuxCtrl <1:0> VBLANK O/P Reg 1 7:0 Only valid if VBLANK circuit is enabled - R Multiplexes clock onto VBLANK or Odd/Even. See Table 1. Least significant byte of lines per frame count. 80h LinesPerFrame <11:8> - Most significant 4 bits of lines per frame count. 3 En50Slice - Indicates sample and hold front end is being used. 2 LPFValid - Indicates lines per frame has been updated. 1 progressive - Not valid for certain types of composite sync. 0 tri-level detect - Only valid if tri-level sync detected. 9 Analog Control Reg 1 R/W 6 ENXTAL 0 Set Hi to enable crystal oscillator. 5 ENLEVELBLANKING 0 Set Hi to enable VLEVEL when not locked. 4 ENLEVEL 0 Set Hi to disable VLEVEL output. 3 ENSYCLAMP 0 Set Hi to disable “soft” sync tip clamping in SYNCIN. 2 ENALOS 0 Set Hi to disable analog loss of signal feature. 1 ENRVIDEO 0 Set Hi to disable internal biasing on SYNCIN (passive resistor or soft clamp.) 0 PWRSAVE 0 Set Hi to put the analog circuit into powersave mode. - Crystal clock periods per field: L.S. Byte. (see description) 13 Absolute Timing Ref 1 7:0 14 SIGNAL NAME R CountsPerField <7:0> Absolute Timing Ref 2 & Misc 22 R FN7009.7 July 21, 2005 EL4511 TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS (Continued) REGISTER REGISTER NUMBER BIT SIGNAL NAME 7:6 TYPE RESET VALUE CountsPerField <9:8> - DESCRIPTION AND COMMENTS Crystal clock periods per field: Bits 9:8. (see description) 5 SyncLock 4 CPFValid - Counts per field valid. Set L if read occurs during an update. 3 SetBiLevel - Lo: Tri-level mode; Hi: Bi-level mode. 2 VinSyncDet - Indicates vertical sync on VERTIN successfully acquired. 1 VinPolarity - VERTIN polarity setting: Observe. 0 HPolarity - HIN polarity setting: Observe. 16 As sync lock pin. Oscillator Settings Observe 2 R 4 RateLocked - Indicates line rate successfully acquired. 3 ALOS - Analog loss of signal, measured via S/H. H indicates analog signal amplitude is below threshold. t(SDENB) IDLE WRITE TO REGISTER OF EL4511 (WRITE INDICATED WITH ADDRESS = 0XXXXXXX) SDENB t(SCL)HI t(SCL)LO (1/F)*SCL SCL 16 td(SDENB) SDA 0 LSB td(SCL) START t(SDA) SETUP “0”=WRITE t(SDA) HOLD REGISTER ADDRESS 7 BITS INPUT DATA 8 BITS t(SDENB) IDLE READ FROM REGISTER OF EL4511 (READ INDICATED WITH ADDRESS = 1XXXXXXX) SDENB t(SCL)HI t(SCL)LO (1/F)*SCL td(SDA)OUT td(SDENB)STOP SCL 16 SDA D7 1 t(SDA) SETUP td(SCL) START “I”=READ D0 t(SDA) HOLD REGISTER ADDRESS 7 BITS td(SDA) OFF OUTPUT DATA 8 BITS FIGURE 11. SERIAL INTERFACE TIMING DIAGRAM 23 FN7009.7 July 21, 2005 EL4511 Application 3 (application using a microcontroller interface) the vertical rate. To enable the crystal oscillator, register 9, bit 6 must be set to a high. In this example, the requirement is to provide the synchronizing information in a video digitizing interface. This example is very similar to the example in application 2. In this example the incoming sync signals may come from one of three sources. Computer, HDTV source or an NTSC/PAL device. Note that a Low Pass Filter is in the NTSC/PAL signal path to reduce noise, glitches and subcarrier. (In signals with bad Croma/Luma gain balance, the subcarrier can extend into the sync slicing level). As some of the signals in this application were non standard formats, the fixed slice mode is used by setting register 2, bit 5 to a high. Register 1, bit 6 is also set to a high. This forced the EL4511 to provide outputs even when the input signals are not recognized by the internal algorithms. As there is a Microcontroller connected in this example, a 32.768kHz XTAL is connected to pins 1 & 24; this will allow the system microcontroller to gather timing information for VIDEO SIGNALS (RGB) H SYNC V SYNC 75Ω 75Ω VIDEO SIGNALS (HDTV) HDTV COMPONENT SYNCS 75Ω 620Ω 510pF CVBS COMPOSITE VIDEO SIGNAL (CVBS) 75Ω 11 1 15 18 VCCA2 0.1µF GNDA2 VERTIN VERTOUT EL4511 10 4 HOUT PDWN BACKPORCH XTAL 22 21 2 HORIZONTAL TIMING VIDEO CLAMP PLL COAST SDA SCL 20 VERTICAL TIMING 7 6 GNDD2 SDENB 5 17 XTALN GNDA2 VBLANK 24 16 SYNCIN 8 32.768kHz CRYSTAL HIN 13 100nF VCCD 14 9 VCCA1 0.1µF GNDD1 4.7µF VCC VCC + TO MICROCONTROLLER FIGURE 12. APPLICATIONS DRAWING 3 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 FN7009.7 July 21, 2005