Product Information Package Thermal Characteristics Introduction This document provides test information about the standard packages offered by Allegro MicroSystems. The data given is intended as a general reference only and is based on certain simplifications such as constant chip size and standard bonding methods. To use this document, in the Allegro Package Code column, locate the package designator for the device. To locate package variants, use the jedec Package Outline column to locate the corresponding jedec designator, or use the Quantity and Type of Terminals column to locate the variant by the configuration of terminals. Three columns of results are presented: • RθJA High K. This test is performed using a high thermal conductivity, multilayer printed circuit board that closely approximates those specified in the jedec standards JESD51-7 (for surface-mount devices except area array devices), JESD51-9 (for area array devices), or JESD51-10 (for through-hole devices). For devices with exposed thermal pads, thermal vias are included per JESD51-5. These standards are available for download on the jedec Web site, www.jedec.org. • RθJA Usual. This test is performed using a com-mon printed circuit board. Where only one value is shown in this column, a singlelayer printed circuit board with minimal PUB296102 140520 exposed copper area is tested. Where two values are shown in this column, it indicates that the printed circuit board has multiple test locations, each having a differ-ent amount of exposed copper foil (2 oz. thick-ness). Both one- and two-layer boards are tested. The ground leads (power tabs) or exposed pad of the devices are connected to these areas of copper foil. The two results shown indicate the highest and the lowest test results Note that the paired results are text hyperlinks to other Web pages. Click the text to open the linked page, which provides information on the printed circuit board layout, as well as intermediate test results. • RθJP and RθJT . This column provides results on other thermal dissipation paths: ▪▪ RθJP [p] Through the exposed thermal pad (for related topic, see Application Note 26020, Procedure for Measuring Pad-toAmbient Thermal Resistance (RθPA) for Exposed Pad Packages). ▪▪ RθJT [t] Certain devices have some leads joined together (fused) internally, and in some in-stances externally, to provide more efficient heat dissipation (referred to as a power tab or batwing configuration). Package Designators Allegro Package Code A B Package Type (Common Package Designator) Plastic Dual In-Line (DlP, PDIP, DIL, or PDIL) Semi-Tab Plastic Dual In-Line (DlP, PDIP, DIL, or PDIL) Quantity JEDEC Package and Type of Outline Terminals RqJA High K (ºC/W) Usual (ºC/W) RqJP RqJT (ºC/W) MS-001 AA 14-Pin 40 73 – MS-001 BB 16-Pin 38 68 – MS-001 AC 18-Pin 36 65 – MS-001 AD 20-Pin 32 60 – MS-010 AA 22-Pin 30 56 – MS-001 AF 24-Pin 26 50 – MS-011 AB 28-Pin – 45 – MS-001 BB 16-Pin 28 41-63 6 [t] MS-001 AF 24-Pin 26 36-54 6 [t] – – – – – MO-220 WGGE 4 x 4 mm 26-Contact 35 – 2 [p] MS-018 AC 44-J Lead 22 30-50 6 [t] CG Wafer-level Chip Scale Package (WLCSP): refer to device datasheet EC Plastic Leadless Package with Exposed Thermal Pad (MLPQ/QFN) ED Semi-Tab (four) Plastic Leaded Chip Carrier (PLCC/PQCC) EE Plastic Leadless Package with Exposed Thermal Pad (MLPD/DFN/ SON) MO-229 UCCD 2 x 2 mm 8-Contact 49 92-219 – EH Plastic Leadless Package with Exposed Thermal Pad (MLPD/DFN/ SON) MO-229 WCED 3 x 2 mm 6-Contact 50 70-221 2 [p] EJ Plastic Leadless Package with Exposed Thermal Pad (MLPD/DFN/ SON) MO-229 WEED 3 x 3 mm 10-Contact 45 65-190 2 [p] EK Plastic Leadless Package with Exposed Thermal Pad (MLPD/DFN/ SON) MO-229 WEEA 3 x 3 mm 5-Contact 50 72-182 2 [p] EL Plastic Leadless Package with Exposed Thermal Pad (MLPD/DFN/ SON) MO-229 WCCD 2 x 2 mm 6-Contact 56 95-250 2 [p] MO-220 WEED 3 x 3 mm 16-Contact 47 96-133 – MO-220 WGGD 4 x 4 mm 20-Contact 37 75-136 2 [p] 5 x 5 mm 28-Contact 32 64-115 2 [p] 5 x 5 mm 32-Contact 30 – – ES ET EU EV Plastic Leadless Package with Exposed Thermal Pad (MLPQ/QFN) Plastic Leadless Package with Exposed Thermal Pad (MLPQ/ QFN) MO-220 VHHD Plastic Leadless Package with Exposed Thermal Pad (MLPQ/QFN) MO-220 WGGC 4 x 4 mm 16-Contact 36 – 2 [p] MO-220 VJJD 6 x 6 mm 36-Contact 27 64-103 2 [p] MO-220 VJJD 6 x 6 mm 40-Contact 27 – 2 [p] MO-220 VKKD 7 x 7 mm 48-Contact 24 – 2 [p] Plastic Leadless Package with Exposed Thermal Pad (MLPQ/ QFN) EW Plastic Leadless Package with Exposed Thermal Pad (MLPD/DFN/ SON) MO-229 X2BCD 1.5 x 2 mm 6-Contact 64 125-235 – JP Plastic Low-Profile Quad Flatpack with Exposed Thermal Pad (eLQFP) MS-026 BBC-HD 48-Gull Wing 23 44-86 2 [p] JS Plastic Thin-Profile Quad Flatpack with Exposed Thermal Pad (TQFP) MS-026 ADD-HD 80-Gull Wing 21 – 2 [p] Continued on next page... PUB296102 140520 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Continued from previous page... Allegro Package Code Package Type (Common Package Designator) Quantity JEDEC Package and Type of Outline Terminals RqJA High K (ºC/W) Usual (ºC/W) RqJP RqJT (ºC/W) K Plastic Single In-Line (SIP) – 4-Lead – 177 – KA Plastic Single In-Line (SIP) – 5-Lead – 164 – KB Plastic Single In-Line (SIP) – 3-Lead – 177 – KC Plastic Single In-Line (SIP) Plastic Single In-Line (SIP) – 3-Lead – 177 – KN – Plastic Single In-Line (SIP) 4-Lead 4-Lead 170 KT – – – – 174 – MS-012 AA 8-Gull Wing 80 140 – – L LB Plastic Small-Outline IC (SOIC) Semi-Tab Plastic Small-Outline IC (SOIC) MS-012 AB 14-Gull Wing 65 120 MS-012 AC 14-Gull Wing 64 118 – MS-013 AA 16-Gull Wing 38 48-90 6 [t] MS-013 AC 20-Gull Wing 38 48-87 6 [t] MS-013 AD 24-Gull Wing 35 45-77 6 [t] LD Plastic Thin Shrink Small-Outline IC (TSSOP) MO-153 BD-1 38-Gull Wing 51 127 – LE Plastic Thin Shrink Small-Outline IC (TSSOP) MO-153 AA 8-Gull Wing 145 – – LG Plastic Thin Shrink Small-Outline IC (TSSOP) with 6 internallyfused leads MO-153 BD-1 38-Gull Wing 47 121 – LH Plastic Small-Outline Transistor (SOT23W) – 3-Lead 154 – – – 5-Lead 124 – – LJ Plastic Small-Outline IC (SOIC) with Exposed Thermal Pad LP Plastic Thin Shrink Small-Outline IC with Exposed Thermal Pad (HTSSOP) LQ Plastic Small-Outline IC (SOIC) LT Plastic Small-Outline Transistor (SOT89) LW Wide-Body Plastic Small-Outline IC (SOIC) MS-012 BA 8-Gull Wing 35 62-147 2 [p] MO-153 ABT 16-Gull Wing 34 43-129 2 [p] MO-153 ADT 24-Gull Wing 28 32-100 2 [p] MO-153 AET 28-Gull Wing 28 32-100 2 [p] – 36-Gull Wing 44 85 – TO-243 AA 3-Lead – 78-180 – MS-013 AA 16-Gull Wing 48 94 – MS-013 AB 18-Gull Wing 48 94 – MS-013 AC 20-Gull Wing 48 90 – MS-013 AD 24-Gull Wing 44 85 – MS-013 AE 28-Gull Wing 44 80 – LY Mini Small Outline (MSOP) with Exposed Thermal Pad MO-187BA-T 10-Gull Wing 44 48-177 – SA Plastic (9 mm Ø x 9 mm long) SIP Module – 4-Lead – 147 – SB Plastic (8.9 mm Ø x 7 mm long) SIP Module – 4-Lead – 150 – SE Plastic (10 mm Ø x 7 mm long) SIP Module – 4-Lead – 77-101 – SG Plastic (8 mm Ø x 5.5 mm long) SIP Module – 4-Lead – 84-126 – SH Plastic (8 mm Ø x 5.5 mm long) SIP Module – 4-Lead – 54-126 – SJ Plastic (8 mm Ø x 5.5 mm long) SIP Module – 4-Lead – 54-126 – U Plastic Mini Single In-Line (SIP) – 3-Lead – 184 – UA Plastic Ultra-Mini Single In-Line (SIP) – 3-Lead – 165 – UB Plastic Mini Single In-Line (SIP) – 2-Lead – 213 – PUB296102 140520 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Copyright ©2001–2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com PUB296102 140520 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4