HT16C21 RAM Mapping 20*4 / 16*8 LCD Driver Controller Feature Applications ●● Operating voltage: 2.4 ~ 5.5V ●● Internal 32kHz RC oscillator ●● Electronic meter ●● Water meter ●● Bias: 1/3 or 1/4; Duty: 1/4 or 1/8 ●● Internal LCD bias generation with voltagefollower buffers ●● Gas meter ●● Heat energy meter ●● Household appliance ●● Games ●● I2C interface ●● Two selectable LCD frame frequencies: 80Hz or 160Hz ●● Telephone ●● Consumer electronics ●● Up to 16 x 8 bits RAM for display data storage ●● Display patterns: ––20 x 4 patterns: 20 segments and 4 commons ––16 x 8 patterns: 16 segments and 8 commons General Description The HT16C21 device is a memory mapping and multi-function LCD controller/driver. The display segments of the device are 80 patterns (20 segments and 4 commons) or 128 patterns (16 segments and 8 commons). The software configuration feature of the HT16C21 device makes it suitable for multiple LCD applications including LCD modules and display subsystems. The HT16C21 device communicates with most microprocessors/microcontrollers via a two-line bidirectional I2C interface. ●● Versatile blinking modes ●● R/W address auto increment ●● Internal 16-step voltage adjustment to adjust LCD operating voltage ●● Low power consumption ●● Provides VLCD pin to adjust LCD operating voltage ●● Manufactured in silicon gate CMOS process ●● Package Type: 20/24/28 SOP, 16 NSOP and Chip. Rev. 1.00 1 November 22, 2011 HT16C21 Block Diagram Power_on reset VSS COM0 SDA SCL Internal RC Oscillator Timing generator I2C Controller Column /Segment driver output Display RAM 16*8bits 8 COM3 COM4/SEG0 COM7/SEG3 VDD － OP4 Internal voltage adjustment VLCD SEG4 ＋ R － OP3 ＋ R － OP2 ＋ R LCD Voltage Selector Segment driver output － OP1 ＋ SEG19 R LCD bias generator Rev. 1.00 2 November 22, 2011 HT16C21 Pin Assignment VDD 1 28 SEG19/VLCD SDA 2 27 SEG18 SCL 3 26 SEG17 25 SEG16 24 SEG19/VLCD 23 SEG18 VSS 4 22 SEG15 COM0 5 24 SEG15 21 SEG14 COM1 6 23 SEG14 20 SEG13 COM2 7 22 SEG13 19 SEG12 COM3 8 21 SEG12 18 SEG11 COM4/SEG0 9 20 SEG11 8 17 SEG10 COM5/SEG1 10 19 SEG10 COM4/SEG0 9 16 SEG7 COM6/SEG2 11 18 SEG9 COM5/SEG1 10 15 SEG6 COM7/SEG3 12 17 SEG8 COM6/SEG2 11 14 SEG5 SEG4 13 16 SEG7 COM7/SEG3 12 13 SEG4 SEG5 14 15 SEG6 VDD 1 SDA 2 SCL 3 VSS 4 COM0 5 COM1 6 COM2 7 COM3 HT16C21 24 SOP-A HT16C21 28 SOP-A 1 20 SEG19/VLCD SDA 2 19 SEG18 VDD 1 16 SEG19/VLCD SCL 3 18 SEG13 SDA 2 15 SEG14 VSS 4 17 SEG12 SCL 3 14 SEG13 COM0 5 16 SEG11 VSS 4 13 SEG12 COM1 6 15 SEG10 COM0 5 12 COM7/SEG3 COM2 7 14 SEG5 COM1 6 11 COM6/SEG2 COM3 8 13 SEG4 COM2 7 10 COM5/SEG1 COM4/SEG0 9 12 COM7/SEG3 COM3 8 9 COM4/SEG0 COM5/SEG1 10 11 COM6/SEG2 HT16C21 16 NSOP-A Rev. 1.00 VDD HT16C21 20 SOP-A 3 November 22, 2011 HT16C21 SEG15 SEG16 SEG17 SEG18 SEG19 VLCD VCCA2 VDD SDA SCL VSS Pad assignment for COB 1 31 30 29 28 27 26 25 24 23 22 N.C. 2 COM0 3 COM1 4 COM2 5 COM3 6 21 SEG14 20 SEG13 19 SEG12 18 SEG11 (0, 0) 7 8 9 10 11 12 13 14 15 16 17 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 COM7/SEG3 COM6/SEG2 COM5/SEG1 COM4/SEG0 Chip size: 1200 x 1846μm2 Note: 1. The IC substrate should be connected to VSS in the PCB layout artwork. 2. VDD (Pad29) and VCCA2 (Pad28) must be bonded together. 3. VLCD (Pad27) and SEG19 (Pad26) must be bonded together. Pad Coordinates for COB No Name X Unit: μm Y No Name X Y 1 VSS -423.6 819.9 17 SEG10 426.1 -825 2 N.C. -251.74 351.435 18 SEG11 502 279.599 3 COM0 -502 134.752 19 SEG12 502 364.599 4 COM1 -502 49.752 20 SEG13 502 449.599 5 COM2 -502 -35.248 21 SEG14 502 534.599 6 COM3 -502 -120.248 22 SEG15 426.4 819.9 7 COM4/SEG0 -426.4 -825 23 SEG16 341.4 819.9 8 COM5/SEG1 -341.4 -825 24 SEG17 256.4 819.9 9 COM6/SEG2 -256.4 -825 25 SEG18 171.4 819.9 10 COM7/SEG3 -171.4 -825 26 SEG19 86.4 819.9 11 SEG4 -83.9 -825 27 VLCD 1.4 819.9 12 SEG5 1.1 -825 28 VCCA2 -83.6 819.9 13 SEG6 86.1 -825 29 VDD -168.6 819.9 14 SEG7 171.1 -825 30 SDA -253.6 819.9 31 SCL -338.6 819.9 15 SEG8 256.1 -825 16 SEG9 341.1 -825 Rev. 1.00 4 November 22, 2011 HT16C21 Pin Description Pin Name Type SDA I/O SCL I Description Serial data input/output for I2C interface Serial clock input for I2C interface VDD — Positive power supply. VSS — Negative power supply, ground. VLCD — ●●One external resistor is connected between the VLCD pin and the VDD pin to determine the bias voltage for the package with a VLCD pin. Internal voltage adjustment function is disabled. ●●Internal voltage adjustment function can be used to adjust the V LCD voltage. If the VLCD pin is used as voltage detection pin, an external power supply should not be applied to the VLCD pin. ●●An external MCU can detect the voltage of the VLCD pin and program the internal voltage adjustment for the packages with a VLCD pin. COM0~COM3 O LCD common outputs. COM4/SEG0~COM7/SEG3 O LCD common/segment multiplexed driver outputs SEG4~SEG19 O LCD segment outputs. Approximate Internal Connections COM0~COM7; SEG0~SEG19 SCL, SDA (for schmit Trigger type) VDD Vselect-on Vselect-off VSS Absolute Maximum Ratings Supply voltage .......................................................................................................................VSS−0.3V to VSS+6.5V Input voltage .........................................................................................................................VSS−0.3V to VDD+0.3V Storage temperature ........................................................................................................................-55°C to +150°C Operating temperature ......................................................................................................................-40°C to +85°C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 5 November 22, 2011 HT16C21 D.C. Characteristics Symbol Parameter VSS = 0V; VDD = 2.4 to 5.5V; Ta =-40~85°C Test Condition VDD Condition Min. Typ. Max. Unit VDD Operating Voltage — — 2.4 — 5.5 V VLCD Operating Voltage — — — — VDD V No load, VLCD=VDD, 1/3bias, fLCD=80Hz, LCD display on, internal system oscillator on, DA0~DA3 are set to "0000" — 18 27 μA — 25 40 μA No load, VLCD=VDD, 1/3bias fLCD=80Hz, LCD display off, internal system oscillator on, DA0~DA3 are set to "0000" — 2 5 μA — 4 10 μA — — 1 μA 5V No load, VLCD=VDD, LCD display off, internal system oscillator off — — 2 μA 3V IDD Operating Current 5V 3V IDD1 Operating Current 5V 3V ISTB Standby Current VIH Input High Voltage — SDA ,SCL 0.7VDD — VDD V VIL Input Low Voltage — SDA, SCL 0 — 0.3VDD V IIL Input Leakage Current — VIN = VSS or VDD -1 — 1 μA IOL Low Level Output Current 3V 3 — — mA 5V VOL=0.4V SDA 6 — — mA IOL1 LCD COM Sink Current 3V VLCD=3V, VOL=0.3V 250 400 — μA 5V VLCD=5V, VOL=0.5V 500 800 — μA IOH1 LCD COM Source Current 3V VLCD=3V, VOH=2.7V -140 -230 — μA 5V VLCD=5V, VOH=4.5V -300 -500 — μA IOL2 LCD SEG Sink Current 3V VLCD=3V, VOL=0.3V 250 400 — μA 5V VLCD=5V, VOL=0.5V 500 800 — μA IOH2 LCD SEG Source Current 3V VLCD=3V, VOH=2.7V -140 -230 — μA 5V VLCD=5V, VOH=4.5V -300 -500 — μA Rev. 1.00 6 November 22, 2011 HT16C21 A.C. Characteristics Symbol Parameter VSS = 0V; VDD = 2.4 to 5.5V; Ta =-40~85°C Test Condition Condition VDD Min. Typ. Max. Unit fLCD1 LCD Frame Frequency 4V 1/4duty, Ta =25°C 72 80 88 Hz fLCD2 LCD Frame Frequency 4V 1/4duty, Ta =25°C 144 160 176 Hz fLCD3 LCD Frame Frequency 4V 1/4duty, Ta=- 40 to +85°C 52 80 124 Hz fLCD4 LCD Frame Frequency 4V 1/4duty, Ta=-40 to +85°C 104 160 248 Hz tOFF VDD Off Times — VDD drop down to 0V 20 — — ms tSR VDD Slew Rate — 0.05 — — V/ms — Note: 1. If the conditions of Power on Reset timing are not satisfied during the power ON/OFF sequence, the internal Power on Reset (POR) circuit will not operate normally. 2. If the VDD voltage drops below the minimum voltage of operating voltage spec. during operating, the Power on Reset timing conditions must also be satisfied. That is, the VDD voltage must drop to 0V and remain at 0V for 20ms (min.) before rising to the normal operating voltage. A.C. Characteristics – I2C Interface Symbol fSCL Parameter Clock Frequency Condition VDD=2.4V to 5.5V VDD=3.0V to 5.5V — Unit Min. Max. Min. Max. — 100 — 400 kHz 4.7 — 1.3 — μs 4 — 0.6 — μs tBUF Bus Free Time Time in which the bus must be free before a new transmission can start tHD: STA Start Condition Hold Time After this period, the first clock pulse is generated tLOW SCL Low Time — 4.7 — 1.3 — μs tHIGH SCL High Time — 4 — 0.6 — μs tSU: STA Start Condition Setup Time 4.7 — 0.6 — μs tHD: DAT Data Hold Time — 0 — 0 — ns tSU: DAT Data Setup Time — 250 — 100 — ns tR SDA and SCL Rise Time Note — 1 — 0.3 μs Only relevant for repeated START condition tF SDA and SCL Fall Time Note — 0.3 — 0.3 μs tSU: STO Stop Condition Set-up Time — 4 — 0.6 — μs tAA Output Valid from Clock — — 3.5 — 0.9 μs tSP Input Filter Time Constant (SDA and SCL Pins) — 100 — 50 ns Noise suppression time Note: These parameters are periodically sampled but not 100% tested. Rev. 1.00 7 November 22, 2011 HT16C21 Timing Diagrams I2C Timing SDA tBUF tSU:DAT tf tLOW tHD:STA tr tSP SCL tHD:STA S tHD:DAT tHIGH tSU:STA tAA tSU:STO Sr P S SDA OUT Reset Timing Rev. 1.00 8 November 22, 2011 HT16C21 Functional Description Power-On Reset When the power is applied, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: ●● All common/segment outputs are set to VLCD. ●● The drive mode 1/4 duty output and 1/3 bias is selected. ●● The System Oscillator and the LCD bias generator are off state. ●● LCD Display is off state. ●● Internal voltage adjustment function is enabled. ●● The Segment / VLCD shared pin is set as the Segment pin. ●● Detection switch for the VLCD pin is disabled. ●● Frame Frequency is set to 80Hz. ●● Blinking function is switched off. Data transfers on the I2C interface should be avoided for 1 ms following power-on to allow completion of the reset action. Display Memory – RAM Structure The display RAM is static 16 x 8-bits RAM which stores the LCD data. Logic “1” in the RAM bit-map indicates the “on” state of the corresponding LCD segment; similarly, logic 0 indicates the ‘off’ state. The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the segments operated with respect to COM0. In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with COM1, COM2 and COM3 respectively. The following is a mapping from the RAM data to the LCD pattern: Output COM3 COM2 COM1 COM0 Output COM3 COM2 COM1 COM0 Address SEG1 SEG0 00H SEG3 SEG2 01H SEG5 SEG4 02H SEG7 SEG6 03H SEG9 SEG8 04H SEG11 SEG10 05H SEG13 SEG12 06H SEG15 SEG14 07H SEG17 SEG16 08H SEG19 SEG18 09H D7 D6 D5 D4 D3 D2 D1 D0 Data RAM mapping of 20x4 display mode Rev. 1.00 9 November 22, 2011 HT16C21 Output COM7/ SEG3 COM6/ SEG2 COM5/ SEG1 COM4/ SEG0 COM3 COM2 COM1 COM0 address SEG4 00H SEG5 01H SEG6 02H SEG7 03H SEG8 04H SEG9 05H SEG10 06H SEG11 07H SEG12 08H SEG13 09H SEG14 0AH SEG15 0BH SEG16 0CH SEG17 0DH SEG18 0EH SEG19 0FH D7 D6 D5 D4 D3 D2 D1 D0 Data RAM mapping of 16x8 display mode MSB LCD LED D7 LSB D6 D5 D4 D3 D2 D1 D0 LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 Display data transfer format for I2C interface System Oscillator The timing for the internal logic and the LCD drive signals are generated by an internal oscillator. The System Clock frequency (fSYS) determines the LCD frame frequency. During initial system power on the System Oscillator will be in the stop state. LCD Bias Generator The full-scale LCD voltage (V OP) is obtained from (V LCD – V SS). The LCD voltage may be temperature compensated externally through the Voltage supply to the VLCD pin. Fractional LCD biasing voltages, known as 1/3 or 1/4 bias voltage, are obtained from an internal voltage divider of four series resistors connected between VLCD and VSS. The centre resistor can be switched out of circuits to provide a 1/3bias voltage level configuration. Rev. 1.00 10 November 22, 2011 HT16C21 LCD Drive Mode Waveforms ●● When the LCD drive mode is selected as 1/4 duty and 1/3 bias, the waveform and LCD display is shown as follows: tLCD VLCD VLCD COM0 COM0 State1 State1 (on) (on) VLCD- Vop/3 VLCD- Vop/3 LCD segment LCD segment VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD COM1 COM1 State2 State2 (off) (off) VLCD- Vop/3 VLCD- Vop/3 VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD COM2 COM2 VLCD- Vop/3 VLCD- Vop/3 VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD COM3 COM3 VLCD- Vop/3 VLCD- Vop/3 VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD VLCD- Vop/3 VLCD- Vop/3 SEG n SEG n VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD VLCD- Vop/3 VLCD- Vop/3 SEG n+1 SEG n+1 VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD VLCD- Vop/3 VLCD- Vop/3 SEG n+2 SEG n+2 VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS VLCD VLCD VLCD- Vop/3 VLCD- Vop/3 SEG n+3 SEG n+3VLCD- 2Vop/3 VLCD- 2Vop/3 VSS VSS Waveforms for 1/4 duty drive mode with 1/3 bias (VOP = VLCD-VSS) Note: tLCD = 1/fLCD Rev. 1.00 11 November 22, 2011 HT16C21 ●● When the LCD drive mode is selected as 1/8 duty and 1/4bias, the waveform and LCD display is shown as follows: tLCD LCD segment LCD segment VLCD VLCD State1 State1 (on) (on) VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM0 VLCD- 2Vop/4 COM0 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD State2 State2 (off) (off) VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM1 VLCD- 2Vop/4 COM1 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM2 VLCD- 2Vop/4 COM2 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM3 VLCD- 2Vop/4 COM3 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM4 VLCD- 2Vop/4 COM4 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM5 VLCD- 2Vop/4 COM5 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM6 VLCD- 2Vop/4 COM6 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 VLCD- 2Vop/4 COM7 VLCD- 2Vop/4 COM7 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 SEG n SEG n VLCD- 2Vop/4 VLCD- 2Vop/4 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 SEG n+1 VLCD- 2Vop/4 SEG n+1 VLCD- 2Vop/4 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 SEG n+2 VLCD- 2Vop/4 SEG n+2 VLCD- 2Vop/4 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS VLCD VLCD VLCD- Vop/4 VLCD- Vop/4 SEG n+3 VLCD- 2Vop/4 SEG n+3 VLCD- 2Vop/4 VLCD- 3Vop/4 VLCD- 3Vop/4 VSS VSS Waveforms for 1/8 duty drive mode with1/4 bias (VOP = VLCD−VSS) Note: tLCD = 1/fLCD Rev. 1.00 12 November 22, 2011 HT16C21 Segment Driver Outputs The LCD drive section includes 20 segment outputs SEG0 ~ SEG19 or 16 segment outputs SEG4 ~ SEG19 which should be connected directly to the LCD panel. The segment output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. The unused segment outputs should be left open-circuit when less than 20 or 16 segment outputs are required. Column Driver Outputs The LCD drive section includes 4 column outputs COM0~COM3 or 8 column outputs COM0~COM7 which should be connected directly to the LCD panel. The column output signals are generated in accordance with the selected LCD drive mode. The unused column outputs should be left open-circuit if less than 4 or 8 column outputs are required. Address Pointer The addressing mechanism for the display RAM is implemented using the address pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the address pointer by the Address pointer command. Blinker Function The device contains versatile blinking capabilities. The whole display can be blinked at frequencies selected by the Blink command. The blinking frequency is a subdivided ratio of the system frequency. The ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table: Blinking Mode Operating Mode Ratio Blinking Frequency (Hz) 0 0 Blink off 1 fSYS / 16384Hz 2 2 fSYS / 32768Hz 1 3 fSYS / 65536Hz 0.5 Frame Frequency The HT16C21 device provides two frame frequencies selected with Mode set command known as 80Hz and 160Hz respectively. Rev. 1.00 13 November 22, 2011 HT16C21 Internal VLCD Voltage Adjustment ●● The internal VLCD adjustment contains four resistors in series and a 4-bit programmable analog switch which can provide sixteen voltage adjustment options using the VLCD voltage adjustment command. ●● The internal VLCD adjustment structure is shown in the diagram: VDD IVA VLCD pin R R R R LCD Bias generator ●● The relationship between the programmable 4-bit analog switch and the VLCD output voltage is shown in the table: DA3~DA0 00H 01H Rev. 1.00 Bias 1/3 1/4 Note Default value 1.000*VDD 1.000*VDD 0.944*VDD 0.957*VDD 0.918*VDD 02H 0.894*VDD 03H 0.849*VDD 0.882*VDD 04H 0.808*VDD 0.849*VDD 05H 0.771*VDD 0.818*VDD 0.789*VDD 06H 0.738*VDD 07H 0.707*VDD 0.763*VDD 08H 0.678*VDD 0.738*VDD 0.714*VDD 09H 0.652*VDD 0AH 0.628*VDD 0.692*VDD 0BH 0.605*VDD 0.672*VDD 0CH 0.584*VDD 0.652*VDD 0DH 0.565*VDD 0.634*VDD 0EH 0.547*VDD 0.616*VDD 0FH 0.529*VDD 0.600*VDD 14 November 22, 2011 HT16C21 I2C Serial Interface I2C Operation The device supports I2C serial interface. The I2C interface is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7KΩ. When the I2C interface is free, both lines are high. Devices connected to the I2C interface must have open-drain or open-collector outputs to implement a wired-or function. Data transfer is initiated only when the I2C interface is not busy. Data Validity The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the data line can only change when the clock signal on the SCL line is Low as shown in the diagram. SDA SCL Data line stable; Data valid Change of data allowed START and STOP Conditions ●● A high to low transition on the SDA line while SCL is high defines a START condition. ●● A low to high transition on the SDA line while SCL is high defines a STOP condition. ●● START and STOP conditions are always generated by the master. The I2C interface is considered to be busy after the START condition. The I2C interface is considered to be free again a certain time after the STOP condition. ●● The I2C interface stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the START(S) and repeated START (Sr) conditions are functionally identical. SDA SDA SCL SCL S P START condition STOP condition Byte Format Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit, MSB, first. P SDA Sr SCL Rev. 1.00 S or Sr 1 2 7 8 9 ACK 15 1 2 3-8 9 ACK P or Sr November 22, 2011 HT16C21 Acknowledge ●● Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed on the I2C interface by the receiver. The master generates an extra acknowledge related clock pulse. ●● A slave receiver which is addressed must generate an acknowledge, ACK, after the reception of each byte. ●● The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. ●● A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition. Data Output by Transmitter not acknowledge Data Outptu by Receiver acknowledge SCL From Master 1 S 7 2 8 START condition 9 clock pulse for acknowledgement Slave Addressing ●● The slave address byte is the first byte received following the START condition form the master device. The first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation. ●● The HT16C21 address bits are “0111000”. When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line. Slave Address MSB 0 Rev. 1.00 LSB 1 1 1 0 16 0 0 R/W November 22, 2011 HT16C21 Write Operation Byte Writes Operation ●● Command Byte A Command Byte write operation requires a START condition, a slave address with an R/W bit, a command byte, a command setting byte and a STOP condition for a command byte write operation. Command byte Command setting BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Slave Address S 0 1 1 1 0 0 0 0 Write ACK ACK 1st P ACK 2nd Command Byte Write Operation ●● Display RAM Single Data Byte A display RAM data byte write operation requires a START condition, a slave address with an R/W bit, a command byte, a valid Register Address byte, a Data byte and a STOP condition. Command byte Register Address byte Data byte BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 D7 D6 D5 D4 D3 D2 D1 D0 Slave Address S 0 1 1 1 0 0 0 0 Write ACK ACK 1st ACK 2nd P ACK Display RAM Single Data Byte Write Operation Display RAM Page Write Operation After a START condition the slave address with the R/W bit is placed on the I2C interface followed with a command byte and the specified display RAM Register Address of which the contents are written to the internal address pointer. The data to be written to the memory will be transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse. After the internal address point reaches the maximum memory address, which is 09H for 1/4 duty drive mode or 0FH for 1/8 duty drive mode, the address pointer will be reset to 00H. Command byte Register Address byte BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1st 2nd Slave Address S 0 1 1 1 0 0 0 0 Write Data byte D7 D6 D5 D4 D3 ACK ACK ACK Data byte D2 D1 D0 D7 1st data D6 D5 D4 D3 Data byte D2 D1 D0 D7 2nd data D5 D4 D3 Nth data ACK ACK D6 ACK D2 D1 P D0 ACK N Bytes Display RAM Data Write Operation Rev. 1.00 17 November 22, 2011 HT16C21 Display RAM Read Operation ●● In this mode, the master reads the HT16C21 data after setting the slave address. Following the R/W bit (=’0”) is an acknowledge bit, a command byte and the register address byte which is written to the internal address pointer. After the start address of the Read Operation has been configured, another START condition and the slave address transferred on the I2C interface followed by the R/W bit (=’1”). Then the MSB of the data which was addressed is transmitted first on the I2C interface. The address pointer is only incremented by 1 after the reception of an acknowledge clock. That means that if the device is configured to transmit the data at the address of AN+1, the master will read and acknowledge the transferred new data byte and the address pointer is incremented to AN+2. After the internal address pointer reaches the maximum memory address, which is 09H for 1/4 duty drive mode or 0FH for 1/8 duty drive mode, the address pointer will be reset to 00H. ●● This cycle of reading consecutive addresses will continue until the master sends a STOP condition. Command byte Register Address byte BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Slave Address S 0 1 1 1 0 0 0 0 Write Device Address S 0 1 1 1 0 2nd 0 1 D7 D6 D5 D4 D3 Data byte D2 D1 D7 D0 D6 D5 D4 D3 Data byte D2 D1 D0 D7 2nd data 1st data ACK ACK ACK ACK Data byte 0 Read Rev. 1.00 1st P ACK 18 D6 D5 D4 D3 Nth data ACK D2 D1 D0 P NACK ACK November 22, 2011 HT16C21 Command Summary Display Data Input Command This command sends data from MCU to memory MAP of the HT16C21 device. Function Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Display data input/ output command 1st 1 0 0 0 0 0 0 0 Address pointer 2nd X X X X A3 A2 A1 A0 Note R/W Def W Display data start address of memory map W 00H R/W Def Note: ●●Power on status: The address is set to 00H. ●●If the programmed command is not defined, the function will not be affected. ●●For 1/4 duty drive mode after reaching the memory location 09H, the pointer will reset to 00H. ●●For 1/8 duty drive mode after reaching the memory location 0FH, the pointer will reset to 00H. Drive Mode Command Function Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Driver mode setting command 1st 1 0 0 0 0 0 1 0 W Duty and bias setting 2nd X X X X X X Duty Bias W 00H R/W Def Note Note: Bit Duty Bias 0 1/4duty 1/3bias 1 1/4duty 1/4bias 1 0 1/8duty 1/3bias 1 1 1/8duty 1/4bias Duty Bias 0 0 ●●Power on status: The drive mode 1/4 duty output and 1/3 bias is selected. ●●If the programmed command is not defined, the function will not be affected. System Mode Command Function Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 System mode setting command 1st 1 0 0 0 0 1 0 0 W System oscillator and display on/off setting 2nd X X X X X X S E W Note 00H Note: Bit S E Internal System Oscillator LCD Display off 0 X off 1 0 on off 1 1 on on ●●Power on status: Display off and disable the internal system oscillator. ●●If the programmed command is not defined, the function will not be affected. Rev. 1.00 19 November 22, 2011 HT16C21 Frame Frequency Command This command selects the frame frequency. Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Frame frequency command 1st 1 0 0 0 0 1 1 0 W Frame frequency setting 2nd X X X X X X X F W 00H R/W Def Function Note R/W Def Note: Bit Frame Frequency F 0 80Hz 1 160Hz ●●Power on status: Frame frequency is set to 80Hz. ●●If the programmed command is not defined, the function will not be affected. Blinking Frequency Command This command defines the blinking frequency of the display modes. Function Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Blinking Frequency command 1st 1 0 0 0 1 0 0 0 W Blinking Frequency setting 2nd X X X X X X BK1 BK0 W Note 00H Note: Bit Blinking Frequency BK1 BK0 0 0 Blinking off 0 1 2Hz 1 0 1Hz 1 1 0.5Hz ●●Power on status: Blinking function is switched off. ●●If the programmed command is not defined, the function will not be affected. Rev. 1.00 20 November 22, 2011 HT16C21 Internal Voltage Adjustment (IVA) Setting Command The internal voltage (VLCD) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting the LCD operating voltage adjustment command. Function Byte Internal Voltage Adjustment (IVA) Setting Internal Voltage Adjust control 1st (MSB) Bit6 Bit7 1 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 0 0 1 0 1 0 0 2nd X X DE VE Segment / VLCD Shared Pin Select VE DA3 DA2 DA1 DA0 Note R/W Def W ●●The Segment/VLCD shared pin can be programmed via the “DE” bit. ●●The “VE” bit is used to enable or disable the internal voltage adjustment for bias voltage. ●●The DA3~DA0 bits can be used to adjust the VLCD output voltage. W 30H Note: Bit DE 0 0 0 1 VLCD pin VLCD pin Internal Voltage Adjustment Note off ●●The Segment/VLCD pin is set as the VLCD pin. ●●Disable the internal voltage adjustment function ●●One external resister must be connected between VLCD pin and VDD pin to determine the bias voltage, and internal voltage follower (OP4) must be enabled by setting the DA3~DA0 bits as the value other than “0000”. ●●If the VLCD pin is connected to the VDD pin, the internal voltage follower (OP4) must be disabled by setting the DA3~DA0 bits as “0000”. on ●●The Segment/VLCD pin is set as the VLCD pin. ●●Enable the internal voltage adjustment function. ●●The VLCD pin is an output pin of which the voltage can be detected by the external MCU host. 1 0 Segment pin off ●●The Segment/VLCD pin is set as the Segment pin. ●●Disable the internal voltage adjustment function. ●●The bias voltage is supplied by the internal VDD power. ●●The internal voltage-follower (OP4) is disabled automatically and DA3~DA0 don’t care. 1 1 Segment pin on ●●The Segment/VLCD pin is set as the Segment pin. ●●Enable the internal voltage adjustment function. ●●Power on status: Disable the internal voltage adjustment and the Segment/VLCD pin is set as the Segment pin. ●●When the DA0~DA3 bits are set to “0000”, the internal voltage-follower (OP4) is disabled. When the DA0~DA3 bits are set to other values except “0000”, the internal voltage follower (OP4) is enabled. ●●If the programmed command is not defined, the function will not be affected. Rev. 1.00 21 November 22, 2011 HT16C21 Operation Flow Chart Access procedures are illustrated below by means of the flowcharts. Initialization Power On Internal LCD bias and duty setting Internal LCD frame frequency setting Segment / VLCD shared pin setting LCD blinking frequency setting Next processing Display Data Read/Write (Address Setting) Start Address setting Display RAM data write Display on and enable internal system clock Next processing Rev. 1.00 22 November 22, 2011 HT16C21 Segment / VLCD shared pin and internal voltage adjustment setting Start Set as Segment pin Internal voltage adjustment enable ? yes Segment / VLCD share pin setting The bias voltage is supplied by Programmable Internal voltage adjustment no The bias voltage is supplied by internal VDD power Rev. 1.00 Set as VLCD pin The external MCU can detect the voltage of VLCD pin yes Internal voltage adjustment enable ? no One external resistor must be connected between to VLCD pin and VDD pin to determine the bias voltage Next processing 23 November 22, 2011 HT16C21 Application Circuit Set as Segment pin ●● 1/4 Duty VDD 0.1uF VDD 4.7KΩ VDD 4.7KΩ COM0~COM3 COM0~COM3 SCL HOST HT16C21 LCD panel SDA SEG0~SEG19 SEG0~SEG19 VSS VSS VSS ●● 1/8 duty VDD 0.1uF VDD 4.7KΩ VDD 4.7KΩ COM0~COM7 COM0~COM7 SCL HOST HT16C21 LCD panel SDA SEG4~SEG19 SEG0~SEG15 VSS VSS VSS Note: 1. If the internal VLCD voltage adjustment function is disabled, the bias voltage is supplied by internal VDD power. 2. If the internal VLCD voltage adjustment function is enabled, the bias voltage is supplied by the internal adjusted voltage selected by the DA3~DA0 bits. Rev. 1.00 24 November 22, 2011 HT16C21 Set as VLCD pin When the internal VLCD voltage adjustment function is disabled, an external resistor must be connected between the VLCD and VDD pins to determine the supplied bias voltage. ●● 1/4 duty VDD VR 0.1uF VDD 4.7KΩ VDD 4.7KΩ VLCD COM0~COM3 COM0~COM3 SCL HOST HT16C21 LCD panel SDA SEG0~SEG18 SEG0~SEG18 VSS VSS VSS ●● 1/8 duty VDD VR 0.1uF VDD 4.7KΩ VDD 4.7KΩ VLCD COM0~COM7 COM0~COM7 SCL HOST HT16C21 LCD panel SDA SEG4~SEG18 SEG0~SEG14 VSS VSS VSS Rev. 1.00 25 November 22, 2011 HT16C21 When the internal VLCD voltage adjustment function is enabled and the Segment/VLCD shared pin is set as VLCD pin, the bias voltage is supplied by the internal adjusted voltage, derived from the VDD voltage, determined by the DA3~DA0 bits and the VLCD pin is used as an output pin of which the voltage is detected by the external MCU host. ●● 1/4 duty VDD 0.1uF VDD 4.7KΩ VDD 4.7KΩ COM0~COM3 COM0~COM3 SCL HOST HT16C21 LCD panel SDA SEG0~SEG18 VLCD SEG0~SEG18 VSS VSS VSS ●● 1/8 duty VDD 0.1uF VDD 4.7KΩ VDD 4.7KΩ COM0~COM7 COM0~COM7 SCL HOST HT16C21 LCD panel SDA SEG4~SEG18 VLCD SEG0~SEG14 VSS VSS VSS Rev. 1.00 26 November 22, 2011 HT16C21 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 20-pin SOP (300mil) Outline Dimensions MS-013 Symbol Nom. Max. 0.419 A 0.393 ― B 0.256 ― 0.300 C 0.012 ― 0.020 C’ 0.496 ― 0.512 0.104 D ― ― E ― 0.050 ― F 0.004 ― 0.012 G 0.016 ― 0.050 H 0.008 ― 0.013 α 0° ― 8° Symbol Rev. 1.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 9.98 ― 10.64 B 6.50 ― 7.62 C 0.30 ― 0.51 C’ 12.60 ― 13.00 2.64 D ― ― E ― 1.27 ― F 0.10 ― 0.30 G 0.41 ― 1.27 H 0.20 ― 0.33 α 0° ― 8° 27 November 22, 2011 HT16C21 24-pin SOP (300mil) Outline Dimensions MS-013 Symbol A Min. Nom. Max. 0.393 ― 0.419 B 0.256 ― 0.300 C 0.012 ― 0.020 C’ 0.598 ― 0.613 D ― ― 0.104 E ― 0.050 ― F 0.004 ― 0.012 G 0.016 ― 0.050 H 0.008 ― 0.013 α 0° ― 8° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A 9.98 ― 10.64 B 6.50 ― 7.62 C 0.30 ― 0.51 C’ 15.19 ― 15.57 D ― ― 2.64 E ― 1.27 ― F 0.10 ― 0.30 G 0.41 ― 1.27 H 0.20 ― 0.33 α 0° ― 8° 28 November 22, 2011 HT16C21 28-pin SOP (300mil) Outline Dimensions MS-013 Symbol Nom. Max. 0.419 A 0.393 ― B 0.256 ― 0.300 C 0.012 ― 0.020 C’ 0.697 ― 0.713 0.104 D ― ― E ― 0.050 ― F 0.004 ― 0.012 G 0.016 ― 0.050 H 0.008 ― 0.013 α 0° ― 8° Symbol Rev. 1.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 9.98 ― 10.64 7.62 B 6.50 ― C 0.30 ― 0.51 C’ 17.70 ― 18.11 2.64 D ― ― E ― 1.27 ― F 0.10 ― 0.30 G 0.41 ― 1.27 H 0.20 ― 0.33 α 0° ― 8° 29 November 22, 2011 Package Information HT16C21 16-pin NSOP (150mil) Outline Dimensions 16-pin NSOP (150mil) Outline Dimensions MS-012 MS-012 Symbol Symbol A A B Dimensions in inch Dimensions in inch Nom. Min. ― Nom. 0.244 Max. 0.157 0.244 0.020 0.157 0.150 0.228 ― C 0.012 ― C' 0.386 ― D ― ― C E D F ― B C Max. Min. 0.228 0.150 0.012 0.069 0.020 0.050 ― 0.402 0.004 ― 0.010 0.069 E G 0.016 ― 0.050 0.050 F H α 0.007 0.004 ― 0.010 0.010 G H 0.386 0.402 0° ― 0.016 0.007 Symbol A B Symbol Min. 0 Nom. 5.79 ― Dimensions in mm 3.81 ― C A C' 9.805.79 B D C E F 0.10 ― G 0.41 ― H 0.18 D E α F 0.050 0.010 Dimensions in mm Min. 0.30 C 8° Max. 8 6.20 3.99 ― Nom. 0.51 Max. ― 10.21 6.20 ― 3.81 ― 1.75 3.99 ― 0.30 1.27 ― 0.51 9.80 0.25 1.27 ― 0.25 0° ― 1.27 8° 10.21 1.75 0.10 0.25 G 0.41 1.27 H 0.18 0.25 0 8 Rev. 1.00 30 November 22, 2011 Package Information HT16C21 Product Tape and Reel Specifications Reel Dimensions Reel Dimensions SOP 28W (300mil) SOP 20W, SOP 24W, SOP 28W (300mil) Symbol Description Symbol A A B B C C D T1 D T2 T1 T2 Dimensions in mm Dimensions in mm 330.01.0 330.0±1.0 100.01.5 100.0±1.5 +0.5/-0.2 13.0 13.0 +0.5/-0.2 2.0±0.5 +0.3/-0.2 24.82.00.5 30.2±0.2 24.8 +0.3/-0.2 Description Reel Outer Diameter Reel Outer Diameter Reel Inner Diameter Reel Inner Diameter Spindle Hole Diameter Spindle Hole Diameter Key Slit Width KeyBetween Slit WidthFlange Space Reel Thickness Space Between Flange Reel Thickness 30.20.2 16-pin NSOP (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.0±1.0 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 16.8 +0.3/-0.2 22.2±0.2 2 Rev. 1.00 31 April 1, 2010 November 22, 2011 Package Information HT16C21 Carrier Tape Dimensions Carrier Tape Dimensions SOP20W 28W (300mil) (300mil) SOP Symbol Symbol WW P EP FE D D1F P0D P1 D1 A0 B0P0 K0 P1 t CA0 Description Description Carrier Tape Width Carrier Tape Width Cavity Pitch Cavity Pitch Perforation Position Cavity to Perforation Perforation Position(Width Direction) Perforation Diameter Cavity to Perforation Cavity Hole Diameter (Width Direction) Perforation Pitch Perforation Diameter Cavity to Perforation (Length Direction) Cavity Hole Diameter Cavity Length Cavity Width Pitch Perforation Cavity Depth Cavity to Perforation (Length Direction) Carrier Tape Thickness Cavity Length Cover Tape Width B0 (300mil) Cavity Width SOP 24W K0 Symbol Wt P EC F D D1 P0 P1 A0 B0 K0 t C Rev. 1.00 Dimensionsininmm mm Dimensions +0.3/-0.1 24.0 24.00.3 12.0±0.1 12.00.1 1.75±0.10 11.5±0.1 1.750.10 1.5+0.1/-0.0 +0.25/-0.00 11.50.1 1.50 +0.1/-0.0 4.0±0.1 1.5 2.0±0.1 1.50 +0.25/-0.00 10.8±0.1 13.3±0.1 4.00.1 3.2±0.1 2.00.1 0.30±0.05 21.3±0.1 10.850.10 18.340.10 Cavity Depth Description Carrier Tape Width Carrier Tape Thickness Cavity Pitch Cover Tape Width Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width 2.970.10 Dimensions in mm 24.0+0.3 0.350.01 12.0±0.1 21.30.1 1.75±0.1 11.5±0.1 1.55+0.1/-0.00 1.50+0.25/-0.00 4.0±0.1 2.0±0.1 10.9±0.1 15.9±0.1 3.1±0.1 0.35±0.05 21.3±0.1 323 April 2010 November 22,1,2011 HT16C21 SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0±0.3 12.0±0.1 1.75±0.10 11.5±0.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.0±0.1 2.0±0.1 10.85±0.10 18.34±0.10 2.97±0.10 0.35±0.01 21.3±0.1 16-pin NSOP (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Rev. 1.00 Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.0±0.3 8.0±0.1 1.75±0.10 7.5±0.1 1.55+0.1/-0.0 1.50+0.25/-0.00 4.0±0.10 2.0±0.10 6.5±0.10 10.3±0.10 2.1±0.10 0.30±0.05 13.3±0.1 33 November 22, 2011 HT16C21 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. (Dongguan Sales Office) Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311, 86-769-2626-1322 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880B Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 34 November 22, 2011