A6818 DABiC-IV 32-Bit Serial Input Latched Source Driver Discontinued Product This device is no longer in production. The device should not be purchased for new design applications. Samples are no longer available. Date of status change: November 1, 2010 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact Allegro Sales. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A6818 DABiC-IV 32-Bit Serial Input Latched Source Driver Features and Benefits Description ▪ Controlled output slew rate ▪ 60 V minimum output break down ▪ PNP active pull-downs ▪ Low-power CMOS logic and latches ▪ High-speed data storage ▪ High data-input rate ▪ Low output-saturation voltages ▪ Improved replacements for SN75518N, SN75518NF, UCN5818x, and UCQ5818x The A6818 device combines a 32-bit CMOS shift register, accompanying data latches and control circuitry, with bipolar sourcing outputs and PNP active pull-downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and –40 mA output ratings also allow this device to be used in many other peripheral power driver applications. The A6818 features an increased data-input rate (compared with the older UCN/UCQ5818x) and a controlled output slew rate. Package: 44 pin PLCC (suffix EP) The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 or 5 V logic supply, typical serial data-input rates are up to 33 MHz. A CMOS serial data output permits cascaded connections in applications requiring additional drive lines. Similar devices are available as the A6810 (10-bit) and A6812 (20-bit). The A6818 output source drivers are NPN Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions Not to scale Continued on the next page… Functional Block Diagram V DD CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER STROBE LATCHES LOGIC SUPPLY SERIAL DATA OUT BLANKING MOS BIPOLAR VBB GROUND 26182.128F OUT 1 OUT 2 OUT 3 OUT N LOAD SUPPLY Dwg. FP-013-1 DABiC-IV 32-Bit Serial Input Latched Source Driver A6818 Description (continued) regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The PNP active pull-downs will sink at least 2.5 mA. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (E-), and extended industrial (K-) applications. The package style provided is the minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic- power dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. The lead (Pb) free versions have 100% matte tin leadframe plating. Selection Guide Part Number Pb-free Packing Ambient Temperature TA (°C) Yes 450 pieces/13-in. reel –40 to 85 – 450 pieces/13-in. reel –40 to 125 Yes 450 pieces/13-in. reel –20 to 85 A6818EEPTR-T A6818KEPTR A6818SEPTR-T Absolute Maximum Ratings* Characteristic Symbol Logic Supply Voltage VDD Notes Rating Units 7.0 V Driver Supply Voltage VBB 60 V Input Voltage Range VIN –0.3 to VDD + 0.3 V Continuous Output Current Range IOUT Operating Ambient Temperature Maximum Junction Temperature Storage Temperature –40 to 15 mA Range E –40 to 85 ºC Range K –40 to 125 ºC Range S –20 to 85 ºC TJ(max) 150 ºC Tstg –55 to 125 ºC TA *Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 DABiC-IV 32-Bit Serial Input Latched Source Driver A6818 Pin-out Diagram Thermal Characteristics Characteristic Package Thermal Resistance Symbol Test Conditions* RθJA Value Units 1-layer PCB with copper limited to solder pads 54 ºC/W *Additional thermal information available on the Allegro website. ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 3.0 2.5 2.0 1.5 1.0 SUFFIX 'EP', RQJA = 54oC/W 0.5 0 25 TYPICAL INPUT CIRCUIT 50 75 100 125 AMBIENT TEMPERATURE IN oC 150 TYPICAL OUTPUT DRIVER Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 DABiC-IV 32-Bit Serial Input Latched Source Driver A6818 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input Latch Contents I1 I2 I3 ... IN-1 Output Contents IN Blanklng I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H L X X ... P1 P2 P3 ... X PN-1 PN X X ... X L L ... L L L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 DABiC-IV 32-Bit Serial Input Latched Source Driver A6818 ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818Eand A6818K-), VBB = 60 V, unless otherwise noted Characteristic Output Leakage Current Output Voltage Symbol ICEX Test Conditions VOUT = 0 V Limits @ VDD = 3.3 V Limits @ VDD = 5 V Mln. Typ. Max. Min. Typ. Max. Units — <-0.1 -15 — <-0.1 -15 μA 57.5 58.3 — 57.5 58.3 — V VOUT(1) IOUT = -25 mA VOUT(0) IOUT = 1 mA — 1.0 1.5 — 1.0 1.5 V Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA Input Voltage VIN(1) 2.2 — — 3.3 — — V VIN(0) — — 1.1 — — 1.7 V Input Current Input Clamp Voltage Serial Data Output Voltage Maximum Clock Frequency Logic Supply Current IIN(1) VIN = VDD — <0.01 1.0 — <0.01 1.0 μA IIN(0) VIN = 0.8 V — <-0.01 -1.0 — <-0.01 -1.0 μA IIN = -200 μA — -0.8 -1.5 — -0.8 -1.5 V VOUT(1) IOUT = -200 μA 2.8 3.05 — 4.5 4.75 — V VOUT(0) IOUT = 200 μA — 0.15 0.3 — 0.15 0.3 V 10 33 — 10 33 — MHz VIK fc IDD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA IDD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA IBB(1) All Outputs High, No Load — 4.5 9.0 — 4.5 9.0 mA IBB(0) All Outputs Low — 0.2 20 — 0.2 20 μA tdis(BQ) CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 μs ten(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 μs tp(STH-QL) RL = 2.3 k, CL 30 pF — 0.7 2.0 — 0.7 2.0 μs tp(STH-QH) RL = 2.3 k, CL 30 pF — 1.8 3.0 — 1.8 3.0 μs Output Fall Time tf RL = 2.3 k, CL 30 pF 2.4 — 12 2.4 — 12 μs Output Rise Time tr RL = 2.3 k, CL 30 pF 2.4 — 12 2.4 — 12 μs Output Slew Rate dV/dt RL = 2.3 k, CL 30 pF 4.0 — 20 4.0 — 20 V/μs IOUT = ±200 μA — 50 — — 50 — ns Load Supply Current Blanking-to-Output Delay Strobe-to-Output Delay Clock-to-Serial Data Out Delay tp(CH-SQX) Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25°C. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 DABiC-IV 32-Bit Serial Input Latched Source Driver A6818 TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ........................................... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ................................................ 25 ns C. Clock Pulse Width, tw(CH) ................................................. 50 ns D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns E. Strobe Pulse Width, tw(STH) .............................................. 50 ns NOTE – Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 DABiC-IV 32-Bit Serial Input Latched Source Driver A6818 Package EP, 44-Pin PLCC 17.53 ±0.13 16.59 ±0.08 0.51 2 1 44 7.75 ±0.36 A 17.53 ±0.13 16.59 ±0.08 7.75 ±0.36 0.74 ±0.08 4.57 MAX 44X SEATING PLANE 0.10 C 0.43 ±0.10 C 1.27 7.75 ±0.36 7.75 ±0.36 For Reference Only (reference JEDEC MS-018 AC) Dimensions in inches, metric dimensions (mm) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Copyright ©1998-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7