Data Sheet 26182.28D 5818-F BiMOS II 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS OUT29 OUT 1 OUT2 OUT3 41 40 SERIAL DATA IN 43 42 LOAD SUPPLY LOGIC SUPPLY OUT32 SERIAL DATA OUT 2 1 OUT31 3 VBB OUT30 4 V DD 44 NC 6 5 UCN5818EPF 7 39 2 8 38 9 37 10 LATCHES 12 REGISTER LATCHES REGISTER 36 11 35 34 OUT 8 13 33 19 14 32 15 31 16 30 OUT13 T C U 8 D Y 1 L 8 O 6 N R P E O —A These smart power drivers have been designed with BiMOS II logic for improved data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use of these devices with TTL may require the use of appropriate pull-up resistors to ensure an input logic high. All devices can be operated over the ambient temperature range of 20°C to +85°C. The UCN5818AF is supplied in a 40-pin plastic dual in-line package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced supply current requirement, and low output saturation voltage permits operation with minimum junction temperature rise. The ‘A’ package allows all 32 outputs to be operated at -25 mA continuously over the operating temperature range. t D C n E N e E U m R e N E ac I T l F p E N e r R O d R C e S FO nd I D — me 27 28 NC 25 OUT16 OUT14 ST 24 OUT15 26 CLK 23 CLOCK GROUND 22 20 OUT17 BLANKING 21 18 19 NC STROBE 29 BLNK 17 OUT18 OUT19 OUT 4 Designed primarily for use with vacuum-fluorescent displays, the UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine CMOS shift registers, data latches, and control circuitry, with bipolar highspeed sourcing outputs and DMOS active pull-down circuitry. The highspeed shift register and data latches allow direct interfacing with microprocessor LSI-based systems. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Both devices feature 60 V and -40 mA output ratings, allowing them to be used in many other peripheral power driver applications. NC Dwg. PP-059-2 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD .................... 15 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD (UCN5818AF) ............................ 3.5 W* (UCN5818EPF) ......................... 2.3 W† Operating Temperature Range, TA ................................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +150°C m o c e R For high-density packaging applications, the UCN5818EPF is furnished in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous operation of all outputs simultaneously at ambient temperatures to 60°C. Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5812AF/EPF (20 bits). FEATURES ■ ■ ■ ■ ■ 60 V Source Outputs High-Speed Source Drivers To 3.3 MHz Data Input Rate Low-Output Saturation Voltages Active DMOS Pull-Downs ■ Low-Power CMOS Logic and Latches ■ Reduced Supply Current Requirements ■ Improved Replacements for SN75518N/FN * Derate at rate of 28 mW/°C above TA = +25°C † Derate at rate of 18 mW/°C above TA = +25°C Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Always order by complete part number, e.g., UCN5818EPF . 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5818AF FUNCTIONAL BLOCK DIAGRAM 40 LOGIC SUPPLY 2 39 SERIAL DATA IN OUT 32 3 38 OUT 1 LOAD SUPPLY 1 SERIAL DATA OUT VBB VDD OUT 3 OUT 29 6 35 OUT 4 OUT 28 7 34 OUT 5 OUT 27 8 33 OUT 6 OUT 26 9 32 OUT 7 LATCHES OUT 2 36 REGISTER 37 5 LATCHES 4 REGISTER OUT 31 OUT 30 31 OUT 8 30 OUT 9 12 29 OUT 10 OUT 22 13 28 OUT 11 OUT 21 14 27 OUT 12 OUT 20 15 26 OUT 13 OUT 19 16 25 OUT 14 OUT 18 17 24 OUT 15 OUT 25 10 OUT 24 11 OUT 23 OUT 17 18 BLANKING 19 GROUND 20 BLNK 23 OUT 16 ST 22 STROBE CLK 21 CLOCK LOGIC SUPPLY V DD CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER STROBE LATCHES SERIAL DATA OUT BLANKING MOS BIPOLAR VBB GROUND OUT 1 OUT 2 OUT 3 OUT N LOAD SUPPLY Dwg. FP-013-1 TYPICAL INPUT CIRCUIT VDD IN Dwg. PP-029-4 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 3.0 2.5 Dwg. EP-010-5 SUFFIX 'A', RθJA = 36°C/W TYPICAL OUTPUT DRIVER 2.0 V BB 1.5 SUFFIX 'EP', RθJA = 54°C/W 1.0 OUT N 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN ° C 150 Dwg. No. A-14,219 Dwg. GP-025B 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1988, 2002 Allegro MicroSystems, Inc. 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS ELECTRICAL CHARACTERISTICS at TA = + 25°C, VBB = 60 V unless otherwise noted. Limits @ VDD = 5 V Characteristic Symbol Output Leakage Current Output Voltage Output Pull-Down Current Input Voltage Input Current Serial Data Output Voltage Limits @ VDD = 12 V Test Conditions Mln. Typ. Max. Min. Typ. Max. Units ICEX VOUT = 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA VOUT(1) IOUT = -25 mA 58 58.5 — 58 58.5 — V VOUT(0) IOUT = 1 mA — 2.0 3.0 — — — V IOUT = 2 mA — — — — 2.0 3.5 V VOUT = 5 V to VBB 2.0 3.5 — — — — mA VOUT = 20 V to VBB — — — 8.0 13 — mA VIN(1) 3.5 — 5.3 10.5 — 12.3 V VIN(0) -0.3 — +0.8 -0.3 — +0.8 V IOUT(0) IIN(1) VIN = VDD — 0.05 0.5 — 0.1 1.0 µA IIN(0) VIN = 0.8 V — -0.05 -0.5 — -0.1 -1.0 µA VOUT(1) IOUT = -200 µA 4.5 4.7 — 11.7 11.8 — V VOUT(0) IOUT = 200 µA — 200 250 — 100 200 mV 3.3* — — — — — MHz Maximum Clock Frequency fclk Supply Current IDD(1) All Outputs High — 100 300 — 200 500 µA IDD(0) All Outputs Low — 100 300 — 200 500 µA IBB(1) Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA IBB(0) Outputs Low — 10 100 — 10 100 µA tPHL CL = 30 pF, 50% to 50% — 2000 — — 1000 — ns tPLH CL = 30 pF, 50% to 50% — 1000 — — 850 — ns Output Fall Time tf CL = 30 pF, 90% to 10% — 1450 — — 650 — ns Output Rise Time tr CL = 30 pF, 10% to 90% — 650 — — 700 — ns Blanking to Output Delay Negative current is defined as coming out of (sourcing) the specified device terminal. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. www.allegromicro.com 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS CLOCK A B Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. D DATA IN E F C STROBE BLANKING G OUTN Dwg. No. A-12,649A TIMING REQUIREMENTS (TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns G. Typical Time Between Strobe Activation and Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input Latch Contents I1 I2 I3 ... IN-1 Output Contents IN Blanking I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H L X X ... P1 P2 P3 ... L = Low Logic Level X PN-1 PN H = High Logic Level X = Irrelevant X P = Present State X ... X R = Previous State 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 L L ... L L 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5818AF Dimensions in Inches (controlling dimensions) 40 0.015 0.008 21 0.700 MAX 0.580 0.485 0.600 BSC 1 2 0.070 0.030 3 20 0.100 4 2.095 1.980 0.005 MIN BSC 0.250 MAX 0.015 0.200 0.115 MIN 0.022 0.014 Dwg. MA-003-40 in Dimensions in Millimeters (for reference only) 40 0.381 0.204 21 17.78 MAX 14.73 12.32 15.24 BSC 1 2 1.77 0.77 3 4 2.54 53.2 50.3 BSC 20 0.13 MIN 6.35 MAX 0.39 5.08 2.93 MIN 0.558 0.356 NOTES: 1. 2. 3. 4. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 9 devices. www.allegromicro.com Dwg. MA-003-40 mm 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS UCN5818EPF Dimensions in Inches (controlling dimensions) 18 28 29 17 0.032 0.026 0.319 0.291 0.695 0.685 0.021 0.013 0.656 0.650 0.319 0.291 0.050 INDEX AREA BSC 7 39 40 0.020 44 1 2 6 0.656 0.650 MIN 0.695 0.685 0.180 0.165 Dwg. MA-005-44A in Dimensions in Millimeters (for reference only) 28 18 29 17 0.812 0.661 8.10 7.39 17.65 17.40 0.533 0.331 16.662 16.510 8.10 7.39 INDEX AREA 1.27 BSC 39 7 40 0.51 MIN 4.57 4.20 44 1 2 6 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. www.allegromicro.com 5818-F 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS POWER INTERFACE DRIVERS Function Output Ratings* Part Number† SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit (constant-current LED driver) 8-Bit (constant-current LED driver) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) -120 mA 350 mA 350 mA 350 mA 350 mA 75 mA 120 mA 250 mA 350 mA 100 mA 50 V‡ 50 V 80 V 50 V‡ 80 V‡ 17 V 24 V 50 V 50 V‡ 50 V 5895 5821 5822 5841 5842 6275 6277 6595 6A595 6B595 10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6810 12-Bit (active pull-downs) -25 mA 60 V 5811 75 mA 17 V 6276 20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) -25 mA 100 mA 100 mA 60 V 30 V 40 V 5818-F and 6818 5833 5832 16-Bit (constant-current LED driver) PARALLEL-INPUT LATCHED DRIVERS 4-Bit 350 mA 50 V‡ 5800 8-Bit 8-Bit 8-Bit (DMOS drivers) 8-Bit (DMOS drivers) -25 mA 350 mA 100 mA 250 mA 60 V 50 V‡ 50 V 50 V 5815 5801 6B273 6273 SPECIAL-PURPOSE DEVICES Unipolar Stepper Motor Translator/Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 8-Bit Decoder/DMOS Driver Addressable 28-Line Decoder/Driver 1.25 A 250 mA 350 mA 100 mA 450 mA 50 V‡ 50 V 50 V‡ 50 V 30 V 5804 6259 6A259 6B259 6817 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional characters to indicate operating temperature range and package style. ‡ Internal transient-suppression diodes included for inductive-load protection. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000