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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300208-E-V16
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
EXTERNAL BUS INTERFACE
APPLICATION NOTE
EXTERNAL BUS INTERFACE
Revision History
Revision History
Date
2006-07-13
2007-06-22
2007-08-10
2007-09-28
2007-10-04
2008-07-08
2009-11-12
Issue
V1.0
First Version; MWi
V1.1
Updated software example and timing analysis; HPi
V1.2
Updated Timing analysis chapter; HPi
V1.3
Updated example in section 4 ; HPi
V1.4
Updated example in section 4 ; HPi
V1.5
Correct start address of Chip Select area 1 to 0x000C00; add more
information on chip select area size and alignment; PHu
V1.6
Typos corrected
Chapter External Vector Mode added; MWi
This document contains 35 pages.
MCU-AN-300208-E-V16
-2-
© Fujitsu Microelectronics Europe GmbH
EXTERNAL BUS INTERFACE
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (e.g. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
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Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
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Microelectronics Europe GmbH warrants that the Product will be free from defects in material
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for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
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© Fujitsu Microelectronics Europe GmbH
-3-
MCU-AN-300208-E-V16
EXTERNAL BUS INTERFACE
Contents
Contents
REVISION HISTORY.............................................................................................................. 2
WARRANTY AND DISCLAIMER........................................................................................... 3
CONTENTS ............................................................................................................................ 4
1 INTRODUCTION................................................................................................................ 6
1.1
Key Features............................................................................................................. 6
2 THE EXTERNAL BUS INTERFACE.................................................................................. 7
2.1
Outline....................................................................................................................... 7
2.1.1
2.2
Address Maps of Bus Modes ...................................................................... 7
Registers ................................................................................................................... 8
2.2.1
External Bus Mode Register (EBM).............................................................. 8
2.2.2
External Bus Clock and Function Register (EBCF)...................................... 8
2.2.3
External Bus Control Signal Register (EBCS).............................................. 9
2.2.4
External Area Configuration Register (Lower Byte) (EACL[5:0]) ............. 9
2.2.5
External Area Configuration Register (Upper Byte) (EACH[5:0]) ........... 10
2.2.6
External Area Select Register (EAS[5:2]) .............................................. 10
2.2.7
External Bus Address Output Enable Register (EBAE[2:0]) .................. 11
2.2.8
Port Input Enable ...................................................................................... 12
3 INITIALIZATION IN START.ASM.................................................................................... 13
3.1
Start.asm................................................................................................................. 13
3.1.1
Enabling the External Bus Interface.......................................................... 13
3.1.2
Enabling Chip Select................................................................................. 13
3.1.3
Enabling Clock Timing Signals.................................................................. 14
3.1.4
Setting Clock Divider................................................................................. 14
3.1.5
Selecting used Address Pins .................................................................... 14
3.1.6
Setting Bus Control Lines.......................................................................... 15
3.1.7
Setting External Area Configuration.......................................................... 15
3.1.8
External Memory Program Bank ............................................................... 15
3.1.9
Automatic Port Enable .............................................................................. 15
4 EXTERNAL BUS INTERFACE EXAMPLES ................................................................... 17
4.1
Hardware Example for Multiplex Mode ................................................................... 17
4.2
Hardware Example for Non Multiplexed Mode........................................................ 18
4.3
Hardware Example for Chip Select using external address decoder...................... 19
4.4
Software Example an External Data Section Declaration ....................................... 19
MCU-AN-300208-E-V16
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© Fujitsu Microelectronics Europe GmbH
EXTERNAL BUS INTERFACE
Contents
4.5
4.4.1
Linker Settings .......................................................................................... 20
4.4.2
External Memory Variable Declaration...................................................... 20
Software Example to Write and Read data from flash ............................................ 20
5 EXTERNAL VECTOR MODES........................................................................................ 24
5.1
External Boot Vector ............................................................................................... 24
5.2
Software Recommendations and Cautions............................................................. 24
5.2.1
Mode Byte ................................................................................................. 24
5.2.2
Chip Select Configuration Order in Start Code ......................................... 25
6 TIMING ANALYSIS.......................................................................................................... 27
6.1
Flash Read AC characteristics................................................................................ 27
6.2
RAM Read and Write AC characteristics ................................................................ 28
6.3
MCU Read AC characteristics ................................................................................ 30
6.4
MCU Write AC characteristics................................................................................. 30
6.5
Timing Analysis ....................................................................................................... 32
6.5.1
Flash Timing Analysis ............................................................................... 32
6.5.2
RAM Timing Analysis ................................................................................ 33
7 ADDITIONAL INFORMATION......................................................................................... 35
© Fujitsu Microelectronics Europe GmbH
-5-
MCU-AN-300208-E-V16
EXTERNAL BUS INTERFACE
Chapter 1 Introduction
1 Introduction
This application note describes the functionality of the External Bus Interface and gives
some hardware and software examples.
The External Bus Interface is used to connect additional hardware to the MCU such like
RAM, Flash-Memory or other controllers.
1.1
Key Features
•
Data Bus Width 8 or 16 Bit
•
Big or little Endian selectable for Data Bus
•
Up to 24 Bit Address Bus (depending on Device)
•
Multiplexed Bus (and non-multiplexed Bus at Devices with high Pin Count)
•
Up to 6 Chip Select Signals with programmable Memory Area
•
0, 1, 2, 3, 4, 8, 16, and 32 Wait states can be inserted for a Read/Write Cycle
•
Address, Read, Write, Upper-Byte and Lower-byte Strobe Signals
•
Polarity of Address Strobe selectable
•
Address Cycle extendable to 2 Clock Cycles
•
External Clock Signal can be enabled, the polarity is selectable, the frequency can be
divided up to 128 in 2n-Steps
•
Ready and Hold Function
MCU-AN-300208-E-V16
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© Fujitsu Microelectronics Europe GmbH
EXTERNAL BUS INTERFACE
Chapter 2 The External Bus Interface
2 The External Bus Interface
THE BASIC FUNCTIONALITY OF THE EXTERNAL BUS INTERFACE
2.1
Outline
The External Bus Interface allows the user to connect external peripherals or memory to the
MCU. The Bus consists of data, address and control signals. Various settings are possible
for several bus timings.
2.1.1 Address Maps of Bus Modes
Figure 2-1 shows the different address maps for the three MCU bus modes.
ff:0000
Single Chip
Internal ROM,
external bus
External ROM,
external bus
ROM/Flash
ROM/Flash
External ROM
(Belongs to ext. Area 2 – 5)
external area 2-5
e0:0000
external area 2-5
de:0000
external area 2-5
10:0000
Boot - ROM
Boot - ROM
RAM
RAM
RAM
ROM/RAM-Mirror
ROM/RAM-Mirror
ROM/RAM-Mirror
RAM
RAM
RAM
external area 1
external area 1
Core/Peripheral
Core/Peripheral
external area 0
external area 0
Peripheral
Peripheral
0f:0000
Boot - ROM
01:0000
00:8000
00:x000
00:0c00
00:0100
Core/Peripheral
00:00f0
00:0000
Peripheral
RAM Start-32
: Internal
: External
: No Access
Figure 2-1: Address Maps of Bus Modes
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300208-E-V16
EXTERNAL BUS INTERFACE
Chapter 2 The External Bus Interface
2.2
Registers
2.2.1 External Bus Mode Register (EBM)
Bit
No.
Name
Explanation
Initial
Value
7
NMS
Non-multiplexed
Bus select
0
6
ERE
5
EAE5
4
EAE4
3
EAE3
2
EAE2
External Area 2
Select
0
1
EAE1
External Area 1
Select
0
0
EAE0
External Area 0
Select
0
External ROM
enable
External Area 5
Select
External Area 4
Select
External Area 3
Select
Value
Operation
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address/Data multiplexed
Address/Data non-multiplexed
Disable External ROM
Enable External ROM
Disable 0xC00000-0xFFFFFF
Enable 0xC00000-0xFFFFFF
Disable 0x800000-0xBFFFFF
Enable 0x800000-0xBFFFFF
Disable 0x400000-0x7FFFFF
Enable 0x400000-0x7FFFFF
Disable 0x100000-0x3FFFFF
Enable 0x100000-0x3FFFFF
Disable 0x000C00-(RAM-Start – 0x21)
Enable 0x000C00-(RAM-Start – 0x21)
Disable 0x0000F0-0x0000FF
Enable 0x0000F0-0x0000FF
0
0
0
0
2.2.2 External Bus Clock and Function Register (EBCF)
Bit
No.
Name
15
HDE
14
RYE
13
CKE
12
CKI
11
CSM
Explanation
Hold function
enable
External Ready
Function enable
External Bus Clock
Output Enable
External Bus Clock
Inversion Control
External Bus Clock
Suspend Mode
Control
Initial
Value
0
Value
Operation
0
Disable Hold Function
Enable Hold Function
Disable external Ready Function
Enable external Ready Function
Enable I/O Port Operation
Enable external Bus Clock Output
Disable Clock Output Inversion
Enable Clock Output Inversion
External Bus Clock is always
output
External Bus Clock is only output
during data transfer
CLKB bypassed to ECLK
CLKB is divided by 2 for ECLK
CLKB is divided by 4 for ECLK
CLKB is divided by 8 for ECLK
CLKB is divided by 16 for ECLK
CLKB is divided by 32 for ECLK
CLKB is divided by 64 for ECLK
CLKB is divided by 128 for ECLK
1
0
0
1
0
0
1
0
0
1
0
0
1
0, 0, 0
0, 0, 1
10
…
8
DIV2
…
DIV0
0, 1, 0
External Clock
Divider (ECLK)
0, 0, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
MCU-AN-300208-E-V16
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© Fujitsu Microelectronics Europe GmbH
EXTERNAL BUS INTERFACE
Chapter 2 The External Bus Interface
2.2.3 External Bus Control Signal Register (EBCS)
Bit
No.
Name
15
-
14
ASL
13
ASE
12
RDE
11
WRHE
Write Strobe (WRHX)
enable
0
10
WRLE
Write Strobe
(WRLX/WRX) enable
0
9
UBE
Upper Byte (UBX)
Output Enable
0
8
LBE
Lower Byte (LBX)
Output Enable
0
Explanation
Initial
Value
Value
X
-
Reserved
Address Strobe
Level Select
Address Strobe
Output Enable
Read Strobe Output
Enable
Read: Undefined
Write: Always write “0”
Low-active: ASX
High-active: ALE
Enable I/O Port
Enable Address Strobe
Enable I/O Port
Enable Read Strobe Output
Enable I/O Port
Enable WRHX Output
0
1
1
0
0
1
0
0
Operation
1
0
1
Enable I/O Port
Enable WRLX/WRX Output
0
1
Enable I/O Port
Enable UBX Output
0
1
Enable I/O Port
Enable LBX Output
0
1
2.2.4 External Area Configuration Register (Lower Byte) (EACL[5:0])
Bit
No.
Name
7
BW
External Bus
Data Width
6
ES
Endian Select
0
5
WSF
Write Strobe
function of
WRLX/WRX pin
0
4
STS
Strobe time
scheme select
3
ACE
2
…
0
R2
…
R0
Explanation
Initial
Value
0*
Operation
Value
0
16-Bit Bus Width
8-Bit Bus Width
Select little endian
Select big endian
Enable WRLX
1
Enable WRX
0
1
1
0
1
Enable Address Strobe during first
half of Address on Bus
0
Enable Address Strobe during
1
whole time of Address on Bus
0
Address Cycle
Disable Cycle Extension
0
Extension
1
Enable One Bus Cycle Extension
0, 0, 0 Disable Automatic Ready Function
0, 0, 1 Automatic Wait of 1 Cycle
0, 1, 0 Automatic Wait of 2 Cycles
0, 0, 0
0, 1, 1 Automatic Wait of 3 Cycles
Automatic
2
1, 0, 0 Automatic Wait of 4 Cycles
Ready Function
0, 1, 1*
1, 0, 1 Automatic Wait of 8 Cycles
1, 1, 0 Automatic Wait of 16 Cycles
1, 1, 1 Automatic Wait of 32 Cycles
1
* 1 for EACL5 after external start vector fetch in 8-Bit Mode
*2 1 for EACL5 after external start vector fetch
0
Note that for each of the 6 external memory areas a corresponding EACLn exists.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300208-E-V16
EXTERNAL BUS INTERFACE
Chapter 2 The External Bus Interface
2.2.5 External Area Configuration Register (Upper Byte) (EACH[5:0])
Bit
No.
Name
15
-
14
-
13
ATL
12
CSL
11
CSE
Initial
Value
Value
Reserved
X
-
Reserved
X
-
Explanation
Access
Type
Limitation
Chip Select
Level Select
Chip Select
Output
Enable
0
0
Operation
0
Read: Undefined
Write: Always write “0”
Read: Undefined
Write: Always write “0”
Enable Code Fetch and Data Read
1
Enable only Data Read
0
0
Enable CSX
Enable CS
Enable I/O Port
1
Enable Chip Select Output
1
0
64 K Bytes, EASn_A[7:0] valid
128 K Bytes, EASn_A[7:1] valid
0, 1, 0 256 K Bytes, EASn_A[7:2] valid
0, 1, 1 512 K Bytes, EASn_A[7:3] valid
1, 0, 0 1 M Byte, EASn_A[7:4] valid
1, 0, 1 2 M Bytes, EASn_A[7:5] valid
1, 1, 0 4 M Bytes, EASn_A[7:6] valid
1, 1, 1 8 M Bytes, EASn_A7 valid
*2 1 for EACL5 after external start vector fetch
0, 0, 0
0, 0, 1
EASZ2
…
EASZ0
10
…
8
External
Area Size
1, 1, 0
0, 1, 1*
2
Note that for each of the 6 external memory areas a corresponding EACHn exists.
The External Area Size can be selected only for areas 2 – 5. The size is selected by
masking the address lines A16 – A22 (depending on configuration), which correspond of the
lower bits of External Area Select Register (EAS). By masking address lines, the selected
area is automatically aligned to its own size. Refer 0
Example Settings of EAS[5:2] for examples.
2.2.6 External Area Select Register (EAS[5:2])
For areas 2 to 5 an External Area Select Register exists. This Byte Register holds the
address bits for the upper 8-Bit address comparison (address bank) for the chip select
signals. It is also the start bank of the chip select. The end address is defined by these
registers and the corresponding area size defined by EACHn_EASZ[2:0].
The following table shows the initial values.
External
Area
Default Memory Area
Start
End
Initial Values
Chip
Select
EAS2 = 0x10
CS2(X)
0x100000
0x3FFFFF
EACH2_EASZ[2:0] = 110
EAS3 = 0x40
CS3(X)
0x400000
0x7FFFFF
3
EACH3_EASZ[2:0] = 110
EAS4 = 0x80
CS4(X)
0x800000
0xBFFFFF
4
EACH4_EASZ[2:0] = 110
EAS5 = 0xC0
CS5(X)
0xC00000
0xFFFFFF
5
EACH5_EASZ[2:0] = 110
Note, that all areas except area 0 – 2 have a default size of 4 M Bytes. The default size of
area 2 is 3 M Bytes, and the size of area 0 and 1 cannot be changed.
2
MCU-AN-300208-E-V16
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© Fujitsu Microelectronics Europe GmbH
EXTERNAL BUS INTERFACE
Chapter 2 The External Bus Interface
The External Area Select Register can point to any bank within the memory range that is
selected in combination with EACH_EASZ bits.
Example Settings of EAS[5:2]
Address
FFFFFFH
F00000H
EFFFFFH
E00000H
DFFFFFH
D00000H
CFFFFFH
C00000H
BFFFFFH
B00000H
AFFFFFH
A00000H
9FFFFFH
900000H
8FFFFFH
800000H
7FFFFFH
700000H
6FFFFFH
600000H
5FFFFFH
500000H
4FFFFFH
400000H
3FFFFFH
300000H
2FFFFFH
200000H
1FFFFFH
100000H
EASZ: 1M
EASZ: 2M
EASZ: 4M
EASZ: 8M
EAS:
A7, A6, A5, A4
EAS:
A7, A6, A5
EAS:
A7, A6
EAS:
A7
1, 1, 1, 1
1, 1, 1
1, 1, 1, 0
1, 1
1, 1, 0, 1
1, 1, 0
1, 1, 0 ,0
1, 0, 1, 1
1
1, 0, 1
1, 0, 1, 0
1, 0, 0, 1
1, 0
1, 0, 0
1, 0, 0, 0
0, 1, 1, 1
0, 1, 1
0, 1, 1, 0
0, 1, 0, 1
0, 1
0, 1, 0
0
0, 1, 0, 0
0, 0, 1, 1
0, 0, 1
0, 0
0, 0, 1, 0
0, 0, 0, 1
0, 0, 0
It is possible to set individual areas, when using different area sizes for EACH_EASZ bits.
The following table shows such an example configuration.
External
Area
2
3
4
5
Default Memory Area
Start
End
Initial Values
EAS2 = 0x18
EACH2_EASZ[2:0] =
EAS3 = 0x60
EACH3_EASZ[2:0] =
EAS4 = 0x73
EACH4_EASZ[2:0] =
EAS5 = 0xFE
EACH5_EASZ[2:0] =
001
010
000
001
Chip
Select
0x180000
0x19FFFF
CS2(X)
0x600000
0x63FFFF
CS3(X)
0x700000
0x73FFFF
CS4(X)
0xFE0000
0xFFFFFF
CS5(X)
2.2.7 External Bus Address Output Enable Register (EBAE[2:0])
This 24-Bit Register (2 words) contains the output enable for the 24 address pins. Bit 0 is
assigned to AD0, Bit 1 to AD1, and so on. The upper byte of the second word is ignored. The
initial values are “0”, if internal reset vector fetch is used.
These enable bits are used to define the minimum of address pins needed and save the I/O
port number.
Please note, that after external reset vector fetch all bits are “1”, i. e. all address lines are
used.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300208-E-V16
EXTERNAL BUS INTERFACE
Chapter 2 The External Bus Interface
2.2.8 Port Input Enable
Please also note, that the corresponding Port Input Enable Registers for the used data and
control pins (if used) have to be enabled, otherwise data/control input does not work (always
“0” is read).
Series
MB96340/350
MB96380
MB96320
Data Bus Width
8 Bit
16 Bit
PIER00
PIER00, PIER01
PIER01
PIER01, PIER02
PIER00
PIER00, PIER01
MCU-AN-300208-E-V16
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HRQ
RDY
PIER03_IE4 PIER03_IE6
PIER12_IE7 PIER00_IE2
PIER03_IE4 PIER03_IE6
© Fujitsu Microelectronics Europe GmbH
EXTERNAL BUS INTERFACE
Chapter 3 Initialization in Start.asm
3 Initialization in Start.asm
INITIALIZATION OF THE EXTERNAL BUS INERFACE IN START.ASM
3.1
Start.asm
In the start up file Start.asm, which is included in our template project, the External Bus
Interface can be initialized before branching to the application. Therefore the application
itself does not need to set up the External Bus Interface, but use it from the beginning on.
The user can adjust the setting in the lines with a “<<<” in the comments on the right side.
3.1.1 Enabling the External Bus Interface
;====================================================================
; 4.7 External Bus Interface
;====================================================================
#set
#set
#set
SINGLE_CHIP
INTROM_EXTBUS
EXTROM_EXTBUS
0
1
2
; all internal
; mask ROM or FLASH memory used
; full external bus (INROM not used)
#set
BUSMODE INTROM_EXTBUS
; <<< set bus mode (see mode pins)
#set
#set
MULTIPLEXED
0
NON_MULTIPLEXED 1
;
; only if supported by the device
#set
ADDRESSMODE MULTIPLEXED
; <<< set address-mode
; Some devices support multiplexed and/or non-multiplexed Bus mode
; please refer to the related datasheet/hardware manual
BUSMODE INTROM_EXTBUS set the External Bus Interface to internal Flash memory and the
external memory enabled. The setting corresponds to the EBM_ERE bit (2.2.1).
ADRESSMODE MULTIPLEXED sets the Interface to address/data bus in multiplexed mode
(EBM_NMS)(2.2.1).
3.1.2 Enabling Chip Select
; Select the used Chip Select areas
#set
CHIP_SELECT0
OFF
; <<< enable chip select area
#set
CHIP_SELECT1
OFF
; <<< enable chip select area
#set
CHIP_SELECT2
OFF
; <<< enable chip select area
#set
CHIP_SELECT3
ON
; <<< enable chip select area
#set
CHIP_SELECT4
OFF
; <<< enable chip select area
#set
CHIP_SELECT5
OFF
; <<< enable chip select area
0
1
2
3
4
5
ON sets the corresponding Chip Select signal. Here it is for example CSX3 for the default
area 0x400000 – 0x7FFFFF. This setting adjusts then EMB_EAE[5:0] bits (2.2.1).
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300208-E-V16
EXTERNAL BUS INTERFACE
Chapter 3 Initialization in Start.asm
3.1.3 Enabling Clock Timing Signals
#set
#set
#set
#set
#set
HOLD_REQ
EXT_READY
EXT_CLOCK_ENABLE
EXT_CLOCK_INVERT
EXT_CLOCK_SUSPEND
OFF
OFF
ON
OFF
OFF
; <<< select Hold function
; <<< select external Ready function
; <<< select external bus clock output
; <<< select clock inversion
; <<< select if external clock is suspended
;
when no transfer in progress
These settings control several bits of the EBCF Register (2.2.2). In this example none of the
options is set.
3.1.4 Setting Clock Divider
; The external bus clock is derived from core clock CLKB. Select the divider
;
for the external bus clock.
#set
#set
#set
#set
#set
#set
#set
#set
EXT_CLOCK_DIV1
EXT_CLOCK_DIV2
EXT_CLOCK_DIV4
EXT_CLOCK_DIV8
EXT_CLOCK_DIV16
EXT_CLOCK_DIV32
EXT_CLOCK_DIV64
EXT_CLOCK_DIV128
#set
EXT_CLOCK_DIVISION
0
1
2
3
4
5
6
7
EXT_CLOCK_DIV1 ; <<< select clock divider
In this example the clock for the External Bus Interface is not divided by the option
EXT_CLOCK_DIV1. This setting controls EBCF_DIV[2:0] (2.2.2).
3.1.5 Selecting used Address Pins
With the following setting, the used address pins, corresponding to the size of the external
memory space, are set to address output.
#set
ADDR_PINS_23_16
B'11111111
#set
ADDR_PINS_15_8
B'11111111
#set
ADDR_PINS_7_0
B'11111111
; <<< select used address lines
;
A23..A16 to be output.
; <<< select used address lines
;
A15..A8 to be output.
; <<< select used address lines
;
A7..A0 to be output.
In this example the address lines A0 – A21 are used, which represents a memory space of 4
M Bytes. These bits are those of the 2 EBAE registers (2.2.7).
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EXTERNAL BUS INTERFACE
Chapter 3 Initialization in Start.asm
3.1.6 Setting Bus Control Lines
The settings for the EBCS register (2.2.3) can be found in the following settings. They mostly
depend on the connected type of memory.
In this case all lines except HWRX are selected.
#set
#set
#set
#set
#set
#set
#set
LOW_BYTE_SIGNAL
HIGH_BYTE_SIGNAL
LOW_WRITE_STROBE
HIGH_WRITE_STROBE
READ_STROBE
ADDRESS_STROBE
ADDRESS_STROBE_LVL
ON
ON
ON
OFF
ON
ON
ON
;
;
;
;
;
;
;
;
select low byte signal LBX
select high byte signal UBX
select write strobe signal WRLX/WRX
select write strobe signal WRHX
select read strobe signal RDX
select address strobe signal ALE/ASX
select address strobe function:
OFF - active low; ON - active high
3.1.7 Setting External Area Configuration
In the following bit definitions the settings of the EACL/H register (2.2.4/2.2.5) is done.
Please note, that for each external memory area, an own setting block exists (0 – 5). In the
following code the settings for area 4 are done.
#set
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CS3_CONFIG
B'0000111000100000
|||||||||||||+++-|||||||||||||
||||||||||||+----||||||||||||
|||||||||||+-----||||||||||+------||||||||||
|||||||||+-------||||||||+--------|||||+++---------|||||
|||||
||||+------------||||
|||+-------------|||
||+--------------||
++----------------
; <<< select Chip Select Area 0 configuration
Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3,
4: 4, 5: 8, 6: 16, 7: 32)
Address Cycle Extension (0: not extended,
1: extension by 1 cycle)
Strobe timing (0: scheme 0, 1: scheme 1)
Write strobe function (0: WRLX strobe,
1: WRX strobe)
Endianess (0: little endian, 1: big endian)
Bus width (0: 16bit, 1: 8bit)
External area size (0: 64kB, 1: 128kB,
2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB,
7: 8MB)
Chip Select output enable (0: CS disabled,
1: CS enabled)
Chip Select level (0: low active,
1: high active)
Access type limitation (0: code and data,
1: data only)
ignored
For correct bit position please follow the hinted lines down/right and left/up.
3.1.8 External Memory Program Bank
#set
#set
#set
#set
CS2_START
CS3_START
CS4_START
CS5_START
0x00
0x40
0x80
0xC0
;
;
;
;
chip
chip
chip
chip
select
select
select
select
area
area
area
area
These settings control the EAS[5:0] registers (2.2.6). Here are the default settings shown.
3.1.9 Automatic Port Enable
The start.asm code of our template project sets automatically the corresponding port input
enable registers for the data and control lines. Its code depends on the used device and
data bus width.
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EXTERNAL BUS INTERFACE
Chapter 3 Initialization in Start.asm
The device should be defined by SERIES.
;====================================================================
; 4.1 Controller Series
;====================================================================
#set
MB96320
0
#set
MB96340
1
#set
MB96350
2
#set
MB96360
3
#set
MB96380
4
#set
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
SERIES
MB96380
; <<< select Series
if SERIES == MB96340 || SERIES == MB96350
MOV PIER00,#0xFF
if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG
(CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG
(CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG
MOV PIER01,#0xFF
endif
if HOLD_REQ == ON
SETB PIER03:4
endif
if EXT_READY == ON
SETB PIER03:6
endif
else if SERIES == MB96380
MOV PIER01,#0xFF
if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG
(CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG
(CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG
MOV PIER02,#0xFF
endif
if HOLD_REQ == ON
SETB PIER12:7
endif
if EXT_READY == ON
SETB PIER00:2
endif
endif
& 0x0080) == 0 ||
& 0x0080) == 0 ||
& 0x0080) == 0
& 0x0080) == 0 ||
& 0x0080) == 0 ||
& 0x0080) == 0
Note, that the MB96310 series does not have the External Bus Interface feature.
Important Note:
Please also see the caution remarks given in chapter 5.2.
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EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
4 External Bus Interface Examples
EXAMPLES FOR THE EXTERNAL BUS INTERFACE
4.1
Hardware Example for Multiplex Mode
The following example schematic shows a possible address decoding of the multiplexed bus
for external memory.
Figure 4-1: Memory Interface Example Schematic
Please note, that in this example a 16 bit wide data bus is used. To de multiplex address and
data line 2- 8bit latches (CD74AC573) are used. Address latch enable (ALE) is used to latch
the address and connected to Address bus of Flash and RAM chip.
Flash chip MBM29DL640E is configured for 16-bit data bus with the help of jumper JP49 and
JP52. Similarly RAM chip TC55VBM416 is configured for 16-bit data bus with the help of
jumper JP50 and JP53. BYTEX pin selects byte (8-bit) mode or word (16-bit) mode for the
device. When this pin is driven high, the device operates in word (16-bit) mode. When this
pin is driven low, the device operates in byte (8-bit) mode.
As can be seen from above diagram, CSX3 is used for MBM29DL640E and CSX4 is used
for TC55VBM416.
Some external memories may also need the UBX and LBX signal.
The basic configuration for this example is EACL_STS = 0 and EACL_ACE = 0.
© Fujitsu Microelectronics Europe GmbH
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EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
4.2
Hardware Example for Non Multiplexed Mode
Figure 4-2: Lime Graphic Design Controller interfaced with Non-multiplex Address/Data bus
Above block diagram shows connection between MCU and Lime GDC MB86276. Here Lime
GDC is interfaced on Non-multiplexed address and Data bus.
In the above example, higher order address line, LIME_A21 to LIME_A23, of Lime GDC is
driven by PORT08. Lime GDC is used in 16bit mode (MODE2:0 = B’100) and hence MCU
address line A0 to A19 is connected to LIME_A1 to LIME_A20.
MCU data line AD0 to AD15 is connected to LIME_D0 to LIME_D15.
CSX3 of MCU is connected to LIME_CS. WRLX, WRHX and RDX of MCU is connected to
LIME_XWE0, LIME_XWE1 and LIME_RD respectively.
LIME_RDY signal is connected to MCU RDY, hence MCU wait for ready signal to go active
before writing or reading data from Lime GDC. LIME_RDYSW and LIME_RDY_MODE,
select active level of LIME_RDY output signal.
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EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
4.3
Hardware Example for Chip Select using external address decoder
Assume that a 16K word E2PROM with a starting address of 0x600000 and a 16K word
SRAM with starting address of 0x700000 need to be connected to MCU using external
bus interface
Accordingly E2PROM will have memory space starting from 0x600000 to 0x607FFF
6
0
0 TO 7
0 TO F
0 TO F
A8
A7
A6
A5
0 TO F
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A4
A3
A2
A1
A0
0
1
1
0
0
0
0
0
0
X
X
X
X
X
X X X X X X X X X X
And RAM will have memory space starting from 0x700000 to 0x707FFF
7
0
0 TO 7
0 TO F
0 TO F
A8
A7
A6
A5
0 TO F
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A4
A3
A2
A1
0
1
1
1
0
0
0
0
0
X
X
X
X
X
X X X X X X X X X X
For the same, Decoder logic can be implemented as shown below
Figure 4-3: Decoder logic
Here, ROMSELX Dx to DY and RAMSELX Dx to DY should be connected to Chip select of
respective E2PROM and RAM chips.
4.4
Software Example an External Data Section Declaration
Assume the External Bus Interface is set like described in 3 in the Start.asm file, the
following further definitions have to be done. Assume further, that an external FLASH is
connected.
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A0
EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
4.4.1 Linker Settings
For an external Flash area of 4 M Bytes beginning at address 0x400000, the following linker
settings have to be added:
-ra _EXT_FLASH=0x400000/0x7FFFFF
-sc EXT_FLASH/Data/WORD=_EXT_FLASH
This setting can also be added by the Softune menu Project Q Setup Project Q Linker Q
Disposition/Connection Q Set and … Q Set Section Q Specify in Address.
The –ra option is to define the memory space and the –sc option is to define the section
name. Please note, that WORD alignment should be used if the external Flash has a 16 bit
wide bus.
4.4.2 External Memory Variable Declaration
Add the following code to your project to define variables, which should be linked to the
external RAM memory.
. . .
#pragma segment FAR_DATA=EXT_FLASH, attr=DATA
__far unsigned int ext_variable;
#pragma segment FAR_DATA
. . .
ext_variable is now linked to 0x800000, if no other previous modules define external
FLASH variables. Outside the two #pragma segment directives all other variables are
linked to the default data section DATA, if not other defined in the linker settings.
After project built the external area can be found in the *.mp1 file of the project:
. . .
00400000-00400001
00000002
DATA
P RW-- 02 REL
EXT_FLASH
. . .
4.5
Software Example to Write and Read data from flash
Assume the External Bus Interface and the section declaration are set like described in
Section 3 and 4.3 respectively. Further assum that target board SK-96380-120PMT with
external flash connected to MCU in multiplexed 16-bit mode is used.
On target board since Flash pin A0 is conncected to latch output pin A1, all address output
from MCU are shifted 1 bit right before sending on a Multiplexed address bus. In section
3.1.8 change default setting of CS3_START to 0x00
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EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
Main.c
In main.c file there are two functions Chiperase() and flashwrite(). As the name
suggest Chip erase function erases the chip and flashwrite function writes particular data at
particular address location in external flash.
In main function, program first erases the external Flash chip. It writes random data in some
memory location in external Flash and reads it back. If read data is different than written data
then an error is indicated by outputting fixed bit pattern at PORT09
#define DQ7 0x0080
#define DQ5 0x0020
#define HEX
#define DEC
0
1
#define seq555 (__far unsigned int*)0x100AAA
#define seq2AA (__far unsigned int*)0x100554
#define start_adr (__far unsigned int*)0x100000
// shifted x555
// shifted x2AA
#include "mb96348rs.h"
#pragma segment FAR_DATA=EXT_FLASH, attr=DATA
__far char dummy;
#pragma segment FAR_DATA
unsigned char *byte_ptr1, *byte_ptr2;
// ===========================================
//
ATTENTION! CHIP ERASE TAKES ABOUT 1 MINUTE!
//
===========================================
void chiperase(void)
{
unsigned char flag = 0;
*seq555
*seq2AA
*seq555
*seq555
*seq2AA
*seq555
=
=
=
=
=
=
0x00AA;
0x0055;
0x0080;
0x00AA;
0x0055;
0x0010;
while(flag == 0)
{
if((*start_adr & DQ7) == DQ7) /* Toggle bit */
{
flag = 1;
/* successful erased */
}
}
}
else if((*start_adr & DQ5) ==
{
if((*start_adr & DQ7)
{
flag = 1;
}
else
{
flag = 2;
}
}
© Fujitsu Microelectronics Europe GmbH
DQ5)
/* time out */
== DQ7)
/* successful erased */
/* timeout error */
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EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
void flashwrite(__far unsigned int *adr, unsigned int wdata)
{
unsigned char flag = 0;
*seq555 = 0x00AA;
*seq2AA = 0x0055;
*seq555 = 0x00A0;
*adr = wdata;
while(flag == 0)
{
if((*(__far unsigned int*)adr & DQ7) == DQ7) /* Toggle bit */
{
flag = 1;
/* successful erased */
}
else if((*(__far unsigned int*)adr & DQ5) == DQ5)
/* time out */
{
if((*(__far unsigned int*)adr & DQ7) == DQ7)
{
flag = 1;
/* successful erased */
flag = 2;
/* timeout error */
}
else
{
}
}
}
}
void wait(unsigned int a)
{
unsigned int i;
for (i = 0; i < a; i++)
{
__wait_nop();
}
}
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EXTERNAL BUS INTERFACE
Chapter 4 External Bus Interface Examples
void main(void)
{
unsigned int rnd, err;
unsigned long i;
InitIrqLevels();
__set_il(7);
/* allow all levels
*/
__EI();
/* global enable interrupts */
DDR09 = 0xFF;
PDR09 = 0x00;
chiperase();
// Takes about 1 Minute!
rnd = 0x56B1;
// Random seed
for (i = 0x100000; i < 0x800000; i += 2)
{
flashwrite((__far unsigned int*)i, rnd);
rnd = ((rnd * 13) >> 2) ^ 0x8A27 + (0xFFFF & i);
// pseudo pseudo random
}
err = 0;
rnd = 0x56B1;
// Random seed
for (i = 0x100000; i < 0x800000; i += 2)
{
if ((*(__far unsigned int*)i) != rnd)
err = 1;
rnd = ((rnd * 13) >> 2) ^ 0x8A27 + (0xFFFF & i);
// pseudo pseudo random
}
if (err == 0)
{
PDR09 = 0xAA;
}
else
{
PDR09 = 0x01;
}
while(1);
}
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EXTERNAL BUS INTERFACE
Chapter 5 External Vector Modes
5 External Vector Modes
RECOMMENDATIONS AND CAUTIONS WHEN USING EXTERNAL VECTOR MODES
5.1
External Boot Vector
The External Bus Interface allows to use external ROM memory for reset vector fetch and
code execution after power-on.
These external boot modes are announced to the MCU via the mode pins. There are 3
different external vector fetch modes:
MD2
0
0
1
5.2
MD1
0
0
1
MD0
0
1
0
External Vector Mode
Mode 0: 8-Bit mulitplexed
Mode 1: 16-Bit multiplexed
Mode 2: 8-Bit non-multiplexed
Software Recommendations and Cautions
The external bus modes can be selected in the Start.asm code.
;====================================================================
; 4.10 External Bus Interface
;====================================================================
#set
#set
#set
SINGLE_CHIP
INTROM_EXTBUS
EXTROM_EXTBUS
0
1
2
; all internal
; mask ROM or FLASH memory used
; full external bus (INROM not used)
#set
BUSMODE EXTROM_EXTBUS
; <<< set bus mode (see mode pins)
#set
#set
MULTIPLEXED
0
NON_MULTIPLEXED 1
;
; only if supported by the device
#set
ADDRESSMODE MULTIPLEXED
; <<< set address-mode
; Some devices support multiplexed and/or non-multiplexed Bus mode
; please refer to the related datasheet/hardwaremanual
5.2.1 Mode Byte
To denote to the Boot ROM, which chip select should be used from power-on cycle on, the
so-called Mode Byte is used, which is located just behind the reset vector in the external
memory.
The Boot ROM code first fetches the reset vector from the external memory and then the
Mode Byte. This Mode Byte has the identical value as the External Bus Mode Register
(EBM) described in chapter 2.2.1. It sets the corresponding chip select pins, for the case that
e. g. external RAM is used by the start code.
Caution!
Always enable Chip Select 5*, external bus mode, and multiplexed/non-multiplexed bus
in the standard Start.asm code! Please also use Start.asm revision S 1.59!
* for MB96380 series use chip select 4 when 8-Bit non-multiplexed mode is chosen.
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EXTERNAL BUS INTERFACE
Chapter 5 External Vector Modes
The Mode Byte is defined in the Start.asm code as follows:
.SECTION
RESVECT,
.DATA.E _start
.DATA.B ((ADDRESSMODE <<
(CHIP_SELECT5 <<
(CHIP_SELECT3 <<
(CHIP_SELECT1 <<
CONST, LOCATE=H'FFFFDC
7)
5)
3)
1)
| ((BUSMODE >> 1) << 6) |
| (CHIP_SELECT4 << 4) |
| (CHIP_SELECT2 << 2) |
| CHIP_SELECT0)
5.2.2 Chip Select Configuration Order in Start Code
The order of setting the chip select start bank and the chip select size is very important for
the chip select which is used for external code fetch.
Caution!
Always set the chip select start bank before the chip select size is changed to avoid malfunction of
exteral code fetch!
The Boot Code uses the initial values of the chip select 5 (4 Mbytes) and corresponding start
bank (0xC0).
If the start code modifies the size for the chip select (because a smaller external ROM
device is used) before setting the new start bank, it may happen, that the fetched code area
is immediately outside of the chip select bank, and code execution fails.
Example for Size is changed before Start Bank (Bad Case):
0xFF.FFFF
PC
0xFF.FFFF
PC
0xF0.0000
Chip
Select
5 area
0xF0.0000
4 MBytes
0xCF.FFFF
Chip
Select
5 area
0xC0.0000
After Boot Code: Size is 4 MBytes default
and Start Bank is 0xC0 default.
© Fujitsu Microelectronics Europe GmbH
0xCF.FFFF
1 MByte
0xC0.0000
After changing size to 1 MByte: Start Bank
is still 0xC0, but the current Program
Counter is outside the Chip Select Area .
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EXTERNAL BUS INTERFACE
Chapter 5 External Vector Modes
Example for Start Bank is changed before Size (Good Case):
0xFF.FFFF
PC
PC
0xF0.0000
Chip
Select
5 area
Chip
Select
5 area
0xFF.FFFF
4 MByte
0xF0.0000
4 MBytes
0xCF.FFFF
0xCF.FFFF
0xC0.0000
0xC0.0000
After changing Start Bank to 0xF0, the
current Program Counter is still inside the
new Chip Select Area. Afterwards the size
can be set down to 1 MByte.
After Boot Code: Size is 4 MBytes default
and Start Bank is 0xC0 default.
Please check the configuration order in your used Start.asm code. It should be like:
. . .
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOV
EBCF, #((HOLD_REQ << 7) | (EXT_READY << 6) |
(EXT_CLOCK_ENABLE << 5) | (EXT_CLOCK_INVERT << 4) |
(EXT_CLOCK_SUSPEND << 3) | EXT_CLOCK_DIVISION)
EBAE0,#ADDR_PINS_7_0
EBAE1,#ADDR_PINS_15_8
EBAE2,#ADDR_PINS_23_16
EBCS, #((ADDRESS_STROBE_LVL << 6) | (ADDRESS_STROBE
<< 5) | (READ_STROBE << 4) | (HIGH_WRITE_STROBE << 3)
| (LOW_WRITE_STROBE << 2) | (HIGH_BYTE_SIGNAL << 1) |
LOW_BYTE_SIGNAL)
EAS2, #CS2_START
EAS3, #CS3_START
EAS4, #CS4_START
CSn_START must be set
EAS5, #CS5_START
before CSn_CONFIG!
EACL0,#CS0_CONFIG
EACL1,#CS1_CONFIG
EACL2,#CS2_CONFIG
EACL3,#CS3_CONFIG
EACL4,#CS4_CONFIG
EACL5,#CS5_CONFIG
EBM, #((ADDRESSMODE << 7) | ((BUSMODE-1) << 6) |
(CHIP_SELECT5 << 5) | (CHIP_SELECT4 << 4) |
(CHIP_SELECT3 << 3) | (CHIP_SELECT2 << 2) |
(CHIP_SELECT1 << 1) | CHIP_SELECT0)
. . .
Start.asm revisions S 1.59 are taking care of the correct order.
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EXTERNAL BUS INTERFACE
Chapter 6 Timing Analysis
6 Timing Analysis
6.1
Flash Read AC characteristics
Figure 4-2 below shows timing diagram of Flash read cycle.
Figure 6-1: Flash read timing diagram
Unit
Value
Parameter
Symbol
80
90
Min
Max
Min
12
Max
Min
Max
Read Cycle Time
tRC
80
-
90
120
ns
Address to Output Delay
tAA
-
80
-
90
-
120
ns
Chip Enable to Output Delay
tCE
-
80
-
90
-
120
ns
Output Enable to Output Delay
tOE
-
30
-
35
-
50
ns
Chip Enable to Output High-Z
tDF
-
25
-
30
-
30
ns
Output Enable to Output High-Z
tDF
-
25
-
30
-
30
ns
Output Hold Time From
Addresses, CEX or OEX,
whichever Occurs First
tOH
0
-
0
-
0
-
ns
Table 6-1: Flash read characteristics
Here, tAA, defines the maximum time after the address stabilizes that the Flash will return
valid data. This parameter is commonly referred to as the ‘access time’ of the device.
Similarly, tCE defines the maximum time after the CEX input is asserted that the Flash will
return data. This spec is typically, though not always, the same as tAA. tOE defines the
maximum time from OEX assertion to valid data output much like tCE. tOH indicates the
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EXTERNAL BUS INTERFACE
Chapter 6 Timing Analysis
minimum time the data is guaranteed to remain valid after CEX/OEX de assertion. tDF,
defines the maximum time after which the output is guaranteed to completely float
6.2
RAM Read and Write AC characteristics
Figure 6-2: RAM read timing diagram
Unit
Value
Parameter
Symbol
70
55
Min
Max
Min
Max
Read Cycle Time
tRC
70
-
55
-
ns
Address Access Time
tACC
-
70
-
55
ns
Chip Enable Access Time
tCE
-
70
-
55
ns
Output Enable Access Time
tOE
-
35
-
30
ns
Chip Enable Low to Output Active
tCLZ
5
-
5
-
ns
Output Enable Low to Output
Active
tOLZ
0
-
0
-
ns
Chip Enable High to Output High-Z
tCHZ
-
30
-
25
ns
Output Enable High to Output
High-Z
tOHZ
-
30
-
25
ns
Output Data Hold Time
tOH
10
-
10
-
ns
Table 6-2: RAM read characteristics
Figure 5-2 shows the read cycle timing for a RAM which is quite similar to that of a Flash.
Here separate CEX and OEX data float specs (tCHZ, tOHZ) are defined instead of a single tDF.
Since the SRAM (unlike the EPROM/Flash) can be written. It also specifies the other side of
the data float (i.e., enable to output driven) with tCLZ and tOLZ.
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Chapter 6 Timing Analysis
Figure 6-3: RAM write timing diagram
Unit
Value
Parameter
Symbol
70
55
Min
Max
Min
Max
Write Cycle Time
tWC
70
-
55
-
ns
Write Pulse Width
tWP
50
-
40
-
ns
Chip Enable to End of Write
tCW
55
-
45
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Output Enable High to Output
High-Z
tOHZ
-
30
-
25
ns
Data Setup Time
tDS
30
-
25
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Table 6-3: RAM write Characteristics
Figure 5-3 shows the write cycle timing.
Write time (tWP) is defined as the time during which both CEX and WE are asserted.
tWC simply defines the write cycle time which, along with tRC, is the same as the ‘access
time’. tCW and tAW specify the minimum time from valid CEX and address inputs to the end of
the write cycle. tAS defines an address setup to the beginning of the write cycle. tWP simply
specifies the minimum write pulse (the overlap of CEX and WE) width. tWR specifies a
minimum write ‘recovery’ time, essentially an address hold time after the end of write. tDW
and tDH specify the input data setup and hold times relative to the end of write. tOHZ defines
time duration that must be elapsed before a new write cycle begin to allow previous read
data to disappear and to avoid bus contention.
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Chapter 6 Timing Analysis
6.3
MCU Read AC characteristics
Figure 6-4 External Memory Read Cycle
6.4
MCU Write AC characteristics
Figure 6-5 External Memory Write Cycle
Parameter
Valid address to valid data input
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Symbol
tADVDV
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Unit
Value
Condition
Min
Max
EBM:NMS=0 &
EACL:ACE=0
-
3tCYC -55
EBM:NMS=0 &
EACL:ACE=1
-
4tCYC -55
EBM:NMS= 1
-
2tCYC -55
EACL:ACE=0
-
5tCYC /2-55
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EXTERNAL BUS INTERFACE
Chapter 6 Timing Analysis
EACL:ACE=1
EACL:STS=0 &
EACL:ACE=0
EACL:STS=1 &
Valid address to ALE low
tADVLL
EACL:ACE=0
EACL:STS=0 &
EACL:ACE=1
EACL:STS=1 &
EACL:ACE=1
EACL:STS=0
7tCYC /2-55
tCYC/2 - 15
-
tCYC - 15
ns
3tCYC/2 -15
-
2tCYC -15
-
tCYC/2 -15
ALE low to address valid
tLLAX
RDX low to valid data input
tRLDV
-
RDX high to Data hold time
tRHDX
0
CS low to valid Data input
tCLDV
RDX high to input data float
tRHDX
RDX low to address invalid
tRLAX
Address valid to write low
tAVWL
Write low to write high
EACL:STS=1
0
ns
-
ns
ns
EBM:NMS=0 &
EACL:ACE=0
3tCYC /2-15
-
ns
EBM:NMS=0
&EACL:ACE=1
5tCYC /2-15
-
ns
EBM:NMS=1 &
EACL:STS=0
tCYC /2-15
-
ns
EBM:NMS=1
&EACL: STS=1
tCYC-15
-
ns
EACL:ACE=0
tCYC-15
-
ns
EACL:ACE=1
2tCYC -15
-
ns
tCYC-5
EBM:ACE=1 &
EACL:STS=1
tWHLH
ns
ns
tWLWH
WR high to ALE high
3tCYC /2-50
2tCYC-10
other
EBM:ACE &
ns
ns
tCYC-10
EACL:STS
setting
Data valid to WR transition
tDVWH
tCYC-20
ns
Write High to Data Invalid
tWHDX
tCYC /2-15
ns
Detail spec can be found in hardware manual
Table 6-4: MCU characteristics
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Chapter 6 Timing Analysis
6.5
Timing Analysis
Let’s start with the ‘classic’ circuit shown in Figure 4.1 that uses a transparent latch to
demultiplex the address/data bus AD0–15. The latch, in Figure 4.1, is controlled with two
pins – LE (Enable) and OEX (Output Enable).. This is exactly the behaviour called for to
demultiplex the MCU AD0–15 bus with the ALE output from the MCU. Usually, OEX is
simply connected to ground enabling the output at all times.
For calculation let us assume MCU is running at 16 MHz. For 16MHz tCYC is 62.5ns.Further
EACL:STS is set to 0 (Strobe scheme 0) , EBM:NMS is set to 0 (Multiplexed AD) and
EACL:ACE is set to 0 (Address cycle is not extended)
For the latch CD74AC573, following table indicates its AC characteristics.
Characteristics
Symbol
LE pulse width
Value
Min
Max
Unit
tW
4.9
-
ns
Setup time data to LEX
tSU
2
-
ns
Hold time data to LEX
tH
3.7
-
ns
Propagation Delay
tPROP
3.1
10.8
ns
Table 6-5: Latch characteristics
The first step is to confirm the MCU meets the setup and hold times for the chosen latch.
tS < tADVLL (address valid to ALE low) = tCYC/2 - 15 = 16.25ns
tH < tLLAX (address hold after ALE low) = tCYC/2 -15 = 16.25ns
6.5.1 Flash Timing Analysis
The procedure is simply to step through each Flash spec one by one to identify a speed
grade that meets all the relevant MCU timing requirements.
Starting with tAA, it is apparent that address access time for the Flash must be less than the
MCU tADVDV (address to valid data in)
tAA (Flash) < tADVDV (MCU) – tPROP (TTL)
tAA (Flash) < (3tCYC -55) – 10.8 = 121.7ns
According to the Flash spec chart (refer back to Table 5.1), this can be met by either ‘–80’
(80ns) or ‘–90’ Flash.
tOE, should be less than tRLDV (RDX low to valid data in)
tOE(Flash) < tRLDV (MCU)
tOE(Flash) < (3tCYC /2 – 50) = 43.75ns
According to the Flash spec chart (refer back to Table 5.1), this can be met by either ‘–80’
(tOE is 30ns Max) or ‘–90’ ( tOE is 35ns Max) Flash.
The Flash tOH spec is 0ns. On the MCU side, the corresponding spec is tRHDX (RDX high to
Data hold time) which is also 0ns. This spec is also met as per the requirement because
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Chapter 6 Timing Analysis
MCU will see RDX going high before the Flash and also in fact Flash will take some time to
clear its output.
Flash spec tDF specifies how long data will be available on bus after OEX signal is deasserted. Flash should stop driving the data output before MCU put address on multiplexed
address and data line to avoid bus contention.
For that, tDF should be less than tRHLH
tDF(Flash) < tRHLH
tDF(Flash) < (tCYC /2 – 10) = 21.25ns
Unfortunately, ‘-70’ flash with tDF max 25ns can not meet this spec. We need to use faster
flash. However we can use ‘-70’ flash ignoring this problem because this situation will arise
quite rarely. In real life application this problem will be taken care by the processing time
required by application in between two transfers.
6.5.2 RAM Timing Analysis
The process of evaluating SRAM interface is similar to that for the Flash
For a data read, the SRAM tAA is compared with the MCU tADVDV (address to valid data in).
tAA(RAM) < tADVDV(MCU)–tPROP(TTL)
tAA (RAM) < (3tCYC -55) – 10.8 = 121.7ns
This meets specs of either ‘–70’ or ‘–55’ RAM.
tOE, should be less than tRLDV (RDX low to valid data in)
tOE (RAM) < tRLDV (MCU)
tOE(RAM) < (3tCYC /2 – 50) = 43.75ns,
This meets spec of either ‘–70’ (tOE is 35ns Max) or ‘–55’ ( tOE is 30ns Max) RAM.
Flash spec tDF specifies how long data will be available on bus after OEX signal is deasserted. tDF should be sufficient enough so that RAM should stop driving the data output
before MCU put address on multiplexed address and data line to avoid bus contention.
tOHZ(RAM) < tRHLH
tOHZ (RAM) < (tCYC /2 – 10) = 21.25ns
Unfortunately, ‘-55’ RAM with tOHZ max 25ns can not meet this spec. We need to use faster
RAM. However we can use ‘-55’ RAM ignoring this problem because this situation will arise
quite rarely. In real life application this problem will be taken care by the processing time
required by application in between two transfers.
On the other side, it is possible to for RAM to drive data on the multiplex bus before the
address is removed which may cause bus contention. The SRAM will drive the bus with in
0ns (tOLZ) of OEX assertion. It is taken care by MCU spec (tLLRL - tLLAX) which guarantees that
address is off the bus when RDX is asserted.
tLLRL - tLLAX = (tCYC/2 - 15) - (tCYC/2 - 20) = 5ns
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Chapter 6 Timing Analysis
For a data write, the SRAM tAW (address valid to end of write) is compared against the sum
of the MCU tAVWL (address valid to write low) and tWLWH (write low to write high) specs.
Again considering the latch propagation delay..
tAW(RAM) < tAVWL (MCU) + tWLWH (MCU) – tPROP (TTL)
tAW(RAM) < 3tCYC /2-15 + tCYC-5 – 10.8 = 187.95ns
This is met by RAM spec.
The SRAM tAS spec defines the time addresses must be setup prior to the assertion of WE
which is connected to the MCU WR line so...
tAS(RAM) < tAVWL(MCU) – tPROP(TTL)
tAS(RAM) < 3tCYC /2-15 – 10.8 = 68.75ns
This meets RAM spec of tAS = 0ns.
The SRAM write pulse is defined as the overlap of CEX and WE, tWP (write pulse width) is
simply defined by tWLWH
tWP(RAM)
tWP(RAM)
< tWLWH(MCU)
< tCYC-5 = 57.5ns
This can be met by either ‘–70’ (tWP is 50ns Max) or ‘–55’ ( tWP is 40ns Max) RAM.
The SRAM tWR (write recovery) spec defines how long the addresses must be held after the
end of write, which is the end of MCU WR in this design. Since addresses are guaranteed to
remain stable while ALE is low, this becomes tWHLH (RDX or WR high to ALE high)...
tWR(RAM) < tWHLH(MCU)
tWR(RAM) < tCYC-10 = 52.5ns
This meets RAM spec of tWR = 0ns.
As for tDS (data setup to end of write), the corresponding MCU timing is derived by summing
tDVWH (data valid to WR transition) and tWLWH (WR pulse width) so...
tDS(RAM) < tDVWH (MCU)+ tWLWH(MCU)
tDS(RAM) < tCYC-20 + tCYC-5 = 100ns
This can be met by either ‘–70’ (tDS is 30ns Max) or ‘–55’ ( tDS is 25ns Max) RAM.
The SRAM hold spec tDH is simply compared with tWHDX
tDH(RAM) < tWHDX(MCU)
tDH(RAM) < tCYC /2-15 = 16.25ns
This meets RAM spec of tDH = 0ns.
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Chapter 7 Additional Information
7 Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet page:
http://mcu.emea.fujitsu.com/
The software examples related to this application note is:
96380_ext_bus
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
© Fujitsu Microelectronics Europe GmbH
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