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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300210-E-V15
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
INTERRUPTS
APPLICATION NOTE
INTERRUPTS
Revision History
Revision History
Date
2006-06-23
2006-12-28
2007-02-21
2007-08-10
2007-08-15
2008-07-08
Issue
First Version; MWi
V1.1, Reviewed the document and updated with review findings, MPi
V1.2, Updated with re-review findings, MPi
V1.3, restructure application note, add sections for priority, latency, MPi
V1.4, corrected alignment of paragraphs; PHu
V1.5, add information on PIER for NMI, update initialization of NMI; PHu
This document contains 30 pages.
MCU-AN-300210-E-V15
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© Fujitsu Microelectronics Europe GmbH
INTERRUPTS
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© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300210-E-V15
INTERRUPTS
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 6
1.1
Key Features........................................................................................................... 6
2 INTERRUPT TYPES ........................................................................................................ 7
2.1
Available Interrupts/Exceptions ............................................................................... 7
2.1.1
Hardware Interrupts ................................................................................... 7
2.1.2
Software Interrupts .................................................................................... 7
2.1.3
Hardware Exceptions................................................................................. 7
2.1.4
2.1.3.1
NMI............................................................................................ 7
2.1.3.2
HW-INT9 (Embedded Debug Support)....................................... 7
Software Exceptions .................................................................................. 8
2.1.4.1
Undefined Instruction ................................................................. 8
2.1.4.2
INT9 Instruction ......................................................................... 8
2.2
Direct Memory Access (DMA) ................................................................................. 8
2.3
Interrupt Acceptance, Levels and Modes................................................................. 9
2.4
2.5
2.3.1
User mode ................................................................................................. 9
2.3.2
Priviledged Mode ....................................................................................... 9
Interrupt Latency ................................................................................................... 12
2.4.1
Context Saving / Restoring ...................................................................... 12
2.4.2
Interrupt Deferring Instructions / Prefix Codes ......................................... 12
Registers............................................................................................................... 13
2.5.1
Processor Status (PS).............................................................................. 13
2.5.1.1
Interrupt Level Mask (ILM)....................................................... 13
2.5.1.2
Condition Code Register (CCR) ................................................ 14
2.5.2
Interrupt Vector Table Base Register (TBR) ............................................. 15
2.5.3
Interrupt Vector Table .............................................................................. 15
2.5.4
Interrupt Control Register (ICR) ............................................................... 16
2.5.5
Non Maskable Interrupt (NMI).................................................................. 17
3 INTERRUPT RECOMMENDATIONS AND EXAMPLES ................................................ 18
3.1
Interrupt Vector Definition...................................................................................... 18
3.2
Interrupt Level Predefinition................................................................................... 18
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INTERRUPTS
Contents
3.3
Setting an Interrupt Level ...................................................................................... 19
3.4
Reading an Interrupt Level .................................................................................... 19
3.5
Interrupt Service Routine....................................................................................... 19
3.6
Interrupt Service Routine without Register Saving................................................. 20
3.7
Setting global Interrupt Level ................................................................................. 20
3.8
Enabling and Disabling Interrupts globally ............................................................. 20
3.9
Order of Initialization ............................................................................................. 22
3.10 NMI Initialization .................................................................................................... 23
3.11 NMI Pin Relocation................................................................................................ 23
3.12 Interrupt Vector Relocation.................................................................................... 23
4 ADDITIONAL INFORMATION ....................................................................................... 28
LIST OF TABLES............................................................................................................... 29
LIST OF FIGURES ............................................................................................................. 30
© Fujitsu Microelectronics Europe GmbH
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Chapter 1 Introduction
1 Introduction
This application note describes the functionality of the internal Interrupts and gives some
examples.
1.1
Key Features
•
Each Resource uses one Interrupt (no Channel Sharing)
•
7 Interrupt Priority Levels selectable (7 = Interrupts Disabled)
•
Interrupt Vector Table Relocatable
•
Software and Hardware Interrupts
•
Software and Hardware Exceptions
•
Non-Maskable Interrupt (NMI)
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INTERRUPTS
Chapter 2 Interrupt Types
2 Interrupt Types
THE BASIC FUNCTIONALITY OF INTERNAL INTERRUPTS
2.1
Available Interrupts / Exceptions
There are four different types of Interrupts / exceptions available.
2.1.1 Hardware Interrupts
This kind of Interrupts is generated by internal resources. An Interrupt is generated if the
corresponding Interrupt enable bit of the resource is set, the level of the vector is equal or
less than the global Interrupt level, Interrupts are globally enabled and an Interrupt cause
has occurred. While execution of interrupt service routine (ISR), the System Stack Pointer is
enabled (CCR:S = 1). These interrupts are serviced in user mode only (CCR:P = 1). Interrupt
level of hardware interrupts is configured by IL (Interrupt Level) bits of ICR (Interrupt Control
Register),
2.1.2 Software Interrupts
Software Interrupts can be requested by executing the INT or INTP instructions. This type of
interrupt has no Interrupt level. It also does not have interrupt request or enable flag. While
execution of ISR, global Hardware Interrupts are disabled (CCR:I = 0), hence all the
hardware interrupts are suspended until INT ISR execution has finished. However INT ISR
can be interrupted by hardware exception. The System Stack Pointer is enabled (CCR:S =
1).
2.1.3 Hardware Exceptions
Hardware exceptions are external events which are not maskable by any software
instruction. They are processed like Interrupts. They have their own vectors. The following
hardware exceptions can occur:
2.1.3.1 NMI
NMI provides external hardware exception handling. NMI has a fixed interrupt level unlike
hardware interrupts. It is level P4 i.e. Privileged Mode – Level 4. That means while execution
of NMI ISR, the mode is changed to Privileged Mode (CCR:P = 0) and the interrupt level
mask is configured to 4 (PS:ILM = 4). Hence all interrupts/exceptions are suspended until
NMI ISR execution has finished. System Stack Pointer is enabled (CCR:S = 1). The P flag
and ILM are restored at execution of the RETI instruction. Hence user mode would be
restored if the same mode was active at the time of NMI.
2.1.3.2 HW-INT9 (Embedded Debug Support)
HW-INT9 is used by address match detection function. With that function embedded debug
support (operand address break or data value break) or a simple memory protection can be
provided. HW-INT9 has a fixed interrupt level unlike hardware interrupts. It is level P6 i.e.
Privileged Mode – Level 6. That means while execution of HW-INT9 ISR, the mode is
changed to Privileged Mode (CCR:P = 0) and the interrupt level mask is configured to 6
(PS:ILM = 6). Hence all interrupts / exceptions are suspended until HW-INT9 ISR execution
has finished, except NMI. System Stack Pointer is enabled (CCR:S = 1). The P flag and ILM
are restored at execution of the RETI instruction. Hence user mode would be restored if the
same mode was active at the time of HW-INT9.
For detailed information please refer the Memory Patch application note MCU-AN-300221.
© Fujitsu Microelectronics Europe GmbH
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Chapter 2 Interrupt Types
2.1.4 Software Exceptions
Software exceptions are always accepted. Same as software interrupts, software exceptions
disable any hardware interrupt acceptance. The following software exceptions can occur:
2.1.4.1 Undefined Instruction
All codes that are not defined in the instruction map are handled as undefined instructions.
When an undefined instruction is executed, the ISR whose starting address is stored at
interrupt vector INT 10 is executed. While storing the CPU status, PC value saved in the
stack is the address at which the undefined instruction is stored. While execution of ISR,
global Hardware Interrupts are disabled (CCR:I = 0) hence all the all hardware interrupts
are suspended until undefined instruction ISR execution has finished. However undefined
instruction ISR can be interrupted by hardware exception. The System Stack Pointer is
enabled (CCR:S).
2.1.4.2 INT9 Instruction
INT9 instruction branches to ISR indicated by interrupt vector INT 9. While execution of ISR,
global Hardware Interrupts are disabled (CCR:I = 0) hence all hardware interrupts are
suspended until INT9 ISR execution has finished. However INT9 ISR can be interrupted by
hardware exception. The System Stack Pointer is enabled (CCR:S).
2.2
Direct Memory Access (DMA)
DMA transfers are accepted regardless of the status of the I flag and the interrupt level.
For detailed information please refer to the DMA application note MCU-AN-300220.
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INTERRUPTS
Chapter 2 Interrupt Types
2.3
Interrupt Acceptance, Levels and Modes
2.3.1 User mode
If the P bit of CCR register is set to 1, it indicates “User Mode”. In the user mode the
hardware interrupts are serviced depending on the ILM.
2.3.2 Privileged Mode
If the P bit of CCR register is set to 0, it indicates “Privileged Mode”. This (CCR:P = 0)
happens in the event of hardware exceptions such as NMI and HW-INT9. If the P flag is
cleared, ILM of PS defines system interrupt levels of the privileged mode (P0 to P7). These
interrupt levels always have higher priority than any ILM setting in user mode (U0 to U7).
Hence in the privileged mode all hardware interrupts are suspended. User mode would be
restored after the execution of RETI instruction (in the hardware exception ISR), if the same
mode was active at the time of hardware exception.
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Chapter 2 Interrupt Types
The following table explains various interrupts/exceptions, corresponding levels, acceptance
conditions etc.
Description
Interrupt/
Vector
Number
Hardware
Exception
NMI
Hardware
Exception
Interrupt/
Exception
Interrupt
Level
Acceptance
Condition
INT 11
Always
Fixed,
P4
(Privileged
Mode Level 4)
HW-INT9
INT 9
Always
Fixed,
P6
Current instruction
execution is finished
String instruction is
Interrupted
If ILM (Interrupt Level
Mask) of PS
(Processor Status )
register is greater
than 4 or P (Privileged
Mode) flag of CCR
(Code Condition
Register) is 1
Current instruction
execution is finished
String instruction is
Interrupted
If ILM of PS register is
greater than 6 or P
flag of CCR is 1
Software
Exception
INT9
Instruction
INT 9,
Shared
with HWINT9
Vector
No Level
Always Accepted
Software
Exception
Undefined
Instruction
INT 10
No Level
Always Accepted
Software
Interrupt
INT
Instruction
INT 0 to
255,
As
specified
by
operand
No Level
Always Accepted
Action after Acceptance
Save CPU status to system
stack
S = 1 (use system stack)
P = 0 (Privileged Mode)
ILM = 4 i.e. all
interrupts/exceptions
suspended until NMI ISR
execution
Branch to interrupt vector
Save CPU status to system
stack
S = 1 (use system stack)
P = 0 (Privileged Mode)
ILM = 6 i.e. all
interrupts/exceptions
suspended until HW-INT9 ISR
execution except NMI
Branch to interrupt vector
Save CPU status to system
stack
S = 1 (use system stack)
I = 0 i.e. all hardware
interrupts are suspended until
INT9 ISR execution, INT9 ISR
can be interrupted by
hardware exception
Branch to interrupt vector
Save CPU status to system
stack
S = 1 (use system stack)
I = 0 i.e. all hardware
interrupts are suspended until
Undefined Instruction ISR
execution, Undefined
Instruction ISR can be
interrupted by hardware
exception
Branch to interrupt vector
Save CPU status to system
stack
S = 1 (use system stack)
I = 0 i.e. all hardware
interrupts are suspended until
INT ISR execution, INT ISR
can be interrupted by
hardware exception
Branch to interrupt vector
Table 2-1: Interrupt Acceptance and Levels - I
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INTERRUPTS
Chapter 2 Interrupt Types
Interrupt/
Exception
Description
Vector
Number
Interrupt
Level
Software
Interrupt
INTP
Instruction
24-Bit
physical
address
as
specified
by
operand
No Level
Hardware
Interrupt
Resource /
Peripheral
Interrupt
INT 13
onwards
As configured
by IL
(Interrupt
Level) bits of
ICR (Interrupt
Control
Register),
Between U0
to U7 (User
Mode - Level
0 to 7)
Hardware
Interrupt
Delayed
Interrupt
INT 12
As configured
by IL bits of
ICR,
Between U0
to U7
Acceptance Condition
Action after Acceptance
Always Accepted
Save CPU status to system
stack
S = 1 (use system stack)
I = 0 i.e. all hardware
interrupts are suspended until
INT ISR execution, INT ISR
can be interrupted by
hardware exception
Branch to interrupt vector
Save CPU status to system
stack
S = 1 (use system stack)
ILM = IL i.e. peripheral ISR
can be interrupted by
hardware exception, software
exception, software interrupt
and hardware interrupt with
lower value of IL (i.e. with
higher priority)
Branch to interrupt vector
Current instruction
execution is finished
String instruction is
Interrupted
If ILM of PS register is
greater than IL of the
peripheral and P flag of
CCR is 1 and I flag of
CCR is 1
For multiple requests with
same IL, smallest
interrupt number is
accepted.
Current instruction
execution is finished
String instruction is
Interrupted
If ILM of PS register is
greater than IL of the
peripheral and P flag of
CCR is 1 and I flag of
CCR is 1
No peripheral interrupts
pending with same IL as
of delayed interrupt
Save CPU status to system
stack
S = 1 (use system stack)
ILM = IL i.e. peripheral ISR
can be interrupted by
hardware exception, software
exception, software interrupt
and hardware interrupt with
lower value of IL (i.e. with
higher priority)
Branch to interrupt vector
Table 2-2: Interrupt Acceptance and Levels - II
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INTERRUPTS
Chapter 2 Interrupt Types
2.4
Interrupt Latency
2.4.1 Context Saving / Restoring
Once the interrupt is generated and if it is enabled, “normally” the following series of steps
are performed:
1. CPU finishes current instruction execution.
2. It stores the current status to stack.
3. It fetches the starting address of the ISR from the corresponding interrupt vector.
4. And Branches to the ISR.
Steps 2 to 4 are also termed as “Context Saving”.
Once the ISR execution is finished, while the execution of RETI instruction the following step
is performed:
1. The status is retrieved from the stack.
2. CPU starts executing the code which it was executing at the time of interrupt.
Steps 1 and 2 are also termed as “Context Restoring”.
The time taken for the Context Saving and Context Restoring is dependent on:
Location of Stack (Internal RAM / External RAM)
Location of Interrupt Vector (Internal Flash / External Flash)
Location of Interrupt Service Routine (Internal Flash / External Flash)
Read Wait States in case of internal flash
Address indicated by stack pointer
If we consider that the internal RAM is used for stack, internal Flash is used for vector as
well as routines and internal flash wait state is 0 then the cycles required for context
saving/restoring are:
Address Indicated by Stack Pointer
Cycle Required
Even Numbered Address
Odd Numbered Address
Context Saving
10
12
Context Restoring
9
11
Table 2-3: Cycles Required for Context Saving / Restoring
These timing gets worsened if the stack / interrupt vector / ISRs are located in the external
memory. This is because the wait cycles for external bus transfer get added to the above
mentioned cycles.
2.4.2 Interrupt Deferring Instructions / Prefix Codes
Other than the above mentioned factors interrupt latency is also dependent on the currently
executing instructions or prefix codes. Some of the instructions and all of the prefix codes
defer or delay interrupts during their execution. This means that even if the valid interrupt
arrives while such instructions / prefix code are getting executed, then such (single / series
of) instructions / prefix codes would continue getting executed. After their execution a normal
instruction (which does fall into the interrupt deferring category) would also be executed and
then only the interrupt would be serviced. Such interrupt deferring instructions / prefix codes
are:
MOV ILM, #imm8
PCB
NCC
AND CCR, #imm8
ADB
CMR
OR CCR, #imm8
DTB
POPW PS
SPB
Table 2-4: Interrupt Deferring Instructions / Prefix Codes
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INTERRUPTS
Chapter 2 Interrupt Types
2.5
Registers
2.5.1 Processor Status (PS)
The Processor Status contains three sub sections.
15
…
13
12
…
ILM
8
7
RP
…
0
CCR
Table 2-5: Processor Status
For Interrupts the Interrupt Level Mask (ILM) and the I-Bit of the Condition Code Register
(CCR) are important.
2.5.1.1 Interrupt Level Mask (ILM)
The three bits of the ILM are “0” after reset. Different settings are described in the following
table:
Bit No. 15
ILM2
0
0
0
0
1
1
1
1
Bit No. 14
ILM1
0
0
1
1
0
0
1
1
Bit No. 13
ILM0
0
1
0
1
0
1
0
1
Level value
Levels of accepted Interrupts
0
1
2
3
4
5
6
7
Interrupts disabled
0
1 and below
2 and below
3 and below
4 and below
5 and below
6 and below
Table 2-6: Interrupt Level Mask
The Level can be set in C with the language extension directive __set_il(n), where n is
the level. The machine instruction for this is MOV ILM,#n.
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Chapter 2 Interrupt Types
2.5.1.2 Condition Code Register (CCR)
The CCR consists of the following bits:
Bit
No.
Bit
Name
7
P1
6
I
5
S
4
T
3
2
1
0
N
Z
V
C
Value
after
Boot
Description
ROM
execution
Privileged Mode Flag. This flag is set by Boot-ROM.
1
1 = User Mode, 0 = Privileged Mode*
0
Global Interrupt Enable Flag
System/User Stack Flag. 1 = System Stack, 0 = User Stack.
This bit is set to “1” after execution of INT, INT9 or INTP
1
instruction and also in case of hardware interrupts (before
execution of interrupt service routine).
Sticky Bit Flag. This bit is used by logical/arithmetic right shift
x
operations
x
Negative Flag
x
Zero Flag
x
Overflow Flag
x
Carry Flag
Table 2-7: Condition Code Register
Interrupts can be enabled globally by the C language extension __EI() and disabled by
__DI().
There is no direct bit access to the CCR in assembler, but bits can be set indirectly with
logical instructions: Setting the I-Bit: OR CCR,#40 and clearing it: AND CCR,#BF.
Please note, that __DI() and __EI() cannot be set consecutively. Please set at least one
instruction in-between, such as a NOP.
Wrong
Correct
__DI();
__EI();
__DI();
__wait_nop;
__EI();
__EI();
__DI();
__EI();
__wait_nop();
__DI();
1
This bit remains “1” if it was set to “1” before. It would be cleared only while execution of hardware exception
ISR.
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INTERRUPTS
Chapter 2 Interrupt Types
2.5.2 Interrupt Vector Table Base Register (TBR)
The TBR contains the base address for the Interrupt vector table. It is 16-bit wide, where the
2 least significant Bits are “0”. The upper byte stands for the program bank of the 24-bit
address space.
TBR:
15 14 13 12 11 10
9
8
7
6
5
4
3
2
TBRL
TBRH
1
0
0
0
9
8
Address Space:
23 22 21 20 19 18 17 16
15 14 13 12 11 10
Program Bank
Upper 16-Bit Address
7
6
5
4
3
2
1
0
Lower 16-Bit Address
The Interrupt vector table has a size of 1024 Bytes. So, if the TBR for example has the value
0xAA24 the vector table starts from 0xAA2400 and ends at 0xAA27FF.
2.5.3 Interrupt Vector Table
The Interrupt Vector Table is a set of 256 quadruple Bytes, which contains the 24-bit
Interrupt Service Routine address. The most significant Byte of the quadruple is undefined.
Note, that Reset, INT9, Undefined Instruction, and NMI are also contained in this table.
In general the table is built as follows:
Interrupt
Vector
Number
Vector
Address
INT0
…
INT7
INT8
TB + 0x3FC
…
TB + 0x3E0
TB + 0x3DC
INT9
TB + 0x3D8
INT10
INT11
INT12
INT13
INT14
INT15
INT16
INT17
INT18
INT19
...
INT254
INT255
Index of
Level
Register
in ICR
Hardware Interrupt /
Interrupt Cause
-
-
-
Reset
INT9 Instruction/HWINT9
Undefined Instruction
NMI
Delayed Interrupt
RC Clock Timer
Main Clock Timer
Sub Clock Timer
Reserved
-
0x3D4
0x3D0
0x3CC
IL12
0x3C8
IL13
0x3C4
IL14
0x3C0
IL15
0x3BC
IL16
0x3B8
IL17
0x3B4
IL18
Device specific
0x3B0
IL19
Peripheral Vectors
...
...
TB + 0x004
TB + 0x000
TB = Interrupt Vector Table Base Address
TB
TB
TB
TB
TB
TB
TB
TB
TB
TB
+
+
+
+
+
+
+
+
+
+
Table 2-8: Interrupt Vector Table
Please note that INT0 till INT7 can collide with the vectored call subroutine table, if the
actual program bank (value of PCB) is same as TBRH. Therefore please use CALLV only if
the actual program bank is the same in which the Vectored Call Table is located.
© Fujitsu Microelectronics Europe GmbH
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INTERRUPTS
Chapter 2 Interrupt Types
2.5.4 Interrupt Control Register (ICR)
Using this register interrupt levels of hardware peripheral interrupts can be configured. For
all other vectors ICR:IX contains the vector number and ICR:IL the level. The level of a
vector can be read out via ICR:IL by writing the vector number to ICR:IX.
Bit
No.
15
…
8
7
…
3
2
…
0
Bit
Name
IX7
…
IX0
Initial
Value
0
Index of the Interrupt Level to be accessed
-
X
Undefined Bits
IL2
…
IL0
1
Interrupt Level of Index specified in IX[7:0]
Description
Table 2-9: Interrupt Control Register
To set an Interrupt level please always access ICR via word writing.
For reading out configured interrupt level of a particular hardware peripheral do the following:
Write the corresponding index to the Interrupt Index Register - IDX (same as
IX[7:0] bits of ICR) (essentially a byte-write).
Read out the entire ICR (essentially a word-read).
Confirm that the read back value and the written value of IX[7:0] match and then
IL[2:0] value is considered to be correct.
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Chapter 2 Interrupt Types
2.5.5 Non Maskable Interrupt (NMI)
The NMI is disabled after Reset. Once it is enabled in an application, it cannot be disabled.
Only another Reset can disable this feature.
The NMI has a control register as follows:
Bit
No.
15
…
11
10
Bit
Name
Initial
Value
-
X
Undefined Bits
LEV
1
9
EN
0
8
FLAG
X
Level Bit. 1 = NMI Pin high active, 0 = NMI Pin low active.
Enable Bit. Writing “1” enables NMI feature until Reset. Writing
“0” has no effect. Write “0” to FLAG before enabling NMI. Also
set the correct level using the LEV bit before enabling NMI.
NMI Flag. 1 = NMI occurred. Writing “0” clears Flag. Write “0” to
this Bit before enabling NMI.
Description
Table 2-10: Non Maskable Interrupt
The Non Maskable Interrupt functionality is available on either of two pins: NMI and NMI_R.
The bit 1 NMI_R of Peripheral resource relocation register 7 configures the same. If this bit is
0 then Pin NMI is used as Non Maskable input pin and if this bit is 1 then Pin NMI_R is used
as Non Maskable input pin. The relocation cannot be changed after the NMI is enabled.
Note that the corresponding Port Input Enable Register (PIER) has to be set also.
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Chapter 3 Interrupt Recommendations and Examples
3 Interrupt Recommendations and Examples
RECOMMENDATIONS AND EXAMPLES FOR THE INTERRUPT USAGE
3.1
Interrupt Vector Definition
By using the #pragma intvect directive, an interrupt vector is defined. It is recommended
to use our standard template project, which contains a file called vectors.c which performs all
interrupt settings. The user may use or copy and modify this file for own projects.
Please make sure to always define the complete interrupt vector table in just one C module
and do not split it.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
#pragma
#pragma
#pragma
#pragma
#pragma
#pragma
#pragma
#pragma
intvect
intvect
intvect
intvect
intvect
intvect
intvect
intvect
My_IRQHandler_1
DefaultIRQHandler
My_IRQHandler_2
My_IRQHandler_3
DefaultIRQHandler
My_IRQHandler_4
My_IRQHandler_5
My_IRQHandler_6
12
13
14
15
16
17
18
19
/*
/*
/*
/*
/*
/*
/*
/*
Delayed Interrupt
RC Clock Timer
Main Clock Timer
Sub Clock Timer
Reserved
EXT0
EXT1
EXT2
*/
*/
*/
*/
*/
*/
*/
*/
. . .
Please note, that if the Interrupt service functions are located in a different C module, their
prototypes have to be defined also for the vector definition.
3.2
Interrupt Level Predefinition
It is possible to predefine all interrupt levels with a default level by a loop. The following code
shows how to do this.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
#define MIN_ICR
#define MAX_ICR
12
120
/* Interrupts with levels begin here
*/
/* Device specific Interrupt Level end */
#define DEFAULT_ILM_MASK 7
void InitIrqLevels(void)
{
unsigned char irq;
}
for (irq = MIN_ICR; irq <= MAX_ICR; irq++)
{
ICR = (irq << 8) | DEFAULT_ILM_MASK;
}
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Chapter 3 Interrupt Recommendations and Examples
3.3
Setting an Interrupt Level
Assume you want to assign the level 2 to the interrupt vector 12. With the following formula,
the correct word is already calculated by the pre-processor.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitIrqLevels(void)
{
ICR = (12 << 8) | 2;
}
3.4
Reading an Interrupt Level
If the currently configured level of the peripheral whose vector number is 12 can be read as
below:
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
unsigned int icr;
unsigned char idx;
void readIrqLevel(void)
{
IDX = 12;
icr = ICR;
idx = (unsigned char)(icr >> 8);
if (idx == 12)
{
/* IL[2:0] is correct level of interrupt whose vector is 12 */
}
}
3.5
Interrupt Service Routine
The type qualifier __interrupt shows the complier, that by entering the following function
several registers have to be saved and the function has to be finished with the RETI
instruction. This function is always of the type of void and has no arguments.
Please note, that the Interrupt cause bit always has to be cleared in the service routine;
otherwise the service routine will be entered again after execution. Most of the resources
have a special Interrupt clear bit, but some have an auto-clear by accessing a special
register (e. g. UART read buffer).
The following code shows a typical Interrupt service routine.
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Chapter 3 Interrupt Recommendations and Examples
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
__interrupt void My_Interrupt_Service_Routine_1(void)
{
Resource_Interrupt_Clear_Bit = 0;
/* clear Interrupt cause */
/* do something here */
}
3.6
Interrupt Service Routine without Register Saving
If the Interrupt service routine does not use any variables and just accesses some resource
registers, it is not needed to save any registers before entering the service routine and
restoring them at the end. The type qualifier __nosavereg signalizes this to the compiler. It
should stand before the __interrupt type qualifier.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
__nosavereg __interrupt void My_Interrupt_Service_Routine_2(void)
{
Resource_Interrupt_Clear_Bit = 0;
/* clear Interrupt cause */
/* only access to resource registers here */
/* no variables allowed to use here
*/
}
3.7
Setting global Interrupt Level
To set the global Interrupt Level via the ILM register, the language extension __set_il(n)
exists, where n is the global level. Please also see 2.5.1.1.
Assume the level 3 is desired. The following code shows how to access the ILM register
from C code.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
__set_il(3);
3.8
Enabling and Disabling Interrupts globally
To enable Interrupts globally use the __EI() language extension. __DI() disables
Interrupts globally. Both extensions access the I-Bit in the Condition Code Register.
Please also see 2.5.1.2.
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Chapter 3 Interrupt Recommendations and Examples
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
. . .
__EI();
/* Enable Interrupts globally */
. . .
__DI();
/* Disable Interrupts globally */
. . .
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Chapter 3 Interrupt Recommendations and Examples
3.9
Order of Initialization
For the Interrupt initialization the order of the steps has to be done like in the following
example code.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
#define MIN_ICR
#define MAX_ICR
12
120
/* Interrupts with levels begin here
*/
/* Device specific Interrupt Level end */
#define DEFAULT_ILM_MASK 7
void InitIrqLevels(void)
{
unsigned char irq;
for (irq = MIN_ICR; irq <= MAX_ICR; irq++)
{
ICR = (irq << 8) | DEFAULT_ILM_MASK;
}
ICR = (12 << 8) | 2;
ICR = (13 << 8) | 3;
/* Example: ICR10 has level 2 */
/* Example: ICR11 has level 3 */
}
. . .
void main(void)
{
InitIrqLevels();
__set_il(7);
__EI();
/* First initialize all Interrupt Levels */
/* Set global Interrupt Level to 7
*/
/* Enable Interrupt globally
*/
. . .
}
Note, that in this example only the initialization flow is shown. Neither the vector definition
nor the Interrupt service routines are shown here.
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Chapter 3 Interrupt Recommendations and Examples
3.10 NMI Initialization
Because the FLAG-Bit of the NMI register is undefined after power-on, it has to be set to “0”
before enabling the NMI feature. The following code gives an example to do the NMI
initialization on MB96340 Series. Note that also the Port Input Enable Register (PIER) needs
to be enabled.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void Init_NMI(void)
{
PIER07_IE0 = 1;
NMI_LEV = 1;
NMI_FLAG = 0;
NMI_EN = 1;
}
/*
/*
/*
/*
P07_0 input enable for NMI of MB9634x series
1 = high active, 0 = low active
Clear NMI cause flag prophylactic
NMI now enabled, disable only by reset
*/
*/
*/
*/
3.11 NMI Pin Relocation
The Non Maskable Interrupt functionality is available on either of two pins: NMI and NMI_R.
The following example shows how to configure NMI_R pin as an input pin instead of NMI pin
on MB96340 Series. Note that also the Port Input Enable Register (PIER) needs to be
enabled.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void Relocate_NMI(void)
{
PIER05_IE5 = 1;
PRRR7_NMI_R = 1;
}
/* P05_5 input enable for NMI_R of MB9634x series */
/* Pin NMI_R is used as input pin
*/
3.12 Interrupt Vector Relocation
As discussed in the section 2.5.2, the interrupt vector table can be relocated to any memory
location in steps of 1 KB using the TBR.
This may be required when the original vector table is inaccessible at some point of time and
still the interrupts need to be serviced. Such need may arise in an application when some
sector of the Main Flash needs to be erased or programmed and while it is happening, some
interrupts such as CAN receive or UART receive interrupts need to be attended.
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Chapter 3 Interrupt Recommendations and Examples
The following are the preconditions for the relocation discussed above for MB96340 Series:
1. The entire application including the interrupt vector is available in the Main Flash.
2. The space equivalent to the entire vector table or the required vectors is reserved in the
memory other than Main Flash. It can be Satellite Flash or RAM. For ease of
understanding, we would consider that space in RAM would be reserved for the required
vectors.
a. The below code indicates that space for relocated CAN0 vector is reserved at
RAM address 0x007F78 (vector number 33, offset from TBR = 0x378) and
space for relocated UART0-RX vector is reserved at the RAM address
0x007EC0 (vector number 33, offset from TBR = 0x2C0). This is considering
later the vector table is relocated to RAM starting from address 0x7C00.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
#pragma segment DATA=INTVECT2_CAN,locate=0x007F78
__interrupt void (*CAN0_ptr)(void);
#pragma segment DATA=DATA
#pragma segment DATA=INTVECT2_UART,locate=0x007EC0
__interrupt void (*UART0_RX_ptr)(void);
#pragma segment DATA=DATA
3. The routine or the function which actually erases / programs the sector of the flash
should be available in the memory other than the Main Flash. It can be Satellite Flash or
RAM. For ease of understanding, we would consider that the routine is mapped to RAM.
a. In order to achieve the above, RAMCODE section needs to be defined as below:
Figure 3-1: CONST Section Setting
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INTERRUPTS
Chapter 3 Interrupt Recommendations and Examples
The RAM and the Flash area reserved would be dependent on the particular
processor which the application uses.
The above dialog box can be reached as mentioned below…
Project -> Setup Project -> Linker -> Disposition Connection -> Set Section
b. In order to link the function EraseSector() to RAM, the #pragma section
directive needs to be used as follows:
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
#pragma section FAR_CODE=RAMCODE
unsigned char EraseSector (int sec_num)
{
. . .
}
. . .
4. The interrupt service routines those have to be accessed while the sector of Main Flash
is erased are also mapped to RAM. We consider that CAN0 and UART0 Receive
interrupt needs to be serviced.
a. The following codes give the interrupt level and vector configuration.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitIrqLevels(void)
{
ICR = (33 << 8) | 2;
// CAN 0 of MB9634x Series
ICR = (79 << 8) | 3;
// UART-RX 0 of MB9634x Series
}
. . .
__interrupt void CAN0_ISR(void);
__interrupt void UART0_Rx_ISR(void);
// Prototype
// Prototype
. . .
#pragma intvect CAN0_ISR
#pragma intvect UART0_Rx_ISR
33
79
© Fujitsu Microelectronics Europe GmbH
// CAN 0 of MB9634x Series
// UART-RX 0 of MB9634x Series
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Chapter 3 Interrupt Recommendations and Examples
b. The following code links the ISRs to RAM.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
#pragma section FAR_CODE=RAMCODE
__interrupt
void CAN0_ISR (void)
{
. . .
. . .
}
__interrupt
void UART0_Rx_ISR (void)
{
. . .
}
. . .
5. The Memory Model for the project should be selected as “Large”.
Figure 3-2: Memory Model Setting
The above dialog box can be reached as mentioned below…
Project -> Setup Project -> C Compiler -> Category -> Target Depend -> Memory Model
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Chapter 3 Interrupt Recommendations and Examples
Once the above preconditions are met then the actual relocation would be carried out in the
following steps for MB96340 Series:
1. Copy the starting address of CAN0 ISR to relocated CAN0 vector in RAM as reserved in
preconditions step 2 above.
2. Copy the starting address of UART0 Receive ISR to relocated UART0 Receive vector in
RAM as reserved in preconditions step 2 above.
3. Store the original TBR settings.
4. Configure the TBR to the new value value.
5. Call the function which erases the sector of Main Flash.
6. Restore the original TBR value.
The below code demonstrates the actual relocation of vector table.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void Main(void)
{
unsigned int tbr;
InitIrqLevels();
__set_il(7);
__EI();
/* First initialize all Interrupt Levels */
/* Set global Interrupt Level to 7
*/
/* Enable Interrupt globally
*/
. . .
CAN0_ptr = CAN0_ISR;
/* Store CAN0 ISR address to relocated vector */
UART0_ptr = UART0_Rx_ISR;/* Store UART0-Rx ISR address to relocated vector
*/
tbr = TBR;
TBR = 0x007C;
}
/* Save original TBR */
EraseSector(0xF0);
/* Configure TBR to point to vector table in
RAM at the base address 0x7C00 */
/* Erase Falsh sector 0xF0 */
TBR = tbr;
/* Restore original TBR value */
. . .
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Chapter 4 Additional Information
4 Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet page:
http://mcu.emea.fujitsu.com/
The software example related to this application note is:
96340_intvect
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
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List of Tables
List of Tables
Table 2-1: Interrupt Acceptance and Levels - I ..................................................................... 10
Table 2-2: Interrupt Acceptance and Levels - II .................................................................... 11
Table 2-3: Cycles Required for Context Saving / Restoring.................................................. 12
Table 2-4: Interrupt Deferring Instructions / Prefix Codes..................................................... 12
Table 2-5: Processor Status................................................................................................. 13
Table 2-6: Interrupt Level Mask............................................................................................ 13
Table 2-7: Condition Code Register ..................................................................................... 14
Table 2-8: Interrupt Vector Table ......................................................................................... 15
Table 2-9: Interrupt Control Register .................................................................................... 16
Table 2-10: Non Maskable Interrupt ..................................................................................... 17
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List of Figures
List of Figures
Figure 3-2: CONST Section Setting ..................................................................................... 24
Figure 3-1: Memory Model Setting ....................................................................................... 26
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