S25FL1-K Power-Up Timing Reset

AN99199
S25FL1-K SPI Power-Up Timing and Reset
AN99199 discusses the considerations for ensuring strict adherence to Power-Up Timing and Voltage Levels specified in the
data sheet for Cypress S25FL1-K SPI Multi-I/O Flash Memory family devices.
1
Introduction
The S25FL1-K Serial Peripheral Interface (SPI) Multi-I/O Flash Memory family requires strict adherence to PowerUp Timing and Voltage Levels specified in the data sheet.
2
Power-On (Cold) Reset
S25FL1-K devices execute a Power-On Reset (POR) process until a time delay of tPUW has elapsed after the
moment that VCC rises above the VWI threshold as shown in Figure 1. The device must not be selected until after
tVSL since Chip Select (CS#) must to go high with VCC, i.e. no commands may be sent to the device until the end
of tVSL. Program, Erase, and Write instructions will be ignored until after tPUW. Power-Up Timing and Voltage
Level parameters are shown in Table 1. CS# should not be held low during the POR.
Figure 1. Power-Up Timing and Voltage Levels
VCC
VCC (max)
Program, Erase, and Write instructions are ignored
CS# must track VCC
VCC (min)
t VSL
Reset
State
Read instructions
allowed
Device is fully
accessible
VWI
t PUW
Time
Table 1. Power-Up Timing and Voltage Levels
Parameter
Symbol
Spec
Min
Max
VCC (min) to CS# Low
tVSL
Power-Up to Write — Time Delay Before Write Command
tPUW
Write Inhibit Threshold Voltage
VWI
2.4
V
tPD
10.0
µs
VCC Low
1.0
V
Power-Down Time
VCC Power-Down Reset Threshold Voltage
10
Unit
µs
10
ms
Note:
1. These parameters are characterized only.
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Document No. 001-99199 Rev. *A
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S25FL1-K SPI Power-Up Timing and Reset
3
Software Reset Command
After a Power-On (Cold) Reset or Power-Down and Voltage Drop, issuing the Software Reset command is
recommended as a best practice. The Software controlled Reset command restores the device to its initial power
up state by reloading volatile registers from non-volatile default values.
A Software Reset is initiated by the Software Reset Enable command (66h) followed by the Software Reset
command (99h) and then executed when CS# is brought high after tRCH time at the end of the Software Reset
instruction and requires an additional tRST time before executing the next Instruction after the Software Reset as
shown in Figure 2 and Table 2.
Figure 2. Software Reset Command Timing
tCS2
tRST
CS#
SCLK
tRCH
SI
7 6 5
4 3 2 1
0
7 6 5 4
3 2 1
0
SO
Phase
Reset Enable Instructi on (66h)
Reset Instruction (99h)
Reset to Next Inst..
Table 2. Software Reset Timing
Spec
Parameter
Symbol
End of Reset
Instruction to CE# High
tRCH
40
ns
CE# High to Next
Instruction after Reset
tRST
1.5
µs
Min
Max
Unit
If a Software Reset is initiated during a Erase, Program or Register write operation, the data in that Sector, Page,
or Register is unknown, and the operation needs to be initiated again.
When the device is in Deep Power Down mode, the software reset commands are ignored and have no effect. To
reset the device send the Release Power down command (ABh) and after the time duration of CS# High to
Standby Mode without Electronic Signature Read tRES1, the device will resume normal operation and the Software
reset commands will be accepted.
4
Summary
The Power-Up Timing and Voltage Levels specified in the S25FL1-K device family data sheet should be strictly
adhered to during the Power-On Reset (POR) process, and, in particular, Chip Select CS# should not be held low
during the POR. Furthermore, issuing the Software Reset command after the Power-On (Cold) Reset or PowerDown and Voltage Drop is recommended as a best practice.
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Document No. 001-99199 Rev. *A
2
S25FL1-K SPI Power-Up Timing and Reset
Document History Page
Document Title: AN99199 - S25FL1-K SPI Power-Up Timing and Reset
Document Number: 001-99199
Rev.
ECN No.
Orig. of
Change
4929456
MSWI
**
*A
www.cypress.com
Submission
Date
Description of Change
09/04/2014
Initial version
09/22/2015
Updated in Cypress template
Document No. 001-99199 Rev. *A
3
S25FL1-K SPI Power-Up Timing and Reset
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