S29PL-J to S29GL-A / S29GL-N Migrating from the 64 Megabit and 32 Megabit S29PL-J (110 nm) to the S29GL-A (200 nm) / S29GL-N (110 nm) Application Note Introduction This migration guide covers the migration of 64 Mbit and 32 Mbit S29PL-J to S29GL-A and S29GL-N. The S29GL-A and S29GL-N families of devices are the latest in the Spansion line of high performance, 3.0 volt-only, Page Mode devices. Built on 200 nm and 110 nm MirrorBit® Flash process technology, the S29GL-A and S29GL-N is a natural step forward for users of S29PL-J devices. The S29GL-A and S29GL-N product families feature densities ranging from 16 Mbit to 512 Mbit. Many new features have been added to the S29GL-A and S29GL-N product lines, including: Write Buffer programming capability Advance Sector Protection algorithm enhancements Larger Secured Silicon Sector Region x16 / x8 Data Bus Width capability Software Migration Considerations Changes required in SW when migrating from the S29PL-J to S29GL-A / S29GL-N Device ID needs to be changed to match the device ID for the product being designed in. May need to implement software changes using erase / program suspend to adjust for the single bank (no Simultaneous Operation) of S29GL-A / S29GL-N vs. the multi-bank S29PL-J. If changing in density from the S29PL-J to the S29GL-A / S29GL-N, then the appropriate density SW changes will need to be made, such as # of blocks. Software programming routines need to be modified to enable buffer writes to maintain program throughput efficiency. Repetitive single bit updating should not be performed on the S29GL-A. Software watchdog timers monitoring programming operations may require modification due to increased programming times in S29GL-A/N. Memory controller configuration software/firmware may require modification due to a variety of timing differences, including: slower minimum access time in S29GL-A/N, longer data setup requirements in S29GL-A/N, minimum CE# negation requirement during polling with S29GL-A/N, longer delay for data bus to tristate after OE# negated in S29GL-N, longer write pulse width negation requirement in S29GL-A/N. Publication Number PL-J_to_GL-A_N_MIGRATE_AN Revision 01 Issue Date May 10, 2007 A pplication 1. Note Feature Comparison Table 1.1 provides an overview of the feature comparisons between the S29PL-J and S29GL-A / S29GL-N families of devices. Table 1.1 Comparisons of Key Features S29PL064J, S29PL032J S29GL064A, S29GL032A, S29GL016A S29GL064N, S29GL032N Process Technology 110 nm Floating Gate 200 nm MirrorBit 110 nm MirrorBit VCC Voltage Range 2.7 V to 3.6 V 2.7 V to 3.6 V 2.7 V to 3.6 V Feature Data Bus Width x16-only x16 / x8 x16 / x8 -25°C to 85°C, -40°C to 85°C -25°C to 85°C, -40°C to 85°C -25°C to 85°C, -40°C to 85°C 55, 60, 65, 70 ns 90, 100, 110 ns 70, 90 ns 20, 25, 30 ns 25, 30 ns 25, 30 ns Cycle 1 227Eh 227Eh (GL064A) 227Eh (GL032A) 2249h (GL016A) 22C4h (GL016A) 227Eh Cycle 2 2202h (PL064J) 220Ah (PL032J) 220Ch (GL064A) 221Dh (GL032A) 220Ch (GL064N) 221Dh (GL032N) Cycle 3 2201h (PL064J) 2201h (PL032J) 2201h (GL064A) 2200h (GL032A) 2201h (GL064N) 2200h (GL032N) 4 Kword, 32 Kword 4 Kword, 32 Kword 4 Kword, 32 Kword Yes Yes Yes Write Buffer Programming None 16-word write buffer 16-word write buffer Accelerated Programming 8.5 V to 9.5 V 11.5 V to 12.5 V 11.5 V to 12.5 V Program / Erase Suspend Yes Yes Yes Simultaneous Read/Write Yes, 4 Banks No, 1 Bank No, 1 Bank Yes Yes Yes WP#, ASP protection in sector groups WP#, ASP protection in sectors or sector groups Operating Temperature Range (Wireless, Industrial) Random Access Time Page Access Time Device ID Sector Architecture (Small, Large Sectors) Secured Silicon Sector CFI Compliant Sector Protection 2 S29PL-J to S29GL-A / S29GL-N WP#, ASP protection in sectors or sector groups PL-J_to_GL-A_N_MIGRATE_AN_01 May 10, 2007 App l ic atio n 2. No t e Command Table Comparison Most device commands were not changed from the S29PL-J- to the S29GL-A / S29GL-N. Table 2.1 highlights the command table differences between the three families of devices. Table 2.1 Command Table Differences Function Device ID Difference For S29GL016A only, Device ID must be read in one cycle. Secured Silicon Protection Bit Program NA in S29GL-A family. Use Lock Register Program in S29GL-N family. (2) Secured Silicon Protection Bit Status NA in S29GL-A family. Use Lock Register Read in S29GL-N family. (2) Password Program NA in S29GL-A family. Use Password Protection Program in S29GL-N family. (3) Password Verify NA in S29GL-A family. Use Password Protection Read in S29GL-N family. (3) Password Unlock NA in S29GL-A family. Use Password Protection Unlock in S29GL-N family. (3) PPB Program NA in S29GL-A family. Use PPB Program in S29GL-N family. (4) PPB Status NA in S29GL-A family. Use PPB Status Read in S29GL-N family. (4) All PPB Erase NA in S29GL-A family. Use All PPB Erase in S29GL-N family. (4) PPB Lock Bit Set NA in S29GL-A family. Use PPB Lock Bit Set in S29GL-N family. (5) DYB Write NA in S29GL-A family. Use DYB Set in S29GL-N family. (6) DYB Erase NA in S29GL-A family. Use DYB Clear in S29GL-N family. (6) DYB Status NA in S29GL-A family. Use DYB Status Read in S29GL-N family. (6) PPMLB Program NA in S29GL-A family. PPMLB Status NA in S29GL-A family SPMLB Program NA in S29GL-A family SPMLB Status NA in S29GL-A family x8 Mode Commands NA in S29PL-J family. Write to Buffer NA in S29PL-J family. Program Buffer to Flash NA in S29PL-J family. Write to Buffer Abort Reset NA in S29PL-J family. Unlock Bypass Erase NA in S29GL-A and S29GL-N families. Unlock Bypass CFI NA in S29GL-A and S29GL-N families. Accelerated Program Command not necessary to perform Accelerated Program in S29GL-A and S29GL-N families. Advanced Sector Protection modes Five new modes introduced in S29GL-N to simplify commands for Advanced Sector Protection. See data sheet for details. Notes 1. Bold indicates a new command for S29GL-A and/or S29GL-N. 2. Must enter Lock Register Bits mode first. 3. Must enter Password Protection mode first. 4. Must enter Non-Volatile Sector Protection (PPB) mode first. 5. Must enter Global Volatile Sector Protection Freeze (PPB Lock) mode first. 6. Must enter Volatile Sector Protection (DYB) mode first. May 10, 2007 PL-J_to_GL-A_N_MIGRATE_AN_01 S29PL-J to S29GL-A / S29GL-N 3 A pplication 3. Note Write Buffer Programming Write buffers were added to the S29GL-A and S29GL-N families of devices. Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system programs six unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-A4. All subsequent address/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation aborts. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address is programmed. Once the specified number of write buffer locations are loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5 = 0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. This flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. For applications requiring incremental bit programming, a modified programming method is required; please contact your local Spansion representative. Any bit in a write buffer address range cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1. 4 S29PL-J to S29GL-A / S29GL-N PL-J_to_GL-A_N_MIGRATE_AN_01 May 10, 2007 App l ic atio n 4. No t e Secured Silicon Sector Changes The Secured Silicon Sector provides an extra Flash Memory region that enables permanent storage of an Electronic Serial Number (ESN). This can be critical to applications that require secure identification or defense against illegal cloning. The Secured Silicon Sector length has doubled on the S29PL-N family to accommodate a larger ESN. There are now 128 words for a factory entered ESN and 128 words for customer-secured data. These two areas can be used independently of each other. Please contact your local Spansion sales representative for details on how to obtain factory-secured devices. 5. Sector Protection Improvements The Advanced Sector Protection scheme on the S29GL-N devices allows the user to disable and enable programming or erase operations in any or all sectors of the memory array. The various methods of protecting data can be handled entirely via software commands. 6. Performance Characteristics Table 6.1 Read Access Time Comparison Read Access times (Maximum) S29PL-J S29GL-A S29GL-N Page Access Times (1) 20 ns - 30 ns 25 ns - 30 ns 25 ns - 30 ns Random access times (1) 55 ns - 70 ns 90 ns - 110 ns 70 ns - 90 ns Note 1. Varies with speed option. Table 6.2 Performance Comparisons, Typical Program and Erase Times Program and Erase Performance (typical) S29PL-J S29GL-A X16 X16 X16 500 ms 500 ms 500 ms Chip Erase Time (1) 39 s - 71 s 17.5 s - 64 s 32 s - 64 s Word Program Time 6 µs — — Accelerated Word Program Time 4 µs — — Total Write Buffer Programming Time NA 240 µs (16-word operation) 240 µs (16-word operation) Total Accelerated Effective Write Buffer Programming Time NA 240 µs (16-word operation) 200 µs (16-word operation) 12.6 s - 25.2 s 16 s - 63 s 31.5 s - 63 s Sector Erase Time Chip Program Time (1) S29GL-N Note 1. Varies with density. Table 6.3 Current Consumption Comparison, Typical Values Current Consumption (typical values) S29PL-J S29GL-A S29GL-N Active Read Current (1) 20 mA-45 mA 5 mA - 35 mA 25 mA - 30 mA Erase/Program Current 15 mA 50 mA 50 mA Standby Current 200 nA 1 µA 10 µA Note 1. Varies with speed. May 10, 2007 PL-J_to_GL-A_N_MIGRATE_AN_01 S29PL-J to S29GL-A / S29GL-N 5 A pplication 7. Note Pinout Comparison The pinout for the S29PL-J and S29GL-A/S29GL-N are identical except for the BYTE# pin. See Table 7.1. Table 7.1 Pinout Comparison for BYTE# S29PL-J S29GL-A, S29GL-N N/A Not available in this device family. BYTE# Selects 8-bit or 16-bit mode. 8. DC Characteristics Comparison The change from floating-gate technology to the Spansion two-bits-per-cell MirrorBit technology has also resulted in some DC parameter changes. Many of these changes are minor and may not require any change to a user's design. Table 8.1 summarizes these changes. Table 8.1 DC Parameter Differences S29PL-J 6 S29GL-A S29GL-N Min Typ Max Min Typ Max Min Typ Max Unit VCC Active Read Current, 5 MHz — 20 30 — 18 25 — 25 30 mA VCC Active Read Current, 10 MHz — 45 55 — 35 50 — — — mA VCC Active Page Read Current — 10 15 — 10 40 — 10 20 mA VCC Active Program / Erase current — 15 25 — 50 60 — 50 60 mA VCC Standby Current — 0.2 5 — 1 5 — 10 50 µA S29PL-J to S29GL-A / S29GL-N PL-J_to_GL-A_N_MIGRATE_AN_01 May 10, 2007 App l ic atio n 9. No t e AC Characteristics Comparison Table 9.1 Read-only Operation Timing Differences S29PL-J S29GL-A S29GL-N Min Max Min Max Min Max Unit 55-70 ---- 90-110 ---- 70-90 ---- ns tRC Read Cycle Time (1) tACC Address to Output Delay (1) — 50-70 — 90-110 — 70-90 ns tCE Chip Enable to Output Delay (1) — 50-70 — 90-110 — 70-90 ns Page Access Time (1) — 20-30 — 25-30 — 25-30 ns tOE Output Enable to Output Delay (1) — 20-30 — 25-30 — 25-35 ns tDF Chip Enable / Output Enable to Output High Z (1) — 16 — 16 — 25 ns tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First 5 — 0 — 0 — ns tPACC Notes 1. Varies with speed option. Table 9.2 Erase/Program Operation Timing Differences S29PL-J S29GL-A S29GL-N Min Max Min Max Min Max Unit tWC Write Cycle Time (1) 55-70 — 90-110 — 70-90 — ns tAH Address Setup Time (1) 30-35 — 45 — 45 — ns tDS Data Setup Time (1) 25-30 — 35 — 45 — ns ns tCEPH CE# High during toggle bit polling — — 20 — 20 — tOEPH OE# High during toggle bit polling 10 — 20 — 20 — ns tWPH Write Pulse Width High (1) 20-25 — 30 — 30 — ns tBUSY WE# High to RY/BY# Low (1) 35 90 90-110 — 70-90 — ns tPSL Program Suspend Latency — 35 — — — — us tESL Erase Suspend Latency — 35 — — — — us tPOLL Program Valid before Status Polling — — — 4 — — us Note 1. Varies with speed option. May 10, 2007 PL-J_to_GL-A_N_MIGRATE_AN_01 S29PL-J to S29GL-A / S29GL-N 7 A pplication Note 10. Revision History Section Description Revision 01 (May 10, 2007) Initial release 8 S29PL-J to S29GL-A / S29GL-N PL-J_to_GL-A_N_MIGRATE_AN_01 May 10, 2007 App l ic atio n No t e Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2007 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. May 10, 2007 PL-J_to_GL-A_N_MIGRATE_AN_01 S29PL-J to S29GL-A / S29GL-N 9