51 This section of the manual contains the following major topics: 51.1 51.2 51.3 51.4 51.5 51.6 51.7 Introduction .................................................................................................................. 51-2 Modes of Operation ..................................................................................................... 51-4 Control Registers ......................................................................................................... 51-5 Effects Of Reset ......................................................................................................... 51-54 Operation in Power-Saving Modes ............................................................................ 51-54 Related Application Notes.......................................................................................... 51-55 Revision History ......................................................................................................... 51-56 © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-1 Hi-Speed USB with On-The-Go (OTG) Section 51. Hi-Speed USB with On-The-Go (OTG) PIC32 Family Reference Manual Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on the device variant, this manual section may not apply to all PIC32 devices. Please consult the note at the beginning of the “Hi-Speed USB with On-The-Go (OTG)” chapter in the current device data sheet to check whether this document supports the device you are using. Device data sheets and family reference manual sections are available for download from the Microchip Worldwide Web site at: http://www.microchip.com 51.1 INTRODUCTION The USB module includes the following features: • • • • • • • • • • • • • USB Hi-Speed, Full-Speed, and Low-Speed support for host and device USB OTG support with one or more Hi-Speed, Full-Speed, or Low-Speed device Integrated signaling resistors Integrated analog comparators for VBUS monitoring Integrated USB transceiver Transaction handshaking performed by hardware Integrated 8-channel DMA to access system RAM and Flash Seven transmit endpoints and seven receive endpoints, in addition to Endpoint 0 Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) support Suspend and resume signaling support Dynamic FIFO sizing Integrated RAM for the FIFOs, eliminating the need for system RAM for the FIFOs Link power management support Note 1: The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is responsible for investigating and satisfying any applicable licensing obligations. 2: When the USB module is used, the Primary Oscillator (POSC) is limited to either 12 MHz or 24 MHz. 3: To avoid cache coherency problems on devices with L1 cache, USB buffers must only be allocated or accessed from the KSEG1 segment. DS60001326B-page 51-2 © 2013-2015 Microchip Technology Inc. PIC32 Hi-Speed USB with On-The-Go (OTG) Interface Diagram USBCLK POSC (12 MHz or 24 MHz only) USB PLL UPLLEN UPLLFSEL Endpoint Control EP0 Control Host Section 51. Hi-Speed USB with On-The-Go (OTG) © 2013-2015 Microchip Technology Inc. Figure 51-1: EPO Control Function DMA Requests Transmit EP1 - EP7 Control Combine Endpoints Receive Host Transaction Scheduler Interrupt Control Interrupts EP Reg Decoder Common Regs D+ UTM Synchronization Packet Encode/Decode D- Data Sync Packet Encode Hi-Speed Negotiation Packet Decode HNP/SRP CRC Gen/Check VUSB3V3 VBUS USB 2.0 Hi-Speed PHY Cycle Control System Bus Slave mode RX Buff RX Buff FIFO Decoder TX Buff TX Buff Cycle Control Timers DS60001326B-page 51-3 Link Power Management RAM 51 Hi-Speed USB with On-The-Go (OTG) USBID RAM Controller PIC32 Family Reference Manual 51.2 MODES OF OPERATION The Hi-Speed USB OTG module has two main modes of operation: Device mode and Host mode. In Device mode, the module encodes, decodes, checks, and directs all USB packets sent and received. IN transactions are handled through the device’s TX FIFOs, OUT transactions are handled through its RX FIFOs. Control, Bulk, Isochronous and Interrupt transactions are also supported. In Host mode, the way in which the Hi-Speed USB OTG module behaves depends on whether it is linked up for point-to-point communications with another USB function or whether it is attached to a hub. When attached to another USB function, the module offers the range of capabilities needed in order to act as the host in point-to-point communications with this USB function. When attached to a hub, it provides the facilities required to act as the host to a number of devices, supported simultaneously. When operating in Host mode and used for point-to-point communications with a single other USB device (which can be Hi-Speed, Full-Speed, or Low-Speed), the Hi-Speed USB OTG module can support Control, Bulk, Isochronous or Interrupt transactions. IN transactions are handled through the RX FIFOs, OUT transactions are handled through the TX FIFOs. As well as encoding, decoding and checking the USB packets sent and received, the module will also automatically schedule Isochronous endpoints and Interrupt endpoints to perform one transaction every ‘n’ frames/microframes (or up to three transactions if the high-bandwidth option is selected), where ‘n’ represents the polling interval that has been programmed for the endpoint. The remaining bus bandwidth is shared equally between the Control and Bulk endpoints. When attached to a hub, the Hi-Speed USB OTG module continues to offer the facilities previously mentioned, but it needs to be further programmed with these details: • The function address of the target device • The operating speed of the target device (so that the appropriate speed conversion can be carried out) • If the target device is a Full-Speed or Low-Speed device that is accessed through a Hi-Speed hub, the endpoint additionally needs to be programmed with the function address and port number of the hub The device may be required to power the VBUS3V3 pin to 5V as the ‘A’ device of the connection (source of power and default host) or, as the ‘B’ device (default peripheral), to be able to wake the ‘A’ device by charging the VBUS3V3 pin to 2V. Outputs from the Hi-Speed USB OTG module indicate when these charging options are required. Whether the Hi-Speed USB OTG module initially operates in Host mode or in Device mode depends on whether it is being used in an ‘A’ device or a ‘B’ device, which in turn depends on whether the USBID input pin is low or high. When the module is operating as an ‘A’ device, it is initially configured to operate in Host mode. When operating as a ‘B’ device, the module is initially configured to operate in Device mode. However, a HOSTREQ bit is provided in the USBOTG register through which the CPU can request that the ‘B’ device becomes the Host the next time there is no activity on the USB bus. The USBID input pin reflects the state of the ID pin of the device’s mini-AB receptacle, with USBID being low indicating an ‘A’ plug (i.e., operation as an ‘A’ device), and USBID being high indicating a ‘B’ plug and operation as a ‘B’ device. Information on whether the Hi-Speed USB OTG module is acting as an ‘A’ device or as a ‘B’ device and on whether the device it is connected to is Hi-Speed, Full-Speed, or Low-Speed is also recorded in the USBOTG register, along with information about the level of the VBUS3V3 pin relative to the high- and low-voltage thresholds used to signal Session Start and Session End. DS60001326B-page 51-4 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 CONTROL REGISTERS The Hi-Speed USB with On-The-Go (OTG) module for PIC32 devices contains the following Special Function Registers (SFRs): • • • • • • • • • • • • • • • • • • • • • • • • • • • • • USBCSR0: USB Control Status Register 0 USBCSR1: USB Control Status Register 1 USBCSR2: USB Control Status Register 2 USBCSR3: USB Control Status Register 3 USBIE0CSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 0) USBIE0CSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 0) USBIE0CSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 0) USBIENCSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7) USBIENCSR1: USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7) USBIENCSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 1-7) USBIENCSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 1-7) USBFIFOx: USB FIFO Data Register ‘x’ (‘x’ = 0-7) USBOTG: USB OTG Control/Status Register USBFIFOA: USB FIFO Address Register USBHWVER: USB Hardware Version Register USBINFO: USB Information Register USBEOFRST: USB End-of-Frame/Soft Reset Control Register USBExTXA: USB Endpoint ‘x’ Transmit Address Register USBExRXA: USB Endpoint ‘x’ Receive Address Register USBDMAINT: USB DMA Interrupt Register USBDMAxC: USB DMA Channel ‘x’ Control Register (‘x’ = 1-8) USBDMAxA: USB DMA Channel ‘x’ Memory Address Register (‘x’ = 1-8) USBDMAxN: USB DMA Channel ‘x’ Count Register (‘x’ = 1-8) USBExRPC: USB Endpoint ‘x’ Request Packet Count Register (Host Mode Only) (‘x’ = 1-7) USBDPBFD: USB Double Packet Buffer Disable Register USBTMCON1: USB Timing Control Register 1 USBTMCON2: USB Timing Control Register 2 USBLPMR1: USB Link Power Management Control Register 1 USBLPMR2: USB Link Power Management Control Register 2 © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-5 Hi-Speed USB with On-The-Go (OTG) 51.3 Bit Range Register Name Table 51-1: 31:16 USBCSR0 USBCSR1 USBCSR2 USBCSR3 15:0 31:16 Hi-Speed USB with On-The-Go (OTG) Special Function Register Map Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 — — — — — — EP7TXIF EP6TXIF EP5TXIF EP4TXIF — — ISOUPD(1) SOFT CONN(1) —(2) —(2) — — 17/1 16/0 EP3TXIF EP2TXIF EP1TXIF EP0IF FUNC<6:0>(1) HSMODE RESET RESUME SUSP MODE SUSPEN — —(2) —(2) —(2) —(2) —(2) —(2) —(2) — — — — — — EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE EP1RXIF — 15:0 — — — — — — — — EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF 31:16 VBUSIE SESSRQIE DISCONIE CONNIE SOFIE RESETIE RESUMEIE SUSPIE VBUSIF SESS REQIF DISCONIF CONNIF SOFIF RESETIF 15:0 — — — EP3RXIE EP2RXIE 31:16 FORCEHST 15:0 — — FIFOACC FORCEFS FORCEHS — — — — — — — EP7RXIE EP6RXIE EP5RXIE EP4RXIE PACKET TESTK TESTJ NAK — — — — — — 31:16 USB IE0CSR0(3) — — — — — — — — — — — — — — 31:16 USB IE0CSR3(3) 15:0 MPRXEN MPTXEN BIGEND HBRXEN HBTXEN — — — — — ISO 31:16 USB IENCSR0(4) AUTOSET MODE — DATA TGGL(2) — — — — FLSHFIFO — NAKLIM<4:0>(2) — — — — — DMA REQEN FRC DATTG DMA REQMD (1) — — (2) DTWREN DATA TGGL(2) SVCRPR © 2013-2015 Microchip Technology Inc. AUTOCLR AUTOREQ(2) DMA REQEN SETUP END(1) DATAEND(1) SENT STALL(1) NAK TMOUT(2) STATPKT(2) REQPKT(2) ERROR(2) SETUP PKT(2) RXSTALL(2) — — — — — SPEED<1:0>(2) — — — — TXPKT RDY RXPKT RDY — — — — — — RXCNT<6:0> — — — — — — — — — — — — — — — — SENT STALL(1) SEND STALL(1) FIFONE RXSTALL(2) SETUPPKT(2) TXPKT RDY FIFOFULL RXPKT RDY INCOMP TX(1) NAK TMOUT(2) CLRDT FLUSH UNDER RUN(1) ERROR(2) TXMAXP<10:0> DISNYET(1) PIDERR(2) DMA REQMD —(1) —(1) DATA TWEN(2) DATA TGGL(2) INCOM PRX SENTSTALL(1) SENDSTALL(1) CLRDT RXSTALL(2) MULT<4:0> REQPKT(2) FLUSH DATAERR(1) OVERRUN(1) DERR NAKT(1) ERROR(2) RXMAXP<10:0> TXINTERV<7:0>(2) — EP1RXIE ENDPOINT<3:0> SEND STALL(1) (1) — DYNFIFOS SOFTCONE UTMIDWID — SVC SETEND(1) MULT<4:0> 15:0 31:16 USB IENCSR3(1,3) 15:0 — (1) ISO(1) 31:16 USB IENCSR2(4) 15:0 — (1) 15:0 31:16 USB IENCSR1(4) (1) DISPING(2) DTWREN(2) 15:0 RESUMEIF SUSPIF RFRMNUM<10:0> (1) — 31:16 USB IE0CSR2(3) 15:0 Legend: Note 1: 2: 3: 4: 5: 18/2 HSEN (1) USB FIFO0 19/3 SPEED<1:0>(2) — PROTOCOL<1:0> TEP<3:0> RXCNT<13:0> RXFIFOSZ<3:0> TXFIFOSZ<3:0> RXINTERV<7:0> — — SPEED<1:0> 31:16 DATA<31:16> 15:0 DATA<15:0> x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. — — PROTOCOL<1:0> — — TEP<3:0> — — PIC32 Family Reference Manual DS60001326B-page 51-6 Table 51-1 provides a brief summary of the related registers. Corresponding register tables appear after the summary, which include a detailed description of each bit. Bit Range Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 USB FIFO1 31:16 15:0 DATA<15:0> USB FIFO2 31:16 DATA<31:16> 15:0 DATA<15:0> USB FIFO3 31:16 DATA<31:16> 15:0 DATA<15:0> USB FIFO4 31:16 DATA<31:16> 15:0 DATA<15:0> USB FIFO5 31:16 DATA<31:16> 15:0 DATA<15:0> USB FIFO6 31:16 DATA<31:16> 15:0 DATA<15:0> USB FIFO7 31:16 DATA<31:16> 15:0 20/4 19/3 TXDPB 18/2 17/1 16/0 DATA<15:0> — — — RXDPB 15:0 — — — — USB FIFOA 31:16 — — — 15:0 — — — USB HWVER 31:16 — — — 15:0 RC USB INFO 31:16 USB EOFRST 31:16 USB E0TXA 31:16 — 15:0 — USB E0RXA 31:16 — 15:0 — USB E1TXA 31:16 — 15:0 — USB E1RXA 31:16 — 15:0 — USB E2TXA 31:16 — 15:0 — USB E2RXA 31:16 — 15:0 — DS60001326B-page 51-7 Legend: Note 1: 2: 3: 4: 5: 21/5 DATA<31:16> 31:16 USBOTG 22/6 RXFIFOSZ<3:0> — — TXEDMA RXEDMA — — — BDEV FSDEV LSDEV — — — — — — — — — RAMBITS<3:0> — — — NRSTX — — — — WTID<3:0> TXENDPTS<3:0> — — — — — — — — — — — — — — — — — — TXHUBPRT<6:0> — — — — — — — RXHUBPRT<6:0> — — — — TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — — MULTTRAN RXHUBPRT<6:0> — — LSEOF<7:0> MULTTRAN — TXHUBPRT<6:0> — — HSEOF<7:0> RXHUBPRT<6:0> — — WTCON<3:0> NRST TXHUBPRT<6:0> — — RXENDPTS<3:0> FSEOF<7:0> — — VERMINOR<9:0> DMACHANS<3:0> — HOSTREQ SESSION TXFIFOAD<12:0> — VERMAJOR<4:0> 15:0 HOSTMODE RXFIFOAD<12:0> VPLEN<7:0> 15:0 TXFIFOSZ<3:0> VBUS<1:0> — — — — — — — — — TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> MULTTRAN TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. 51 Hi-Speed USB with On-The-Go (OTG) Register Name Hi-Speed USB with On-The-Go (OTG) Special Function Register Map (Continued) Section 51. Hi-Speed USB with On-The-Go (OTG) © 2013-2015 Microchip Technology Inc. Table 51-1: Bit Range Register Name Hi-Speed USB with On-The-Go (OTG) Special Function Register Map (Continued) Bits 31/15 © 2013-2015 Microchip Technology Inc. USB E3TXA 31:16 — 15:0 — USB E3RXA 31:16 — 15:0 — US BE4TXA 31:16 — 15:0 — USB E4RXA 31:16 — 15:0 — USB E5TXA 31:16 — 15:0 — USB E5RXA 31:16 — 15:0 — USB E6TXA 31:16 — 15:0 — USB E6RXA 31:16 — 15:0 — USB E7TXA 31:16 — 15:0 — USB E7RXA 31:16 — 15:0 — USB E0CSR0 31:16 USB E0CSR2 31:16 USB E0CSR3 31:16 USB E1CSR0 31:16 USB E1CSR1 31:16 USB E1CSR2 31:16 USB E1CSR3 31:16 USB E2CSR0 31:16 Legend: Note 1: 2: 3: 4: 5: 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 30/14 29/13 28/12 — — — 27/11 26/10 25/9 24/8 — — — TXHUBPRT<6:0> — — — — — — — TXHUBPRT<6:0> — — — — — — — RXHUBPRT<6:0> — — — — — — — TXHUBPRT<6:0> — — — — — — — RXHUBPRT<6:0> — — — — — — — TXHUBPRT<6:0> — — — — — — — RXHUBPRT<6:0> — — — — — — — TXHUBPRT<6:0> — — — — — — — RXHUBPRT<6:0> — — — — 22/6 MULTTRAN RXHUBPRT<6:0> — 23/7 — — — 21/5 20/4 19/3 TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> MULTTRAN TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> MULTTRAN TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> MULTTRAN TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> MULTTRAN TXHUBADD<6:0> — TXFADDR<6:0> MULTTRAN RXHUBADD<6:0> — RXFADDR<6:0> Indexed by the same bits in USBIE0CSR0 Indexed by the same bits in USBIE0CSR2 Indexed by the same bits in USBIE0CSR3 Indexed by the same bits in USBIE1CSR0 Indexed by the same bits in USBIE1CSR1 Indexed by the same bits in USBIE1CSR2 Indexed by the same bits in USBIE1CSR3 Indexed by the same bits in USBIE2CSR0 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. 18/2 17/1 16/0 PIC32 Family Reference Manual DS60001326B-page 51-8 Table 51-1: Bit Range Register Name 31:16 USB E2CSR2 31:16 USB E2CSR3 31:16 USB E3CSR0 31:16 USB E3CSR1 31:16 USB E3CSR2 31:16 USB E3CSR3 31:16 USB E4CSR0 31:16 USB E4CSR1 31:16 USB E4CSR2 31:16 USB E4CSR3 31:16 USB E5CSR0 31:16 USB E5CSR1 31:16 USB E5CSR2 31:16 USB E5CSR3 31:16 USB E6CSR0 31:16 USB E6CSR1 31:16 USB E6CSR2 31:16 Legend: Note 1: 2: 3: 4: 5: 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Indexed by the same bits in USBIE2CSR1 Indexed by the same bits in USBIE2CSR2 Indexed by the same bits in USBIE2CSR3 Indexed by the same bits in USBIE3CSR0 Indexed by the same bits in USBIE3CSR1 Indexed by the same bits in USBIE3CSR2 Indexed by the same bits in USBIE3CSR3 Indexed by the same bits in USBIE4CSR0 Indexed by the same bits in USBIE4CSR1 Indexed by the same bits in USBIE4CSR2 Indexed by the same bits in USBIE4CSR3 Indexed by the same bits in USBIE5CSR0 Indexed by the same bits in USBIE5CSR1 Indexed by the same bits in USBIE5CSR2 Indexed by the same bits in USBIE5CSR3 Indexed by the same bits in USBIE6CSR0 Indexed by the same bits in USBIE6CSR1 Indexed by the same bits in USBIE6CSR2 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. 51 Hi-Speed USB with On-The-Go (OTG) DS60001326B-page 51-9 USB E2CSR1 Hi-Speed USB with On-The-Go (OTG) Special Function Register Map (Continued) Section 51. Hi-Speed USB with On-The-Go (OTG) © 2013-2015 Microchip Technology Inc. Table 51-1: Bit Range Register Name Hi-Speed USB with On-The-Go (OTG) Special Function Register Map (Continued) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 © 2013-2015 Microchip Technology Inc. USB E6CSR3 31:16 USB E7CSR0 31:16 USB E7CSR1 31:16 USB E7CSR2 31:16 USB E7CSR3 31:16 USB DMAINT 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF USB DMA1C 31:16 — — — — — — — — — — — — 15:0 — — — — — USB DMA1A 31:16 15:0 DMAADDR<15:0> USB DMA1N 31:16 DMACOUNT<31:16> USB DMA2C 31:16 — — — — — 15:0 — — — — — USB DMA2A 31:16 15:0 DMAADDR<15:0> USB DMA2N 31:16 DMACOUNT<31:16> USB DMA3C 31:16 — — — — — 15:0 — — — — — USB DMA3A 31:16 15:0 DMAADDR<15:0> USB DMA3N 31:16 DMACOUNT<31:16> USB DMA4C 31:16 — — — — — 15:0 — — — — — USB DMA4A 31:16 15:0 DMAADDR<15:0> USB DMA4N 31:16 DMACOUNT<31:16> 15:0 DMACOUNT<15:0> Legend: Note 1: 2: 3: 4: 5: Indexed by the same bits in USBIE6CSR3 15:0 Indexed by the same bits in USBIE7CSR0 15:0 Indexed by the same bits in USBIE7CSR1 15:0 Indexed by the same bits in USBIE7CSR2 15:0 Indexed by the same bits in USBIE7CSR3 15:0 DMABRSTM<1:0> DMAERR DMAEP<3:0> — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — DMABRSTM<1:0> — — — DMAERR — — DMAEP<3:0> — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — DMABRSTM<1:0> — — — DMAERR — — DMAEP<3:0> — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — DMABRSTM<1:0> — — DMAERR — — DMAEP<3:0> DMAADDR<31:16> x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. — — — — — DMAIE DMAMODE DMADIR DMAEN PIC32 Family Reference Manual DS60001326B-page 51-10 Table 51-1: Bit Range Register Name Hi-Speed USB with On-The-Go (OTG) Special Function Register Map (Continued) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — 24/8 23/7 22/6 — — — © 2013-2015 Microchip Technology Inc. USB DMA5C 31:16 — — — — — 15:0 — — — — — USB DMA5A 31:16 15:0 DMAADDR<15:0> USB DMA5N 31:16 DMACOUNT<31:16> USB DMA6C 31:16 — — — — — 15:0 — — — — — USB DMA6A 31:16 15:0 DMAADDR<15:0> USB DMA6N 31:16 DMACOUNT<31:16> USB DMA7C 31:16 — — — — — 15:0 — — — — — USB DMA7A 31:16 15:0 DMAADDR<15:0> USB DMA7N 31:16 DMACOUNT<31:16> USB DMA8C 31:16 — — — — — 15:0 — — — — — USB DMA8A 31:16 15:0 DMAADDR<15:0> USB DMA8N 31:16 DMACOUNT<31:16> USB E1RPC 31:16 USB E2RPC 31:16 USB E3RPC 31:16 USB E4RPC 31:16 USB E5RPC 31:16 USB E6RPC 31:16 Legend: Note 1: 2: 3: 4: 5: DMABRSTM<1:0> DMAERR 20/4 — — DMAEP<3:0> 19/3 18/2 17/1 16/0 — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — DMABRSTM<1:0> — — — DMAERR — — DMAEP<3:0> — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — DMABRSTM<1:0> — — — DMAERR — — DMAEP<3:0> — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — DMABRSTM<1:0> — — — DMAERR — — DMAEP<3:0> — — — — DMAIE DMAMODE DMADIR DMAEN DMAADDR<31:16> 15:0 DMACOUNT<15:0> — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — RQPKTCNT<15:0> — — — — — — — — 15:0 — RQPKTCNT<15:0> — — — — — — — — 15:0 — RQPKTCNT<15:0> — — — — — — — — 15:0 — RQPKTCNT<15:0> — — — — — — — — 15:0 15:0 21/5 — RQPKTCNT<15:0> — — — — — — — — — RQPKTCNT<15:0> x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. PIC32 Family Reference Manual DS60001326B-page 51-11 Table 51-1: Bit Range Register Name Hi-Speed USB with On-The-Go (OTG) Special Function Register Map (Continued) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — USB E7RPC 31:16 USB DPBFD 31:16 — — — — — — — — EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD EP2TXD EP1TXD — 15:0 — — — — — — — — EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD EP2RXD EP1RXD — USB TMCON1 31:16 USB TMCON2 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — USB LPMR1 31:16 — — LPM ERRIE LPM RESIE LPMACKIE LPMNYIE LPMSTIE LPMTOIE — — — LPMRES LPMXMT — — — RMTWAK — — — — — — — — — — — PHYIDEN VBUS MONEN ASVAL MONEN 15:0 RQPKTCNT<15:0> THHSRTN<15:0> 15:0 TUCH<15:0> 15:0 31:16 USB LMPR2 USB CRCON(5) Legend: Note 1: 2: 3: 4: 5: 15:0 31:16 15:0 ENDPOINT<3:0> — — — — — — — LPMFADDR<6:0> — — — — — — — — USBIF USBRF USBWKUP — USB IDOVEN USB IDVAL THSBT<3:0> LPMNAK(1) LPMEN<1:0> —(2) —(2) — — — — — LPMRES LPMNC LPMACK LPMNY LPMST — — — — — BSVAL MONEN SEND MONEN USBRIE USB WKUPEN HIRD<3:0> LNKSTATE<3:0> — LPMERR(1) x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0). Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7). This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. —(2) —(2) USBIE PIC32 Family Reference Manual DS60001326B-page 51-12 Table 51-1: © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 USBCSR0: USB Control Status Register 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF R/W-0 R/W-0 R/W-1 R-0, HS R-0 R/W-0 R-0, HC R/W-0 ISOUPD SOFTCONN — — HSEN HSMODE RESET RESUME SUSPMODE SUSPEN U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — FUNC<6:0> — — — — Legend: HS = Hardware Settable HC = Hardware Clearable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-17 EP7TXIF:EP1TXIF: Endpoint ‘n’ TX Interrupt Flag bit 1 = Endpoint has a transmit interrupt to be serviced 0 = No interrupt event bit 16 EP0IF: Endpoint 0 Interrupt bit 1 = Endpoint 0 has an interrupt to be serviced 0 = No interrupt event All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently from the remaining bits in this register to avoid accidental clearing. bit 15 ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode) 1 = The USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet 0 = No change in behavior This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is unimplemented in Host mode. bit 14 SOFTCONN: Soft Connect/Disconnect Feature Selection bit 1 = The USB D+/D- lines are enabled and active 0 = The USB D+/D- lines are disabled and are tri-stated This bit is only available in Device mode. bit 13 HSEN: Hi-Speed Enable bit 1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub 0 = The USB module only operates in Full-Speed mode bit 12 HSMODE: Hi-Speed Mode Status bit 1 = Hi-Speed mode successfully negotiated during a USB reset 0 = The USB module is not in Hi-Speed mode In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when the RESET bit is cleared. bit 11 RESET: Module Reset Status bit 1 = Reset signaling is present on the bus 0 = Normal module operation In Device mode, this bit is read-only. In Host mode, this bit is read/write. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-13 Hi-Speed USB with On-The-Go (OTG) Register 51-1: PIC32 Family Reference Manual Register 51-1: USBCSR0: USB Control Status Register 0 (Continued) bit 10 RESUME: Resume from Suspend control bit 1 = Generate Resume signaling when the device is in Suspend mode 0 = Stop Resume signaling In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, the software should clear this bit after 20 ms. bit 9 SUSPMODE: Suspend Mode status bit 1 = The USB module is in Suspend mode 0 = The USB module is in normal operation This bit is read-only in Device mode. In Host mode, it can be set by software, and is cleared by hardware. bit 8 SUSPEN: Suspend Mode Enable bit 1 = Suspend mode is enabled 0 = Suspend mode is not enabled bit 7 Unimplemented: Read as ‘0’ bit 6-0 FUNC<6:0>: Device Function Address bits These bits are only available in Device mode. These bits are written with the address received through a SET_ADDRESS command, which will then be used for decoding the function address in subsequent token packets. DS60001326B-page 51-14 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 USBCSR1: USB Control Status Register 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS U-0 EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF EP1RXIF — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-17 EP7TXIE:EP1TXIE: Endpoint ‘n’ Transmit Interrupt Enable bits 1 = Endpoint Transmit interrupt events are enabled 0 = Endpoint Transmit interrupt events are not enabled bit 16 EP0IE: Endpoint 0 Interrupt Enable bit 1 = Endpoint 0 interrupt events are enabled 0 = Endpoint 0 interrupt events are not enabled bit 15-8 Unimplemented: Read as ‘0’ bit 7-1 EP7RXIF:EP1RXIF: Endpoint ‘n’ RX Interrupt bit 1 = Endpoint has a receive event to be serviced 0 = No interrupt event bit 0 Unimplemented: Read as ‘0’ © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-15 Hi-Speed USB with On-The-Go (OTG) Register 51-2: PIC32 Family Reference Manual Register 51-3: Bit Range 31:24 23:16 15:8 7:0 USBCSR2: USB Control Status Register 2 Bit 31/23/15/7 R/W-0 VBUSIE Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 SESSRQIE DISCONIE Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 CONNIE SOFIE RESETIE RESUMEIE SUSPIE R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS VBUSIF SESSRQIF DISCONIF CONNIF SOFIF RESETIF RESUMEIF SUSPIF U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 EP7RXIE EP6RXIE EP5RXIE EP4RXIE EP3RXIE EP2RXIE EP1RXIE — Legend: HS = Hardware Settable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 VBUSIE: VBUS Error Interrupt Enable bit 1 = VBUS error interrupt is enabled 0 = VBUS error interrupt is disabled bit 30 SESSRQIE: Session Request Interrupt Enable bit 1 = Session request interrupt is enabled 0 = Session request interrupt is disabled bit 29 DISCONIE: Device Disconnect Interrupt Enable bit 1 = Device disconnect interrupt is enabled 0 = Device disconnect interrupt is disabled bit 28 CONNIE: Device Connection Interrupt Enable bit 1 = Device connection interrupt is enabled 0 = Device connection interrupt is disabled bit 27 SOFIE: Start of Frame Interrupt Enable bit 1 = Start of Frame event interrupt is enabled 0 = Start of Frame event interrupt is disabled bit 26 RESETIE: Reset/Babble Interrupt Enable bit 1 = Interrupt when reset (Device mode) or Babble (Host mode) is enabled 0 = Reset/Babble interrupt is disabled bit 25 RESUMEIE: Resume Interrupt Enable bit 1 = Resume signaling interrupt is enabled 0 = Resume signaling interrupt is disabled bit 24 SUSPIE: Suspend Interrupt Enable bit 1 = Suspend signaling interrupt is enabled 0 = Suspend signaling interrupt is disabled bit 23 VBUSIF: VBUS Error Interrupt bit 1 = VBUS has dropped below the VBUS valid threshold during a session 0 = No interrupt bit 22 SESSRQIF: Session Request Interrupt bit 1 = Session request signaling has been detected 0 = No session request detected bit 21 DISCONIF: Device Disconnect Interrupt bit 1 = In Host mode, indicates when a device disconnect is detected. In Device mode, indicates when a session ends. 0 = No device disconnect detected bit 20 CONNIF: Device Connection Interrupt bit 1 = In Host mode, indicates when a device connection is detected 0 = No device connection detected DS60001326B-page 51-16 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 bit 18 RESETIF: Reset/Babble Interrupt bit 1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on the bus. 0 = No reset/babble detected bit 17 RESUMEIF: Resume Interrupt bit 1 = Resume signaling is detected on the bus while USB module is in Suspend mode 0 = No Resume signaling detected bit 16 SUSPIF: Suspend Interrupt bit 1 = Suspend signaling is detected on the bus (Device mode) 0 = No suspend signaling detected bit 15-8 Unimplemented: Read as ‘0’ bit 7-1 EP7RXIE:EP1RXIE: Endpoint ‘n’ Receive Interrupt Enable bit 1 = Receive interrupt is enabled for this endpoint 0 = Receive interrupt is not enabled bit 0 Unimplemented: Read as ‘0’ © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-17 Hi-Speed USB with On-The-Go (OTG) Register 51-3: USBCSR2: USB Control Status Register 2 (Continued) bit 19 SOFIF: Start of Frame Interrupt bit 1 = A new frame has started 0 = No start of frame detected PIC32 Family Reference Manual Register 51-4: Bit Range 31:24 23:16 15:8 7:0 USBCSR3: USB Control Status Register 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FORCEHST FIFOACC FORCEFS FORCEHS PACKET TESTK TESTJ NAK U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — U-0 U-0 U-0 U-0 U-0 ENDPOINT<3:0> — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RFRMNUM<10:8> R-0 R-0 R-0 RFRMNUM<7:0> Legend: HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 FORCEHST: Test Mode Force Host Select bit 1 = Forces the USB module into Host mode, regardless of whether it is connected to any peripheral 0 = Normal operation bit 30 FIFOACC: Test Mode Endpoint 0 FIFO Transfer Force bit 1 = Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO 0 = No transfer bit 29 FORCEFS: Test mode Force Full-Speed Mode Select bit 1 = Forces the USB module into Full-Speed mode. Undefined behavior if FORCEHS = 1. 0 = If FORCEHS = 0, the USB module is placed into Low-Speed mode This bit is only active if FORCEHST = 1. bit 28 FORCEHS: Test mode Force Hi-Speed Mode Select bit 1 = Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1. 0 = If FORCEFS = 0, the USB module is placed into Low-Speed mode This bit is only active if FORCEHST = 1. bit 27 PACKET: Test_Packet Test Mode Select bit 1 = The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded into the Endpoint 0 FIFO before the test mode is entered. 0 = Normal operation This bit is only active if the USB module is in Hi-Speed mode. bit 26 TESTK: Test_K Test Mode Select bit 1 = Enters Test_K test mode. The USB module transmits a continuous K on the bus. 0 = Normal operation This bit is only active if the USB module is in Hi-Speed mode. bit 25 TESTJ: Test_J Test Mode Select bit 1 = Enters Test_J test mode. The USB module transmits a continuous J on the bus. 0 = Normal operation This bit is only active if the USB module is in Hi-Speed mode. bit 24 NAK: Test_SE0_NAK Test Mode Select bit 1 = Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid IN token with a NAK 0 = Normal operation This mode is only active if the USB module is in Hi-Speed mode. bit 23-20 Unimplemented: Read as ‘0’ DS60001326B-page 51-18 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Hi-Speed USB with On-The-Go (OTG) Register 51-4: USBCSR3: USB Control Status Register 3 (Continued) bit 19-16 ENDPOINT<3:0>: Endpoint Registers Select bits 1111 = Reserved • • • 1000 = Reserved 0111 = Endpoint 7 • • • 0000 = Endpoint 0 These bits select which endpoint registers are accessed through addresses 0x3010-0x301F. bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 RFRMNUM<10:0>: Last Received Frame Number bits © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-19 PIC32 Family Reference Manual Register 51-5: Bit Range USBIE0CSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 0) Bit 31/23/15/7 U-0 31:24 23:16 15:8 7:0 Bit Bit 30/22/14/6 29/21/13/5 U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0, HC R/W-0 R/W-0, HC — — — DISPING DTWREN DATATGGL R-0 U-0 — — — — R/W-0, HC R/W-0, HC R/W-0, HC R/C-0, HS SVCSETEND SVCRPR SENDSTALL SETUPEND R/W-0, HS R-0, HS DATAEND SENTSTALL FLSHFIFO R-0 TXPKTRDY RXPKTRDY NAKTMOUT STATPKT REQPKT ERROR SETUPPKT RXSTALL U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: HC = Cleared by hardware HS Cleared by software R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 x = Bit is unknown bit 31-28 Unimplemented: Read as ‘0’ bit 27 DISPING: Disable Ping tokens control bit (Host mode) 1 = The USB Module will not issue Ping tokens in data and status phases of a Hi-Speed control transfer 0 = Ping tokens are issued bit 26 DTWREN: Data Toggle Write Enable bit (Host mode) 1 = Enable the current state of the Endpoint 0 data toggle to be written. This bit is automatically cleared. 0 = Disable data toggle write bit 25 DATATGGL: Data Toggle bit (Host mode) When read, this bit indicates the current state of the Endpoint 0 data toggle. If DTWREN = 1, this bit is writable with the desired setting If DTWREN = 0, this bit is read-only bit 24 FLSHFIFO: Flush FIFO Control bit 1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should be used only when TXPKTRDY/RXPKTRDY = 1. 0 = No Flush operation bit 23 SVCSETEND: Clear SETUPEND Control bit (Device mode) 1 = Clear the SETUPEND bit in this register. This bit is automatically cleared. 0 = Do not clear NAKTMOUT: NAK Time-out Control bit (Host mode) 1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLIM<4:0> bits (USBICSR<28:24>) 0 = Allow the endpoint to continue bit 22 SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode) 1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared. 0 = Do not clear STATPKT: Status Stage Transaction Control bit (Host mode) 1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction 0 = Do not perform a status stage transaction DS60001326B-page 51-20 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 REQPKT: IN transaction Request Control bit (Host mode) 1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set. 0 = Do not request an IN transaction bit 20 SETUPEND: Early Control Transaction End Status bit (Device mode) 1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and the FIFO flushed at this time. 0 = Normal operation This bit is cleared by writing a ‘1’ to the SVCSETEND bit in this register. ERROR: No Response Error Status bit (Host mode) 1 = Three attempts have been made to perform a transaction with no response from the peripheral. An interrupt is generated. 0 = Clear this flag. Software must write a ‘0’ to this bit to clear it. bit 19 DATAEND: End of Data Control bit (Device mode) The software sets this bit when: • Setting TXPKTRDY for the last data packet • Clearing RXPKTRDY after unloading the last data packet • Setting TXPKTRDY for a zero length data packet Hardware clears this bit. SETUPPKT: Send a SETUP token Control bit (Host mode) 1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an OUT token for the transaction 0 = Normal OUT token operation Setting this bit also clears the Data Toggle. bit 18 SENTSTALL: STALL sent status bit (Device mode) 1 = STALL handshake has been transmitted 0 = Software clear of bit RXSTALL: STALL handshake received Status bit (Host mode) 1 = STALL handshake was received 0 = Software clear of bit bit 17 TXPKTRDY: TX Packet Ready Control bit 1 = Data packet has been loaded into the FIFO. This bit is cleared automatically. 0 = No data packet is ready for transmit bit 16 RXPKTRDY: RX Packet Ready Status bit 1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set. 0 = No data packet has been received This bit is cleared by setting the SVCRPR bit. bit 15-0 Unimplemented: Read as ‘0’ © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-21 Hi-Speed USB with On-The-Go (OTG) Register 51-5: USBIE0CSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 0) (Continued) bit 21 SENDSTALL: Send Stall Control bit (Device mode) 1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared. 0 = Do not send STALL handshake. PIC32 Family Reference Manual Register 51-6: Bit Range 31:24 23:16 15:8 7:0 USBIE0CSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 0) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 U-0 SPEED<1:0> U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 U-0 U-0 NAKLIM<4:0> U-0 U-0 U-0 — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — RXCNT<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 NAKLIM<4:0>: Endpoint 0 NAK Limit bits The number of frames/microframes (Hi-Speed transfers) after which Endpoint 0 should time-out on receiving a stream of NAK responses. bit 23-22 SPEED<1:0>: Operating Speed Control bits 11 = Low-Speed 10 = Full-Speed 01 = Hi-Speed 00 = Reserved bit 21-7 Unimplemented: Read as ‘0’ bit 6-0 RXCNT<6:0>: Receive Count bits The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY is set. DS60001326B-page 51-22 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 USBIE0CSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 0) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R-x R-x R-0 R-x R-x MPRXEN MPTXEN BIGEND HBRXEN HBTXEN U-0 U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-1 R-0 DYNFIFOS SOFTCONE UTMIDWID U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 MPRXEN: Automatic Amalgamation Option bit 1 = Automatic amalgamation of bulk packets is done 0 = No automatic amalgamation bit 30 MPTXEN: Automatic Splitting Option bit 1 = Automatic splitting of bulk packets is done 0 = No automatic splitting bit 29 BIGEND: Byte Ordering Option bit 1 = Big Endian ordering 0 = Little Endian ordering bit 28 HBRXEN: High-bandwidth RX ISO Option bit 1 = High-bandwidth RX ISO endpoint support is selected 0 = No High-bandwidth RX ISO endpoint support bit 27 HBTXEN: High-bandwidth TX ISO Option bit 1 = High-bandwidth TX ISO endpoint support is selected 0 = No High-bandwidth TX ISO endpoint support bit 26 DYNFIFOS: Dynamic FIFO Sizing Option bit 1 = Dynamic FIFO sizing is supported 0 = No Dynamic FIFO sizing is supported bit 25 SOFTCONE: Soft Connect/Disconnect Option bit 1 = Soft Connect/Disconnect is supported 0 = Soft Connect/Disconnect is not supported bit 24 UTMIDWID: UTMI+ Data Width Option bit This bit is always ‘0’, indicating 8-bit UTMI+ data width. x = Bit is unknown bit 23-0 Unimplemented: Read as ‘0’ © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-23 Hi-Speed USB with On-The-Go (OTG) Register 51-7: PIC32 Family Reference Manual Register 51-8: Bit Range 31:24 USBIENCSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DATAWEN DATATGGL R/W-0 R/W-0, HC FIFONE TXPKTRDY R/W-0 R/W-0 AUTOSET R/W-0, HS INCOMPTX 23:16 NAKTMOUT R/W-0 15:8 ISO — R/W-0, HC CLRDT R/W-0 MODE DMAREQEN FRCDATTG DMAREQMD R/W-0, HS R/W-0 R/W-0 SENTSTALL SENDSTALL RXSTALL SETUPPKT R/W-0 R/W-0 FLUSH R/W-0 R/W-0, HS UNDERRUN ERROR R/W-0 MULT<4:0> R/W-0 7:0 R/W-0 R/W-0 TXMAXP<10:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXMAXP<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 AUTOSET: Auto Set Control bit 1 = TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have to be set manually. 0 = TXPKTRDY must be set manually for all packet sizes bit 30 ISO: Isochronous TX Endpoint Enable bit (Device mode) 1 = Enables the endpoint for Isochronous transfers 0 = Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers. This bit only has an effect in Device mode. In Host mode, it always returns ‘0’. bit 29 MODE: Endpoint Direction Control bit 1 = Endpoint is TX 0 = Endpoint is RX This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions. bit 28 DMAREQEN: Endpoint DMA Request Enable bit 1 = DMA requests are enabled for this endpoint 0 = DMA requests are disabled for this endpoint bit 27 FRCDATTG: Force Endpoint Data Toggle Control bit 1 = Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. 0 = No forced behavior bit 26 DMAREQMD: Endpoint DMA Request Mode Control bit 1 = DMA Request Mode 1 0 = DMA Request Mode 0 This bit must not be cleared either before or in the same cycle as the above DMAREQEN bit is cleared. bit 25 DATAWEN: Data Toggle Write Enable bit (Host mode) 1 = Enable the current state of the TX endpoint data toggle (DATATGGL) to be written 0 = Disables writing the DATATGGL bit bit 24 DATATGGL: Data Toggle Control bit (Host mode) When read, this bit indicates the current state of the TX endpoint data toggle. If DATAWEN = 1, this bit may be written with the required setting of the data toggle. If DATAWEN = 0, any value written to this bit is ignored. DS60001326B-page 51-24 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 In anything other than isochronous transfers, this bit will always return ‘0’. NAKTMOUT: NAK Time-out status bit (Host mode) 1 = TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting 0 = Written by software to clear this bit bit 22 CLRDT: Clear Data Toggle Control bit 1 = Resets the endpoint data toggle to 0 0 = Do not clear the data toggle bit 21 SENTSTALL: STALL handshake transmission status bit (Device mode) 1 = STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit is cleared. 0 = Written by software to clear this bit RXSTALL: STALL receipt bit (Host mode) 1 = STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed and the TXPKTRDY bit is cleared. 0 = Written by software to clear this bit bit 20 SENDSTALL: STALL handshake transmission control bit (Device mode) 1 = Issue a STALL handshake to an IN token 0 = Terminate stall condition This bit has no effect when the endpoint is being used for Isochronous transfers. SETUPPKT: Definition bit (Host mode) 1 = When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token for the transaction. This also clears the Data Toggle. 0 = Normal OUT token for the transaction bit 19 FLUSH: FIFO Flush control bit 1 = Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, TXPKTRDY is cleared and an interrupt is generated. 0 = Do not flush the FIFO bit 18 UNDERRUN: Underrun status bit (Device mode) 1 = An IN token has been received when TXPKTRDY is not set. 0 = Written by software to clear this bit ERROR: Handshake failure status bit (Host mode) 1 = Three attempts have been made to send a packet and no handshake packet has been received 0 = Written by software to clear this bit bit 17 FIFONE: FIFO Not Empty status bit 1 = At least 1 packet in the TX FIFO 0 = TX FIFO is empty bit 16 TXPKTRDY: TX Packet Ready Control bit The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-25 Hi-Speed USB with On-The-Go (OTG) Register 51-8: USBIENCSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7) (Continued) bit 23 INCOMPTX: Incomplete TX Status bit (Device mode) 1 = For high-bandwidth Isochronous endpoint, a large packet has been split into two or three packets for transmission, but insufficient IN tokens have been received to send all the parts 0 = Normal operation PIC32 Family Reference Manual Register 51-8: USBIENCSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7) (Continued) bit 15-11 MULT<4:0>: Multiplier Control bits For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT + 1 for the payload size. For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required to be an exact multiple of the payload specified by TXMAXP. For Isochronous/Interrupts endpoints operating in Hi-Speed mode, the value of MULT may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe. bit 10-0 TXMAXP<10:0>: Maximum TX Payload per transaction Control bits These bits set the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Full-Speed and Hi-Speed operations. TXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1. DS60001326B-page 51-26 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 USBIENCSR1: USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7) Bit Bit Range 31/23/15/7 31:24 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 AUTOCLR ISO R/W-0, HC 23:16 15:8 7:0 CLRDT R/W-0 AUTOREQ DMAREQEN R/W-0, HS R/W-0 SENTSTALL SENDSTALL RXSTALL REQPKT R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0, HC R-0 R/W-0 — — DISNYET PIDERR DMAREQMD R/W-0, HC FLUSH DATATWEN DATATGGL R-0, HS R/W-0, HS DATAERR OVERRUN DERRNAKT ERROR R/W-0 R/W-0 R/W-0 MULT<4:0> R/W-0 R/W-0 R/W-0 R-0, HSC R/W-0, HS FIFOFULL RXPKTRDY R/W-0 R/W-0 RXMAXP<10:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXMAXP<7:0> Legend: HC = Hardware Clearable HS = Hardware Settable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 INCOMPRX x = Bit is unknown AUTOCLR: RXPKTRDY Automatic Clear Control bit 1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte chunks regardless of the RXMAXP. 0 = No automatic clearing of RXPKTRDY This bit should not be set for high-bandwidth Isochronous endpoints. bit 30 ISO: Isochronous Endpoint Control bit (Device mode) 1 = Enable the RX endpoint for Isochronous transfers 0 = Enable the RX endpoint for Bulk/Interrupt transfers AUTOREQ: Automatic Packet Request Control bit (Host mode) 1 = REQPKT will be automatically set when the RXPKTRDY bit is cleared 0 = No automatic packet request This bit is automatically cleared when a short packet is received. bit 29 DMAREQEN: DMA Request Enable Control bit 1 = Enable DMA requests for the RX endpoint 0 = Disable DMA requests for the RX endpoint bit 28 DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode) 1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX packets are ACKed including at the point at which the FIFO becomes full. 0 = Normal operation. In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for all Interrupt endpoints. PIDERR: PID Error Status bit (Host mode) 1 = In ISO transactions, this indicates a PID error in the received packet 0 = No error bit 27 DMAREQMD: DMA Request Mode Selection bit 1 = DMA Request Mode 1 0 = DMA Request Mode 0 bit 26 DATATWEN: Data Toggle Write Enable Control bit (Host mode) 1 = DATATGGL can be written 0 = DATATGGL is not writable © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-27 Hi-Speed USB with On-The-Go (OTG) Register 51-9: PIC32 Family Reference Manual Register 51-9: USBIENCSR1: USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7) (Continued) bit 25 DATATGGL: Data Toggle bit (Host mode) When read, this bit indicates the current state of the endpoint data toggle. If DATATWEN = 1, this bit may be written with the required setting of the data toggle. If DATATWEN = 0, any value written to this bit is ignored. bit 24 INCOMPRX: Incomplete Packet Status bit 1 = The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received 0 = Written by then software to clear this bit In anything other than Isochronous transfer, this bit will always return ‘0’. bit 23 CLRDT: Clear Data Toggle Control bit 1 = Reset the endpoint data toggle to 0 0 = Leave endpoint data toggle alone bit 22 SENTSTALL: STALL Handshake Status bit (Device mode) 1 = STALL handshake is transmitted 0 = Written by the software to clear this bit RXSTALL: STALL Handshake Receive Status bit (Host mode) 1 = A STALL handshake has been received. An interrupt is generated. 0 = Written by the software to clear this bit bit 21 SENDSTALL: STALL Handshake Control bit (Device mode) 1 = Issue a STALL handshake 0 = Terminate stall condition REQPKT: IN Transaction Request Control bit (Host mode) 1 = Request an IN transaction. 0 = No request This bit is cleared when RXPKTRDY is set. bit 20 FLUSH: Flush FIFO Control bit 1 = Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is double-buffered, FLUSH may need to be set twice to completely clear the FIFO. 0 = Normal FIFO operation This bit is automatically cleared. bit 19 DATAERR: Data Packet Error Status bit (Device mode) 1 = The data packet has a CRC or bit-stuff error. 0 = No data error This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns ‘0’. DERRNAKT: Data Error/NAK Time-out Status bit (Host mode) 1 = The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK limit. 0 = No data or NAK time-out error DS60001326B-page 51-28 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 ERROR: No Data Packet Received Status bit (Host mode) 1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt is generated. 0 = Written by the software to clear this bit. This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns ‘0’. bit 17 FIFOFULL: FIFO Full Status bit 1 = No more packets can be loaded into the RX FIFO 0 = The RX FIFO has at least one free space bit 16 RXPKTRDY: Data Packet Reception Status bit 1 = A data packet has been received. An interrupt is generated. 0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO bit 15-11 MULT<4:0>: Multiplier Control bits For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT + 1 for the payload size. For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required to be an exact multiple of the payload specified by TXMAXP. For Isochronous/Interrupts endpoints operating in Hi-Speed mode, the value of MULT may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe. bit 10-0 RXMAXP<10:0>: Maximum RX Payload Per Transaction Control bits These bits set the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Full-Speed and Hi-Speed operations. RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-29 Hi-Speed USB with On-The-Go (OTG) Register 51-9: USBIENCSR1: USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7) (Continued) bit 18 OVERRUN: Data Overrun Status bit (Device mode) 1 = An OUT packet cannot be loaded into the RX FIFO. 0 = Written by software to clear this bit This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns ‘0’. PIC32 Family Reference Manual Register 51-10: USBIENCSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 1-7) Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 R/W-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 TXINTERV<7:0> R/W-0 R/W-0 R/W-0 SPEED<1:0> R/W-0 PROTOCOL<1:0> U-0 U-0 — — R-0 R-0 R-0 TEP<3:0> R-0 RXCNT<13:8> R-0 R-0 R-0 R-0 RXCNT<7:0> Legend: HC = Hardware Clearable HS = Hardware Settable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 TXINTERV<7:0>: Endpoint TX Polling Interval/NAK Limit bits (Host mode) For Interrupt and Isochronous transfers, these bits define the polling interval for the endpoint. For Bulk endpoints, these bits set the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses. The following table describes the valid values and interpretation for these bits: Transfer Type Speed Valid Values (m) Low-Speed/ Full-Speed 0x01 to 0xFF Polling interval is ‘m’ frames. Hi-Speed 0x01 to 0x10 Polling interval is 2(m-1) frames. Isochronous Full-Speed or Hi-Speed 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes. Bulk Full-Speed or Hi-Speed 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A value of ‘0’ or ‘1’ disables the NAK time-out function. Interrupt Interpretation bit 23-22 SPEED<1:0>: TX Endpoint Operating Speed Control bits (Host mode) 11 = Low-Speed 10 = Full-Speed 01 = Hi-Speed 00 = Reserved bit 21-20 PROTOCOL<1:0>: TX Endpoint Protocol Control bits 11 = Interrupt 10 = Bulk 01 = Isochronous 00 = Control bit 19-16 TEP<3:0>: TX Target Endpoint Number bits This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during device enumeration. bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 RXCNT<13:0>: Receive Count bits The number of received data bytes in the RX FIFO endpoint. The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY is set. DS60001326B-page 51-30 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R-x R-x R-x R-x R-x RXFIFOSZ<3:0> U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x TXFIFOSZ<3:0> U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXINTERV<7:0> SPEED<1:0> R/W-0 PROTOCOL<1:0> TEP<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 RXFIFOSZ<3:0>: Receive FIFO Size bits 1111 = Reserved 1110 = Reserved 1101 = 8192 bytes 1100 = 4096 bytes • • • 0011 = 8 bytes 0010 = Reserved 0001 = Reserved 0000 = Reserved or endpoint has not been configured This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic FIFO sizing is used. bit 27-24 TXFIFOSZ<3:0>: Transmit FIFO Size bits 1111 = Reserved 1110 = Reserved 1101 = 8192 bytes 1100 = 4096 bytes • • • 0011 = 8 bytes 0010 = Reserved 0001 = Reserved 0000 = Reserved or endpoint has not been configured This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic FIFO sizing is used. bit 23-16 Unimplemented: Read as ‘0’ © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-31 Hi-Speed USB with On-The-Go (OTG) Register 51-11: USBIENCSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 1-7) PIC32 Family Reference Manual Register 51-11: USBIENCSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 1-7) (Continued) bit 15-8 RXINTERV<7:0>: Endpoint RX Polling Interval/NAK Limit bits For Interrupt and Isochronous transfers, these bits define the polling interval for the endpoint. For Bulk endpoints, these bits set the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses. The following table describes the valid values and meaning for these bits: Transfer Type Speed Valid Values (m) Low-Speed/ Full-Speed 0x01 to 0xFF Polling interval is ‘m’ frames. Hi-Speed 0x01 to 0x10 Polling interval is 2(m-1) frames. Isochronous Full-Speed or Hi-Speed 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes. Bulk Full-Speed or Hi-Speed 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A value of ‘0’ or ‘1’ disables the NAK time-out function. Interrupt Interpretation bit 7-6 SPEED<1:0>: RX Endpoint Operating Speed Control bits 11 = Low-Speed 10 = Full-Speed 01 = Hi-Speed 00 = Reserved bit 5-4 PROTOCOL<1:0>: RX Endpoint Protocol Control bits 11 = Interrupt 10 = Bulk 01 = Isochronous 00 = Control bit 3-0 TEP<3:0>: RX Target Endpoint Number bits This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during device enumeration. DS60001326B-page 51-32 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA<23:16> R/W-0 DATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown DATA<31:0>: USB Transmit/Receive FIFO Data bits Writes to this register loads data into the TX FIFO for the corresponding endpoint. Reading from this register unloads data from the RX FIFO for the corresponding endpoint. Transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the data accessed is contiguous. However, all transfers associated with one packet must be of the same width so that data is consistently byte-, word- or double-word aligned. The last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-33 Hi-Speed USB with On-The-Go (OTG) Register 51-12: USBFIFOx: USB FIFO Data Register ‘x’ (‘x’ = 0-7) PIC32 Family Reference Manual Register 51-13: USBOTG: USB OTG Control/Status Register Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RXDPB U-0 U-0 U-0 R/W-0 RXFIFOSZ<3:0> R/W-0 R/W-0 R/W-0 R/W-0 — — — TXDPB U-0 U-0 U-0 U-0 U-0 TXFIFOSZ<3:0> U-0 R/W-0 R/W-0 — — — — — — TXEDMA RXEDMA R-1 R-0 R-0 R-0 R-0 R-0 R/W-0, HC R/W-0 BDEV FSDEV LSDEV VBUS<1:0> HOSTMODE HOSTREQ SESSION Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28 RXDPB: RX Endpoint Double-packet Buffering Control bit 1 = Double-packet buffer is supported. This doubles the size set in RXFIFOSZ. 0 = Double-packet buffer is not supported bit 27-24 RXFIFOSZ<3:0>: RX Endpoint FIFO Packet Size bits The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission) 1111 = Reserved • • • 1010 = Reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 bytes 0000 = 8 bytes bit 23-21 Unimplemented: Read as ‘0’ bit 20 TXDPB: TX Endpoint Double-packet Buffering Control bit 1 = Double-packet buffer is supported. This doubles the size set in TXFIFOSZ. 0 = Double-packet buffer is not supported DS60001326B-page 51-34 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission) 1111 = Reserved • • • 1010 = Reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 bytes 0000 = 8 bytes bit 15-10 Unimplemented: Read as ‘0’ bit 9 TXEDMA: TX Endpoint DMA Assertion Control bit 1 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode. 0 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. bit 8 RXEDMA: RX Endpoint DMA Assertion Control bit 1 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode. 0 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. bit 7 BDEV: USB Device Type bit 1 = USB is operating as a ‘B’ device 0 = USB is operating as an ‘A’ device bit 6 FSDEV: Full-Speed/Hi-Speed device detection bit (Host mode) 1 = A Full-Speed or Hi-Speed device has been detected being connected to the port 0 = No Full-Speed or Hi-Speed device was detected bit 5 LSDEV: Low-Speed Device Detection bit (Host mode) 1 = A Low-Speed device has been detected being connected to the port 0 = No Low-Speed device was detected bit 4-3 VBUS<1:0>: VBUS Level Detection bits 11 = Above VBUS Valid 10 = Above AValid, below VBUS Valid 11 = Above Session End, below AValid 00 = Below Session End bit 2 HOSTMODE: Host Mode bit 1 = The USB module is acting as a Host 0 = The USB module is not acting as a Host bit 1 HOSTREQ: Host Request Control bit ‘B’ device only: 1 = USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when Host Negotiation is completed. 0 = Host Negotiation is not taking place © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-35 Hi-Speed USB with On-The-Go (OTG) Register 51-13: USBOTG: USB OTG Control/Status Register (Continued) bit 19-16 TXFIFOSZ<3:0>: TX Endpoint FIFO packet size bits PIC32 Family Reference Manual Register 51-13: USBOTG: USB OTG Control/Status Register (Continued) bit 0 SESSION: Active Session Control/Status bit ‘A’ device: 1 = Start a session 0 = End a session ‘B’ device: 1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol 0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect Clearing this bit when the USB module is not suspended will result in undefined behavior. DS60001326B-page 51-36 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFIFOAD<12:8> R/W-0 RXFIFOAD<7:0> R/W-0 TXFIFOAD<12:8> R/W-0 R/W-0 R/W-0 TXFIFOAD<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-16 RXFIFOAD<12:0>: Receive Endpoint FIFO Address bits Start address of the endpoint FIFO in units of 8 bytes as follows: 1111111111111 = 0xFFF8 • • • 0000000000010 = 0x0010 0000000000001 = 0x0008 0000000000000 = 0x0000 bit 15-13 Unimplemented: Read as ‘0’ bit 12-0 TXFIFOAD<12:0>: Transmit Endpoint FIFO Address bits Start address of the endpoint FIFO in units of 8 bytes as follows: 1111111111111 = 0xFFF8 • • • 0000000000010 = 0x0010 0000000000001 = 0x0008 0000000000000 = 0x0000 © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-37 Hi-Speed USB with On-The-Go (OTG) Register 51-14: USBFIFOA: USB FIFO Address Register PIC32 Family Reference Manual Register 51-15: USBHWVER: USB Hardware Version Register Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RC R-0 VERMAJOR<4:0> R-0 VERMINOR<9:8> R-0 R-0 VERMINOR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 RC: Release Candidate bit 1 = The USB module was created using a release candidate 0 = The USB module was created using a full release bit 14-10 VERMAJOR<4:0>: USB Module Major Version number bits This read-only number is the Major version number for the USB module. bit 9-0 VERMINOR<9:0>: USB Module Minor Version number bits This read-only number is the Minor version number for the USB module. DS60001326B-page 51-38 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 VPLEN<7:0> R/W-0 R/W-1 R-1 R-0 R/W-0 R/W-1 R/W-1 R/W-1 R-0 R-1 R-1 WTCON<3:0> R-0 WTID<3:0> DMACHANS<3:0> R-0 R-1 R-1 RXENDPTS<3:0> R-0 R-0 RAMBITS<3:0> R-1 R-0 R-1 R-1 R-1 TXENDPTS<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 VPLEN<7:0>: VBUS pulsing charge length bits Sets the duration of the VBUS pulsing charge in units of 546.1 µs. The default setting corresponds to 32.77 ms. bit 23-20 WTCON<3:0>: Connect/Disconnect filter control bits Sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. The default setting corresponds to 2.667 µs. bit 19-6 WTID<3:0>: ID delay valid control bits Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms. The default setting corresponds to 52.43 ms. bit 15-12 DMACHANS<3:0>: DMA Channels bits These read-only bits provide the number of DMA channels in the USB module. For the PIC32MZ EC family, this number is 8. bit 11-8 RAMBITS<3:0>: RAM address bus width bits These read-only bits provide the width of the RAM address bus. For the PIC32MZ EC family, this number is 12. bit 7-4 RXENDPTS<3:0>: Included RX Endpoints bits This read-only register gives the number of RX endpoints in the design. For the PIC32MZ EC family, this number is 7. bit 3-0 TXENDPTS<3:0>: Included TX Endpoints bits These read-only bits provide the number of TX endpoints in the design. For the PIC32MZ EC family, this number is 7. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-39 Hi-Speed USB with On-The-Go (OTG) Register 51-16: USBINFO: USB Information Register PIC32 Family Reference Manual Register 51-17: USBEOFRST: USB End-of-Frame/Soft Reset Control Register Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — NRSTX NRST R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R.W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R.W-1 R/W-1 R/W-1 R.W-0 R/W-0 R/W-0 LSEOF<7:0> R/W-0 FSEOF<7:0> R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 HSEOF<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as ‘0’ bit 25 NRSTX: Reset of XCLK Domain bit 1 = Reset the XCLK domain, which is the clock recovered from the received data by the PHY 0 = Normal operation bit 24 NRST: Reset of CLK Domain bit 1 = Reset the CLK domain, which is the clock recovered from the peripheral bus 0 = Normal operation bit 23-16 LSEOF<7:0>: Low-Speed EOF bits These bits set the Low-Speed transaction in units of 1.067 µs (default setting is 121.6 µs) prior to the EOF to stop new transactions from beginning. bit 15-8 FSEOF<7:0>: Full-Speed EOF bits These bits set the Full-Speed transaction in units of 533.3 µs (default setting is 63.46 µs) prior to the EOF to stop new transactions from beginning. bit 7-0 HSEOF<7:0>: Hi-Speed EOF bits These bits set the Hi-Speed transaction in units of 133.3 µs (default setting is 17.07 µs) prior to the EOF to stop new transactions from beginning. DS60001326B-page 51-40 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — R/W-0 TXHUBPRT<6:0> R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MULTTRAN R/W-0 TXHUBADD<6:0> — TXFADDR<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown Unimplemented: Read as ‘0’ bit 30-24 TXHUBPRT<6:0>: TX Hub Port bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint through a Hi-Speed USB 2.0 hub, these bits record the port number of that USB 2.0 hub. bit 23 MULTTRAN: TX Hub Multiple Translators bit (Host mode) 1 = The USB 2.0 hub has multiple transaction translators 0 = The USB 2.0 hub has a single transaction translator bit 22-16 TXHUBADD<6:0>: TX Hub Address bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint through a Hi-Speed USB 2.0 hub, these bits record the address of that USB 2.0 hub. bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 TXFADDR<6:0>: TX Functional Address bits (Host mode) Specifies the address for the target function that to be accessed through the associated endpoint, which must be defined for each TX endpoint that is used. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-41 Hi-Speed USB with On-The-Go (OTG) Register 51-18: USBExTXA: USB Endpoint ‘x’ Transmit Address Register PIC32 Family Reference Manual Register 51-19: USBExRXA: USB Endpoint ‘x’ Receive Address Register Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — R/W-0 RXHUBPRT<6:0> R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MULTTRAN R/W-0 RXHUBADD<6:0> — RXFADDR<6:0> Legend: HC = Hardware Clearable HS = Hardware Settable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown Unimplemented: Read as ‘0’ bit 30-24 RXHUBPRT<6:0>: RX Hub Port bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint through a Hi-Speed USB 2.0 hub, these bits record the port number of that USB 2.0 hub. bit 23 MULTTRAN: RX Hub Multiple Translators bit (Host mode) 1 = The USB 2.0 hub has multiple transaction translators 0 = The USB 2.0 hub has a single transaction translator bit 22-16 TXHUBADD<6:0>: RX Hub Address bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint through a Hi-Speed USB 2.0 hub, these bits record the address of that USB 2.0 hub. bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 RXFADDR<6:0>: RX Functional Address bits (Host mode) Specifies the address for the target function that to be accessed through the associated endpoint, which must be defined for each RX endpoint that is used. DS60001326B-page 51-42 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 DMA8IF:DMA1IF: DMA Channel ‘x’ Interrupt bit 1 = The DMA channel has an interrupt event 0 = No interrupt event All bits are cleared on a read of the register. © 2013-2015 Microchip Technology Inc. x = Bit is unknown DS60001326B-page 51-43 Hi-Speed USB with On-The-Go (OTG) Register 51-20: USBDMAINT: USB DMA Interrupt Register PIC32 Family Reference Manual Register 51-21: USBDMAxC: USB DMA Channel ‘x’ Control Register (‘x’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DMABRSTM<1:0> — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAIE DMAMODE DMADIR DMAEN DMAEP<3:0> DMAERR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-9 DMABRSTM<1:0>: DMA Burst Mode Selection bit 11 = Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length 10 = Burst Mode 2: INCR8, INCR4 or unspecified length 01 = Burst Mode 1: INCR4 or unspecified length 00 = Burst Mode 0: Bursts of unspecified length bit 8 DMAERR: Bus Error bit 1 = A bus error has been observed on the input 0 = The software writes this to clear the error bit 7-4 DMAEP<3:0>: DMA Endpoint Assignment bits These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7. bit 3 DMAIE: DMA Interrupt Enable bit 1 = Interrupt is enabled for this channel 0 = Interrupt is disabled for this channel bit 2 DMAMODE: DMA Transfer Mode bit 1 = DMA Mode 1 Transfers 0 = DMA Mode 0 Transfers bit 1 DMADIR: DMA Transfer Direction bit 1 = DMA Read (TX endpoint) 0 = DMA Write (RX endpoint) bit 0 DMAEN: DMA Enable bit 1 = Enable the DMA transfer and start the transfer 0 = Disable the DMA transfer DS60001326B-page 51-44 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 DMAADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAADDR<23:16> R/W-0 R/W-0 DMAADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown DMAADDR<31:0>: DMA Memory Address bits This register identifies the current memory address of the corresponding DMA channel. The initial memory address written to this register during initialization must have a value such that its Modulo 4 value is equal to ‘0’. The lower two bits of this register are read only and cannot be set by software. As the DMA transfer progresses, the memory address will increment as bytes are transferred. Register 51-23: USBDMAxN: USB DMA Channel ‘x’ Count Register (‘x’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMACOUNT<31:24> R/W-0 R/W-0 DMACOUNT<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMACOUNT<15:8> R/W-0 R/W-0 DMACOUNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown DMACOUNT<31:0>: DMA Transfer Count bits This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer which identifies the entire transfer length. As the count progresses this count is decremented as bytes are transferred. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-45 Hi-Speed USB with On-The-Go (OTG) Register 51-22: USBDMAxA: USB DMA Channel ‘x’ Memory Address Register (‘x’ = 1-8) PIC32 Family Reference Manual Register 51-24: USBExRPC: USB Endpoint ‘x’ Request Packet Count Register (Host Mode Only) (‘x’ = 1-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RQPKTCNT<15:8> R/W-0 R/W-0 RQPKTCNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 RQPKTCNT<15:0>: Request Packet Count bits Sets the number of packets of size MAXP that are to be transferred in a block transfer. This register is only available in Host mode when the AUTOREQ bit (USBIENCSR1<14>) is set. Register 51-25: USBDPBFD: USB Double Packet Buffer Disable Register Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD EP2TXD EP1TXD — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD EP2RXD EP1RXD — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-17 EP7TXD:EP1TXD: TX Endpoint ‘x’ Double Packet Buffer Disable bits 1 = TX double packet buffering is disabled for Endpoint ‘x’ 0 = TX double packet buffering is enabled for Endpoint ‘x’ bit 16 Unimplemented: Read as ‘0’ bit 15-1 EP7RXD:EP1RXD: RX Endpoint ‘x’ Double Packet Buffer Disable bits 1 = RX double packet buffering is disabled for Endpoint ‘x’ 0 = RX double packet buffering is enabled for Endpoint ‘x’ bit 0 Unimplemented: Read as ‘0’ DS60001326B-page 51-46 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 THHSRTN<15:8> R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 THHSRTN<7:0> R/W-0 TUCH<15:8> R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 TUCH<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 THHSRTN:<15:0>: Hi-Speed Resume Signaling Delay bits These bits set the delay from the end of Hi-Speed resume signaling (acting as a Host) to enable the UTM normal operating mode. bit 15-0 TUCH<15:0>: Chirp Time-out bits These bits set the chirp time-out. This number, when multiplied by 4, represents the number of USB module clock cycles before the time-out occurs. Note: This register will allow the Hi-Speed time-out to be set to values that are greater than the maximum specified in the USB 2.0 specification, making the USB module non-compliant. Register 51-27: USBTMCON2: USB Timing Control Register 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — THBST<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3-0 THBST<3:0>: High Speed Time-out Adder bits These bits represent the value to be added to the minimum Hi-Speed time-out period of 736 bit times. The time-out period can be increased in increments of 64 Hi-Speed bit times (133 ns). Note: This register will allow the Hi-Speed time-out to be set to values that are greater than the maximum specified in the USB 2.0 specification, making the USB module non-compliant. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-47 Hi-Speed USB with On-The-Go (OTG) Register 51-26: USBTMCON1: USB Timing Control Register 1 PIC32 Family Reference Manual Register 51-28: USBLPMR1: USB Link Power Management Control Register 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 — — U-0 U-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 LPMERRIE LPMRESIE LPMACKIE U-0 R/W-0 — — — LPMNAK R-0 R-0 R-0 R-0 ENDPOINT<3:0> R-0 R-0 R-0 R-0 HIRD<3:0> R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 LPMNYIE LPMSTIE LPMTOIE R/W-0 R/W-0, HC R/W-0, HC LPMRES LPMXMT LPMEN<1:0> U-0 U-0 U-0 R-0 — — — RMTWAK R-0 R-0 R-0 R-0 LNKSTATE<3:0> Legend: Hardware Clearable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29 LPMERRIE: LPM Error Interrupt Enable bit 1 = LPMERR interrupt is enabled 0 = LPMERR interrupt is disabled bit 28 LPMRESIE: LPM Resume Interrupt Enable bit 1 = LPMRES interrupt is enabled 0 = LPMRES interrupt is disabled bit 27 LPMACKIE: LPM Acknowledge Interrupt Enable bit 1 = Enable the LPMACK Interrupt 0 = Disable the LPMACK Interrupt bit 26 LPMNYIE: LPM NYET Interrupt Enable bit 1 = Enable the LPMNYET Interrupt 0 = Disable the LPMNYET Interrupt bit 25 LPMSTIE: LPM STALL Interrupt Enable bit 1 = Enable the LPMST Interrupt 0 = Disable the LPMST Interrupt bit 24 LPMTOIE: LPM Time-out Interrupt Enable bit 1 = Enable the LPMTO Interrupt 0 = Disable the LPMTO Interrupt bit 23-21 Unimplemented: Read as ‘0’ bit 20 LPMNAK: LPM-only Transaction Setting bit 1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK 0 = Normal transaction operation Setting this bit to ‘1’ will only take effect after the USB module as been LPM suspended. bit 19-18 LPMEN<1:0>: LPM Enable bits (Device mode) 11 = LPM extended transactions are supported 10 = LPM and Extended transactions are not supported 01 = LPM mode is not supported but extended transactions are supported 00 = LPM extended transactions are supported bit 17 LPMRES: LPM Resume bit 1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 µs. 0 = No resume operation This bit is self-clearing. DS60001326B-page 51-48 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 When LPMXMT and LPMEN are set, the USB module can respond in the following ways: • If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will self clear and a software interrupt will be generated. • If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In this case, the bit will not self clear however a software interrupt will be generated. When in Host mode: 1 = USB module will transmit an LPM transaction. This bit is self clearing, and will be immediately cleared upon receipt of any Token or three time-outs have occurred. 0 = Maintain current state bit 15-12 ENDPOINT<3:0>: LPM Token Packet Endpoint bits This is the endpoint in the token packet of the LPM transaction. bit 11-9 Unimplemented: Read as ‘0’ bit 8 RMTWAK: Remote Wake-up Enable bit This bit is applied on a temporary basis only and is only applied to the current suspend state. 1 = Remote wake-up is enabled 0 = Remote wake-up is disabled bit 7-4 HIRD<3:0>: Host Initiated Resume Duration bits The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual resume time of: Resume Time = 50 µs + HIRD * 75 µs. The resulting range is 50 µs to 1200 µs. bit 3-0 LNKSTATE<3:0>: Link State bits This value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a LPM transaction. The only valid value for this register is ‘1’ for Sleep State (L1). All other values are reserved. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-49 Hi-Speed USB with On-The-Go (OTG) Register 51-28: USBLPMR1: USB Link Power Management Control Register 1 (Continued) bit 16 LPMXMT: LPM Transition to the L1 State bit When in Device mode: 1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must be set to ‘0b11. Both LPMXMT and LPMEN must be set in the same cycle. 0 = Maintain current state PIC32 Family Reference Manual Register 51-29: USBLPMR2: USB Link Power Management Control Register 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — LPMFADDR<6:0> U-0 U-0 — — Legend: R-0 R-0, HS LPMERRIF LPMRESIF R-0, HS R-0, HS R-0, HS R-0, HS LPMNCIF LPMACKIF LPMNYIF LPMSTIF HS = Hardware Settable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 14-8 LPMFADDR<6:0>: LPM Payload Function Address bits These bits contain the address of the LPM payload function. bit 7-6 Unimplemented: Read as ‘0’ bit 5 LPMERRIF: LPM Error Interrupt Flag bit (Device mode) 1 = An LPM transaction was received that had a LINKSTATE field that is not supported. The response will be a STALL. 0 = No error condition bit 4 LPMRESIF: LPM Resume Interrupt Flag bit 1 = The USB module has resumed (for any reason) 0 = No Resume condition bit 3 LPMNCIF: LPM NC Interrupt Flag bit When in Device mode: 1 = The USB module received a LPM transaction and responded with a NYET due to data pending in the RX FIFOs. 0 = No NC interrupt condition When in Host mode: 1 = A LPM transaction is transmitted and the device responded with an ACK 0 = No NC interrupt condition bit 2 LPMACKIF: LPM ACK Interrupt Flag bit When in Device mode: 1 = A LPM transaction was received and the USB Module responded with an ACK 0 = No ACK interrupt condition When in Host mode: 1 = The LPM transaction is transmitted and the device responds with an ACK 0 = No ACK interrupt condition bit 1 LPMNYIF: LPM NYET Interrupt Flag bit When in Device mode: 1 = A LPM transaction is received and the USB Module responded with a NYET 0 = No NYET interrupt flag When in Host mode: 1 = A LPM transaction is transmitted and the device responded with an NYET 0 = No NYET interrupt flag DS60001326B-page 51-50 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 When in Host mode: 1 = A LPM transaction was transmitted and the device responded with a STALL 0 = No Stall condition © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-51 Hi-Speed USB with On-The-Go (OTG) Register 51-29: USBLPMR2: USB Link Power Management Control Register 2 (Continued) bit 0 LPMSTIF: LPM STALL Interrupt Flag bit When in Device mode: 1 = A LPM transaction was received and the USB Module responded with a STALL 0 = No Stall condition PIC32 Family Reference Manual Register 51-30: USBCRCON: USB Clock/Reset Control Register Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R/W-0, HS — — — — — USBIF USBRF USBWKUP U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — r-1 U-0 r-1 U-0 U-0 U-0 R/W-0 R/W-0 — — USB IDOVEN USB IDVAL — — — — Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHYIDEN VBUS MONEN ASVAL MONEN BSVAL MONEN SEND MONEN USBIE USBRIE USB WKUPEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as ‘0’ bit 26 USBIF: USB General Interrupt Flag bit 1 = An event on the USB Bus has occurred 0 = No interrupt from USB module or interrupts have not been enabled bit 25 USBRF: USB Resume Flag bit 1 = Resume from Suspend state. Device wake-up activity can be started. 0 = No Resume activity detected during Suspend, or not in Suspend state bit 24 USBWKUP: USB Activity Status bit 1 = Connect, disconnect, or other activity on USB detected since last cleared 0 = No activity detected on USB Note: This bit should be cleared just prior to entering sleep, but it should be checked that no activity has already occurred on USB before actually entering sleep. bit 23-16 Unimplemented: Read as ‘0’ bit 15 Reserved: Read as ‘1’ bit 14 Unimplemented: Read as ‘0’ bit 13 Reserved: Read as ‘1’ bit 12-10 Unimplemented: Read as ‘0’ bit 9 USBIDOVEN: USB ID Override Enable bit 1 = Enable use of USBIDVAL bit 0 = Disable use of USBIDVAL and instead use the PHY value bit 8 USBIDVAL: USB ID Value bit 1 = ID override value is 1 0 = ID override value is 0 bit 7 PHYIDEN: PHY ID Monitoring Enable bit 1 = Enable monitoring of the ID bit from the USB PHY 0 = Disable monitoring of the ID bit from the USB PHY bit 6 VBUSMONEN: VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in VBUS Valid range (between 4.4V and 4.75V) 0 = Disable monitoring for VBUS in VBUS Valid range Note: This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. DS60001326B-page 51-52 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 bit 4 BSVALMONEN: B-Device VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session Valid range for B-device (between 0.8V and 4.0V) 0 = Disable monitoring for VBUS in Session Valid range for B-device bit 3 SENDMONEN: Session End VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session End range (between 0.2V and 0.8V) 0 = Disable monitoring for VBUS in Session End range bit 2 USBIE: USB General Interrupt Enable bit 1 = Enables general interrupt from USB module 0 = Disables general interrupt from USB module bit 1 USBRIE: USB Resume Interrupt Enable bit 1 = Enable remote resume from suspend Interrupt 0 = Disable interrupt to a Remote Devices USB resume signaling bit 0 USBWKUPEN: USB Activity Detection Interrupt Enable bit 1 = Enable interrupt for detection of activity on USB bus in Sleep mode 0 = Disable interrupt for detection of activity on USB bus in Sleep mode Note: This register is not available on all devices. Refer to the “USB On-The-GO (OTG)” chapter in the specific device data sheet to determine availability. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-53 Hi-Speed USB with On-The-Go (OTG) Register 51-30: USBCRCON: USB Clock/Reset Control Register (Continued) bit 5 ASVALMONEN: A-Device VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session Valid range for A-device (between 0.8V and 2.0V) 0 = Disable monitoring for VBUS in Session Valid range for A-device PIC32 Family Reference Manual 51.4 EFFECTS OF RESET All forms of Reset force the Hi-Speed USB OTG module registers to the default state. 51.4.1 Device Reset (MCLR) A device Reset forces all Hi-Speed USB OTG module registers to their reset state and turns off the USB module. 51.4.2 Power-on Reset (POR) A POR forces all Hi-Speed USB OTG module registers to their reset state and turns off the USB module. 51.4.3 Watchdog Timer Reset (WDT) A WDT Reset forces all Hi-Speed USB OTG module registers to their reset state and turns off the USB module. 51.5 OPERATION IN POWER-SAVING MODES 51.5.1 Sleep Mode Placing the PIC32 device into Sleep mode while the Hi-Speed USB OTG module is active can result in violating the USB protocol. When the device enters Sleep mode, the clock to the module is maintained. The effect on the CPU clock source is dependent on the USB and CPU clock configuration. • If the CPU and Hi-Speed USB OTG module were using the Primary Oscillator (POSC) source, the CPU is disconnected from the clock source when entering Sleep mode and the oscillator remains in an enabled state for the module • If the CPU was using a different clock source, that clock source is disabled on entering Sleep, and the USB clock source is left enabled To further reduce power consumption, the Hi-Speed USB OTG module can be placed in Suspend mode. This can be done prior to placing the CPU in Sleep mode using the SUSPEN bit (USBCSR0<8>). 51.5.2 Idle Mode When the device enters Idle mode, the CPU clock is turned off, but the clock to the Hi-Speed USB OTG module is maintained when in Idle mode. The module can therefore continue operation while the CPU is in Idle mode. When USB interrupts are generated, the CPU is taken out of Idle mode. DS60001326B-page 51-54 © 2013-2015 Microchip Technology Inc. Section 51. Hi-Speed USB with On-The-Go (OTG) 51 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32 device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Hi-Speed USB with On-The-Go (OTG) module are: Title Application Note # No application notes at this time Note: N/A Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32 family of devices. © 2013-2015 Microchip Technology Inc. DS60001326B-page 51-55 Hi-Speed USB with On-The-Go (OTG) 51.6 PIC32 Family Reference Manual 51.7 REVISION HISTORY Revision A (November 2013) This is the initial released version of this document. Revision B (June 2015) This revision includes the following updates: • The document control number was changed from DS60001232 to DS60001326 • The USBCRCON register was added (see Table 51-1 and Register 51-30) • In addition, minor updates to text and formatting were incorporated throughout the document DS60001326B-page 51-56 © 2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-456-9 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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