PIC32MZ Embedded Connectivity (EC) Family Data Sheet

PIC32MZ Embedded
Connectivity (EC) Family
32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with
Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog
Operating Conditions
Advanced Analog Features
• 2.3V to 3.6V, -40ºC to +85ºC, DC to 200 MHz
•
•
•
•
Core: 200 MHz (up to 330 DMIPS) microAptiv™
•
•
•
•
16 KB I-Cache, 4 KB D-Cache
MMU for optimum embedded OS execution
microMIPS™ mode for up to 35% smaller code size
DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
10-bit ADC resolution and up to 48 analog inputs
Flexible and independent ADC trigger sources
Two comparators with 32 programmable voltage references
Temperature sensor with ±2ºC accuracy
Communication Interfaces
• Two CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (25 Mbps):
- Supports LIN 1.2 and IrDA® protocols
• Six 4-wire SPI modules
• SQI configurable as an additional SPI module (50 MHz)
• Five I2C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Peripheral Pin Select (PPS) to enable function remap
Clock Management
•
•
•
•
Internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timers (WDT) and Deadman
Timer (DMT)
• Fast wake-up and start-up
Timers/Output Compare/Input Capture
• Low-power modes (Sleep and Idle)
• Integrated Power-on Reset and Brown-out Reset
•
•
•
•
•
Memory Interfaces
Input/Output
• 50 MHz External Bus Interface (EBI)
• 50 MHz Serial Quad Interface (SQI)
• 5V-tolerant pins with up to 32 mA source/sink
• Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins
Power Management
Audio and Graphics Interfaces
•
•
•
•
Nine 16-bit or up to four 32-bit timers/counters
Nine Output Compare (OC) modules
Nine Input Capture (IC) modules
PPS to enable function remap
Real-Time Clock and Calendar (RTCC) module
Qualification and Class B Support
Graphics interfaces: EBI or PMP
Audio data communication: I2S, LJ, and RJ
Audio control interfaces: SPI and I2C
Audio master clock: Fractional clock frequencies with USB
synchronization
• Class B Safety Library, IEC 60730
• Back-up internal oscillator
Debugger Development Support
High-Speed (HS) Communication Interfaces 
(with Dedicated DMA)
• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
•
•
•
•
•
Security Features
Software and Tools Support
• Crypto Engine with a RNG for data encryption/decryption
and authentication (AES, 3DES, SHA, MD5, and HMAC)
• Advanced memory protection:
- Peripheral and memory region access control
•
•
•
•
•
Direct Memory Access (DMA)
• Eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
In-circuit and in-application programming
4-wire MIPS® Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
C/C++ compiler with native DSP/fractional support
MPLAB® Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™, and Bluetooth® audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS®
Packages
Type
QFN
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
64
53
0.50 mm
9x9x0.9 mm
TQFP
64
53
0.50 mm
10x10x1 mm
 2013-2016 Microchip Technology Inc.
100
78
0.40 mm
12x12x1 mm
0.50 mm
14x14x1 mm
144
120
0.40 mm
16x16x1 mm
VTLA
LQFP
124
98
0.50 mm
9x9x0.9 mm
144
120
0.50 mm
20x20x1.40 mm
DS60001191F-page 1
PIC32MZ EC FAMILY FEATURES
8/16
2
N
Y
2
Y
Y
8/18
PIC32MZ1024ECG100
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
8/16
1024
PIC32MZ1024ECM100
512
PIC32MZ2048ECG100
PIC32MZ2048ECH100
100
TQFP
160
51
9/9/9
6
6
5
2
N
Y
PIC32MZ2048ECM100
2
Y
Y
8/18
PIC32MZ1024ECG124
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
8/16
PIC32MZ1024ECH124
2048
1024
PIC32MZ1024ECM124
512
PIC32MZ2048ECG124
PIC32MZ2048ECH124
124
VTLA
160
53
9/9/9
6
6
5
 2013-2016 Microchip Technology Inc.
2
N
Y
PIC32MZ2048ECM124
2
Y
Y
8/18
PIC32MZ1024ECG144
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
PIC32MZ1024ECH144
2048
1024
PIC32MZ1024ECM144
512
PIC32MZ2048ECG144
PIC32MZ2048ECH144
144
LQFP,
TQFP
160
2048
PIC32MZ2048ECM144
Note
1:
2:
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
53
9/9/9
6
6
5
Trace
8/12
JTAG
Y
I/O Pins
N
PIC32MZ2048ECM064
PIC32MZ1024ECH100
2048
8/18
0
Ethernet
5
RTCC
4
Y
SQI
6
Y
EBI
9/9/9
8/16
2
PMP
34
8/12
Y
I2C
160
Y
N
USB 2.0 HS OTG
PIC32MZ2048ECH064
64
N
2
Analog Comparators
512
PIC32MZ2048ECG064
TQFP,
QFN
0
ADC (Channels)
PIC32MZ1024ECM064
DMA Channels
(Programmable/
Dedicated)
1024
RNG
PIC32MZ1024ECH064
Crypto
PIC32MZ1024ECG064
CAN 2.0B
External
Interrupts(2)
SPI/I2S
UART
Timers/
Capture/
Compare(1)
Remappable Pins
Boot Flash
Memory (KB)
Packages
Pins
Data
Memory (KB)
Device
Program
Memory (KB)
Remappable Peripherals
24
2
Y
4
Y
N
Y
Y
Y
46
Y
Y
40
2
Y
5
Y
Y
Y
Y
Y
78
Y
Y
48
2
Y
5
Y
Y
Y
Y
Y
97
Y
Y
48
2
Y
5
Y
Y
Y
Y
Y
120
Y
Y
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 2
TABLE 1:
PIC32MZ Embedded Connectivity (EC) Family
Device Pin Tables
TABLE 2:
PIN NAMES FOR 64-PIN DEVICES
64-PIN QFN(4) AND TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)064
PIC32MZ1024EC(G/H/M)064
PIC32MZ1024EC(E/F/K)064
PIC32MZ2048EC(G/H/M)064
64
1
64
QFN(4)
Pin #
Full Pin Name
1
TQFP
Pin #
Full Pin Name
1
AN17/ETXEN/RPE5/PMD5/RE5
33
VBUS
2
AN16/ETXD0/PMD6/RE6
34
VUSB3V3
3
AN15/ETXD1/PMD7/RE7
35
VSS
4
AN14/C1IND/RPG6/SCK2/PMA5/RG6
36
D-
5
AN13/C1INC/RPG7/SDA4/PMA4/RG7
37
D+
6
AN12/C2IND/RPG8/SCL4/PMA3/RG8
38
RPF3/USBID/RF3
7
VSS
39
VDD
8
VDD
40
VSS
9
MCLR
41
RPF4/SDA5/PMA9/RF4
10
AN11/C2INC/RPG9/PMA2/RG9
42
RPF5/SCL5/PMA8/RF5
11
AN45/C1INA/RPB5/RB5
43
AERXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9
12
AN4/C1INB/RB4
44
ECOL/RPD10/SCL1/SCK4/RD10
13
AN3/C2INA/RPB3/RB3
45
AERXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11
14
AN2/C2INB/RPB2/RB2
46
AERXD1/ETXD3/RPD0/RTCC/INT0/RD0
15
PGEC1/VREF-/CVREF-/AN1/RPB1/RB1
47
SOSCI/RPC13/RC13
16
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0
48
SOSCO/RPC14/T1CK/RC14
17
PGEC2/AN46/RPB6/RB6
49
EMDIO/AEMDIO/RPD1/SCK1/RD1
18
PGED2/AN47/RPB7/RB7
50
ETXERR/AETXEN/RPD2/SDA3/RD2
19
AVDD
51
AERXERR/ETXCLK/RPD3/SCL3/RD3
20
AVss
52
SQICS0/RPD4/PMWR/RD4
21
AN48/RPB8/PMA10/RB8
53
SQICS1/RPD5/PMRD/RD5
22
AN49/RPB9/PMA7/RB9
54
VDD
23
TMS/CVREFOUT/AN5/RPB10/PMA13/RB10
55
VSS
24
TDO/AN6/PMA12/RB11
56
ERXD3/AETXD1/RPF0/RF0
25
VSS
57
TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1
26
VDD
58
TRD0/SQID0/ERXD1/PMD0/RE0
27
TCK/AN7/PMA11/RB12
59
VSS
28
TDI/AN8/RB13
60
VDD
29
AN9/RPB14/SCK3/PMA1/RB14
61
TRD1/SQID1/ERXD0/PMD1/RE1
30
AN10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15
62
TRD2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2
31
OSC1/CLKI/RC12
63
TRD3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3
OSC2/CLKO/RC15
64
AN18/ERXERR/PMD4/RE4
32
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 3
PIC32MZ Embedded Connectivity (EC) Family
TABLE 3:
PIN NAMES FOR 100-PIN DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)100
PIC32MZ1024EC(G/H/M)100
PIC32MZ1024EC(E/F/K)100
PIC32MZ2048EC(G/H/M)100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AN23/AERXERR/RG15
36
VSS
2
EBIA5/AN34/PMA5/RA5
37
VDD
3
EBID5/AN17/RPE5/PMD5/RE5
38
TCK/EBIA19/AN29/RA1
4
EBID6/AN16/PMD6/RE6
39
TDI/EBIA18/AN30/RPF13/SCK5/RF13
5
EBID7/AN15/PMD7/RE7
40
TDO/EBIA17/AN31/RPF12/RF12
6
EBIA6/AN22/RPC1/PMA6/RC1
41
EBIA11/AN7/ERXD0/AECRS/PMA11/RB12
7
EBIA12/AN21/RPC2/PMA12/RC2
42
AN8/ERXD1/AECOL/RB13
8
EBIWE/AN20/RPC3/PMWR/RC3
43
EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14
9
EBIOE/AN19/RPC4/PMRD/RC4
44
EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15
10
AN14/C1IND/ECOL/RPG6/SCK2/RG6
45
VSS
11
EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7
46
VDD
12
EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/
AECRSDV/RPG8/SCL4/PMA3/RG8
47
AN32/AETXD0/RPD14/RD14
13
VSS
48
AN33/AETXD1/RPD15/SCK6/RD15
14
VDD
49
OSC1/CLKI/RC12
15
MCLR
50
OSC2/CLKO/RC15
16
EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/
AEREFCLK/RPG9/PMA2/RG9
51
VBUS
17
TMS/EBIA16/AN24/RA0
52
VUSB3V3
18
AN25/AERXD0/RPE8/RE8
53
VSS
19
AN26/AERXD1/RPE9/RE9
54
D-
20
AN45/C1INA/RPB5/RB5
55
D+
21
AN4/C1INB/RB4
56
RPF3/USBID/RF3
22
AN3/C2INA/RPB3/RB3
57
EBIRDY3/RPF2/SDA3/RF2
23
AN2/C2INB/RPB2/RB2
58
EBIRDY2/RPF8/SCL3/RF8
24
PGEC1/AN1/RPB1/RB1
59
EBICS0/SCL2/RA2
25
PGED1/AN0/RPB0/RB0
60
EBIRDY1/SDA2/RA3
26
PGEC2/AN46/RPB6/RB6
61
EBIA14/PMCS1/PMA14/RA4
27
PGED2/AN47/RPB7/RB7
62
VDD
28
VREF-/CVREF-/AN27/AERXD2/RA9
63
VSS
29
VREF+/CVREF+/AN28/AERXD3/RA10
64
EBIA9/RPF4/SDA5/PMA9/RF4
30
AVDD
65
EBIA8/RPF5/SCL5/PMA8/RF5
31
AVSS
66
AETXCLK/RPA14/SCL1/RA14
32
EBIA10/AN48/RPB8/PMA10/RB8
67
AETXEN/RPA15/SDA1/RA15
33
EBIA7/AN49/RPB9/PMA7/RB9
68
EBIA15/RPD9/PMCS2/PMA15/RD9
34
EBIA13/CVREFOUT/AN5/RPB10/PMA13/RB10
69
RPD10/SCK4/RD10
35
AN6/ERXERR/AETXERR/RB11
70
EMDC/AEMDC/RPD11/RD11
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
DS60001191F-page 4
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 3:
PIN NAMES FOR 100-PIN DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)100
PIC32MZ1024EC(G/H/M)100
PIC32MZ1024EC(E/F/K)100
PIC32MZ2048EC(G/H/M)100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
71
EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0
86
EBID10/ETXD0/RPF1/PMD10/RF1
72
SOSCI/RPC13/RC13
87
EBID9/ETXERR/RPG1/PMD9/RG1
73
SOSCO/RPC14/T1CK/RC14
88
EBID8/RPG0/PMD8/RG0
74
VDD
89
TRCLK/SQICLK/RA6
75
VSS
90
TRD3/SQID3/RA7
76
RPD1/SCK1/RD1
91
EBID0/PMD0/RE0
77
EBID14/ETXEN/RPD2/PMD14/RD2
92
VSS
78
EBID15/ETXCLK/RPD3/PMD15/RD3
93
VDD
79
EBID12/ETXD2/RPD12/PMD12/RD12
94
EBID1/PMD1/RE1
80
EBID13/ETXD3/PMD13/RD13
95
TRD2/SQID2/RG14
81
SQICS0/RPD4/RD4
96
TRD1/SQID1/RG12
82
SQICS1/RPD5/RD5
97
TRD0/SQID0/RG13
83
VDD
98
EBID2/PMD2/RE2
84
VSS
99
EBID3/RPE3/PMD3/RE3
85
EBID11/ETXD1/RPF0/PMD11/RF0
100
EBID4/AN18/PMD4/RE4
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 5
PIC32MZ Embedded Connectivity (EC) Family
TABLE 4:
PIN NAMES FOR 124-PIN DEVICES
A34
124-PIN VTLA (BOTTOM VIEW)
A17
B29
B13
PIC32MZ0512EC(E/F/K)124
PIC32MZ1024EC(G/H/M)124
PIC32MZ1024EC(E/F/K)124
PIC32MZ2048EC(G/H/M)124
B56
Full Pin Name
A51
A1
A68
Polarity Indicator
Package
Pin #
B41
B1
Package
Pin #
Full Pin Name
A1
No Connect
A35
A2
AN23/RG15
A36
VBUS
VUSB3V3
A3
EBID5/AN17/RPE5/PMD5/RE5
A37
D-
A4
EBID7/AN15/PMD7/RE7
A38
RPF3/USBID/RF3
A5
AN35/ETXD0/RJ8
A39
EBIRDY2/RPF8/SCL3/RF8
A6
EBIA12/AN21/RPC2/PMA12/RC2
A40
ERXD3/RH9
A7
EBIOE/AN19/RPC4/PMRD/RC4
A41
EBICS0/SCL2/RA2
A8
EBIA4/AN13/C1INC/RPG7/SDA4/PMA4/RG7
A42
EBIA14/PMCS1/PMA14/RA4
A9
VSS
A43
VSS
A10
MCLR
A44
EBIA8/RPF5/SCL5/PMA8/RF5
A11
TMS/EBIA16/AN24/RA0
A45
RPA15/SDA1/RA15
A12
AN26/RPE9/RE9
A46
RPD10/SCK4/RD10
A13
AN4/C1INB/RB4
A47
ECRS/RH12
A14
AN3/C2INA/RPB3/RB3
A48
RPD0/RTCC/INT0/RD0
A15
VDD
A49
SOSCO/RPC14/T1CK/RC14
A16
AN2/C2INB/RPB2/RB2
A50
VDD
A17
PGEC1/AN1/RPB1/RB1
A51
VSS
A18
PGED1/AN0/RPB0/RB0
A52
RPD1/SCK1/RD1
A19
PGED2/AN47/RPB7/RB7
A53
EBID15/RPD3/PMD15/RD3
A20
VREF+/CVREF+/AN28/RA10
A54
EBID13/PMD13/RD13
A21
AVSS
A55
EMDIO/RJ1
A22
AN39/ETXD3/RH1
A56
SQICS0/RPD4/RD4
A23
EBIA7/AN49/RPB9/PMA7/RB9
A57
ETXEN/RPD6/RD6
A24
AN6/RB11
A58
VDD
A25
VDD
A59
EBID11/RPF0/PMD11/RF0
A26
TDI/EBIA18/AN30/RPF13/SCK5/RF13
A60
EBID9/RPG1/PMD9/RG1
A27
EBIA11/AN7/PMA11/RB12
A61
TRCLK/SQICLK/RA6
A28
EBIA1/AN9/RPB14/SCK3/PMA1/RB14
A62
RJ4
A29
VSS
A63
VSS
A30
AN40/ERXERR/RH4
A64
EBID1/PMD1/RE1
A31
AN42/ERXD2/RH6
A65
TRD1/SQID1/RG12
A32
AN33/RPD15/SCK6/RD15
A66
EBID2/SQID2/PMD2/RE2
A33
OSC2/CLKO/RC15
A67
EBID4/AN18/PMD4/RE4
No Connect
A68
No Connect
A34
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS60001191F-page 6
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 4:
PIN NAMES FOR 124-PIN DEVICES (CONTINUED)
A34
124-PIN VTLA (BOTTOM VIEW)
A17
B13
PIC32MZ0512EC(E/F/K)124
PIC32MZ1024EC(G/H/M)124
PIC32MZ1024EC(E/F/K)124
PIC32MZ2048EC(G/H/M)124
Full Pin Name
B41
B1
B56
A51
A1
A68
Polarity Indicator
Package
Pin #
B29
Package
Pin #
Full Pin Name
B1
EBIA5/AN34/PMA5/RA5
B29
VSS
B2
EBID6/AN16/PMD6/RE6
B30
D+
B3
EBIA6/AN22/RPC1/PMA6/RC1
B31
RPF2/SDA3/RF2
B4
AN36/ETXD1/RJ9
B32
ERXD0/RH8
B5
EBIWE/AN20/RPC3/PMWR/RC3
B33
ECOL/RH10
B6
AN14/C1IND/RPG6/SCK2/RG6
B34
EBIRDY1/SDA2/RA3
B7
EBIA3/AN12/C2IND/RPG8/SCL4/PMA3/RG8
B35
VDD
B8
VDD
B36
EBIA9/RPF4/SDA5/PMA9/RF4
RPA14/SCL1/RA14
B9
EBIA2/AN11/C2INC/RPG9/PMA2/RG9
B37
B10
AN25/RPE8/RE8
B38
EBIA15/RPD9/PMCS2/PMA15/RD9
B11
AN45/C1INA/RPB5/RB5
B39
EMDC/RPD11/RD11
B12
AN37/ERXCLK/EREFCLK/RJ11
B40
ERXDV/ECRSDV/RH13
B13
VSS
B41
SOSCI/RPC13/RC13
B14
PGEC2/AN46/RPB6/RB6
B42
EBID14/RPD2/PMD14/RD2
B15
VREF-/CVREF-/AN27/RA9
B43
EBID12/RPD12/PMD12/RD12
B16
AVDD
B44
ETXERR/RJ0
B17
AN38/ETXD2/RH0
B45
EBIRDY3/RJ2
B18
EBIA10/AN48/RPB8/PMA10/RB8
B46
SQICS1/RPD5/RD5
B19
EBIA13/CVREFOUT/AN5/RPB10/PMA13/RB10
B47
ETXCLK/RPD7/RD7
B20
VSS
B48
VSS
B21
TCK/EBIA19/AN29/RA1
B49
EBID10/RPF1/PMD10/RF1
B22
TDO/EBIA17/AN31/RPF12/RF12
B50
EBID8/RPG0/PMD8/RG0
B23
AN8/RB13
B51
TRD3/SQID3/RA7
B24
EBIA0/AN10/RPB15/OCFB/PMA0/RB15
B52
EBID0/PMD0/RE0
B25
VDD
B53
VDD
B26
AN41/ERXD1/RH5
B54
TRD2/SQID2/RG14
B27
AN32/AETXD0/RPD14/RD14
B55
TRD0/SQID0/RG13
B28
OSC1/CLKI/RC12
B56
EBID3/RPE3/PMD3/RE3
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 7
PIC32MZ Embedded Connectivity (EC) Family
TABLE 5:
PIN NAMES FOR 144-PIN DEVICES
144-PIN LQFP AND TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)144
PIC32MZ1024EC(G/H/M)144
PIC32MZ1024EC(E/F/K)144
PIC32MZ2048EC(G/H/M)144
144
1
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
1
AN23/RG15
37
PGEC2/AN46/RPB6/RB6
2
EBIA5/AN34/PMA5/RA5
38
PGED2/AN47/RPB7/RB7
3
4
EBID5/AN17/RPE5/PMD5/RE5
EBID6/AN16/PMD6/RE6
39
40
VREF-/CVREF-/AN27/RA9
VREF+/CVREF+/AN28/RA10
5
EBID7/AN15/PMD7/RE7
41
AVDD
6
EBIA6/AN22/RPC1/PMA6/RC1
42
AVSS
7
AN35/ETXD0/RJ8
43
AN38/ETXD2/RH0
8
AN36/ETXD1/RJ9
44
AN39/ETXD3/RH1
9
EBIBS0/RJ12
45
EBIRP/RH2
10
11
EBIBS1/RJ10
EBIA12/AN21/RPC2/PMA12/RC2
46
47
RH3
EBIA10/AN48/RPB8/PMA10/RB8
12
EBIWE/AN20/RPC3/PMWR/RC3
13
EBIOE/AN19/RPC4/PMRD/RC4
48
49
EBIA7/AN49/RPB9/PMA7/RB9
CVREFOUT/AN5/RPB10/RB10
14
15
AN14/C1IND/RPG6/SCK2/RG6
AN13/C1INC/RPG7/SDA4/RG7
50
51
AN6/RB11
EBIA1/PMA1/RK1
16
AN12/C2IND/RPG8/SCL4/RG8
52
EBIA3/PMA3/RK2
17
VSS
53
EBIA17/RK3
18
19
VDD
EBIA16/RK0
54
55
VSS
VDD
20
21
MCLR
EBIA2/AN11/C2INC/RPG9/PMA2/RG9
56
57
TCK/AN29/RA1
TDI/AN30/RPF13/SCK5/RF13
22
23
TMS/AN24/RA0
AN25/RPE8/RE8
58
59
TDO/AN31/RPF12/RF12
AN7/RB12
24
25
AN26/RPE9/RE9
AN45/C1INA/RPB5/RB5
60
61
AN8/RB13
AN9/RPB14/SCK3/RB14
26
AN4/C1INB/RB4
62
AN10/RPB15/OCFB/RB15
27
AN37/ERXCLK/EREFCLK/RJ11
63
VSS
28
EBIA13/PMA13/RJ13
64
VDD
29
30
EBIA11/PMA11/RJ14
EBIA0/PMA0/RJ15
65
66
AN40/ERXERR/RH4
AN41/ERXD1/RH5
31
32
AN3/C2INA/RPB3/RB3
VSS
67
AN42/ERXD2/RH6
68
EBIA4/PMA4/RH7
33
34
VDD
AN2/C2INB/RPB2/RB2
69
70
AN32/RPD14/RD14
AN33/RPD15/SCK6/RD15
35
PGEC1/AN1/RPB1/RB1
71
OSC1/CLKI/RC12
36
PGED1/AN0/RPB0/RB0
72
OSC2/CLKO/RC15
Note 1:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
2:
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more
information.
3:
Shaded pins are 5V tolerant.
DS60001191F-page 8
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 5:
PIN NAMES FOR 144-PIN DEVICES (CONTINUED)
144-PIN LQFP AND TQFP (TOP VIEW)
PIC32MZ0512EC(E/F/K)144
PIC32MZ1024EC(G/H/M)144
PIC32MZ1024EC(E/F/K)144
PIC32MZ2048EC(G/H/M)144
144
1
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
73
VBUS
109
RPD1/SCK1/RD1
74
VUSB3V3
75
VSS
110
111
EBID14/RPD2/PMD14/RD2
EBID15/RPD3/PMD15/RD3
76
D-
77
D+
112
113
EBID12/RPD12/PMD12/RD12
EBID13/PMD13/RD13
78
RPF3/USBID/RF3
79
SDA3/RPF2/RF2
114
115
ETXERR/RJ0
EMDIO/RJ1
80
81
SCL3/RPF8/RF8
ERXD0/RH8
116
117
EBIRDY3/RJ2
EBIA22/RJ3
82
ERXD3/RH9
118
SQICS0/RPD4/RD4
83
84
ECOL/RH10
EBIRDY2/RH11
119
120
SQICS1/RPD5/RD5
ETXEN/RPD6/RD6
85
86
SCL2/RA2
EBIRDY1/SDA2/RA3
121
122
ETXCLK/RPD7/RD7
VDD
87
EBIA14/PMCS1/PMA14/RA4
123
VSS
88
VDD
124
EBID11/RPF0/PMD11/RF0
89
VSS
125
EBID10/RPF1/PMD10/RF1
90
EBIA9/RPF4/SDA5/PMA9/RF4
126
EBIA21/RK7
91
92
EBIA8/RPF5/SCL5/PMA8/RF5
EBIA18/RK4
127
128
EBID9/RPG1/PMD9/RG1
EBID8/RPG0/PMD8/RG0
93
EBIA19/RK5
129
TRCLK/SQICLK/RA6
94
95
EBIA20/RK6
RPA14/SCL1/RA14
130
131
TRD3/SQID3/RA7
EBICS0/RJ4
96
97
RPA15/SDA1/RA15
EBIA15/RPD9/PMCS2/PMA15/RD9
132
133
EBICS1/RJ5
EBICS2/RJ6
98
99
RPD10/SCK4/RD10
EMDC/RPD11/RD11
134
135
EBICS3/RJ7
EBID0/PMD0/RE0
100
101
ECRS/RH12
ERXDV/ECRSDV/RH13
136
137
VSS
VDD
102
RH14
138
EBID1/PMD1/RE1
103
104
EBIA23/RH15
RPD0/RTCC/INT0/RD0
139
140
TRD2/SQID2/RG14
TRD1/SQID1/RG12
105
SOSCI/RPC13/RC13
106
SOSCO/RPC14/T1CK/RC14
141
142
TRD0/SQID0/RG13
EBID2/PMD2/RE2
107
VDD
108
VSS
143
144
EBID3/RPE3/PMD3/RE3
EBID4/AN18/PMD4/RE4
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 9
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 10
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 37
3.0 CPU............................................................................................................................................................................................ 47
4.0 Memory Organization ................................................................................................................................................................. 59
5.0 Flash Program Memory.............................................................................................................................................................. 97
6.0 Resets ...................................................................................................................................................................................... 107
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................. 113
8.0 Oscillator Configuration ............................................................................................................................................................ 149
9.0 Prefetch Module ....................................................................................................................................................................... 161
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 165
11.0 Hi-Speed USB with On-The-Go (OTG) .................................................................................................................................... 189
12.0 I/O Ports ................................................................................................................................................................................... 237
13.0 Timer1 ...................................................................................................................................................................................... 273
14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9............................................................................................................................ 277
15.0 Deadman Timer (DMT) ............................................................................................................................................................ 283
16.0 Watchdog Timer (WDT) ........................................................................................................................................................... 291
17.0 Input Capture............................................................................................................................................................................ 295
18.0 Output Compare....................................................................................................................................................................... 299
19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)....................................................................................................... 305
20.0 Serial Quad Interface (SQI)...................................................................................................................................................... 315
21.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 339
22.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 347
23.0 Parallel Master Port (PMP)....................................................................................................................................................... 355
24.0 External Bus Interface (EBI)..................................................................................................................................................... 365
25.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 373
26.0 Crypto Engine........................................................................................................................................................................... 383
27.0 Random Number Generator (RNG) ......................................................................................................................................... 403
28.0 Pipelined Analog-to-Digital Converter (ADC) ........................................................................................................................... 409
29.0 Controller Area Network (CAN) ................................................................................................................................................ 439
30.0 Ethernet Controller ................................................................................................................................................................... 477
31.0 Comparator .............................................................................................................................................................................. 521
32.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 525
33.0 Power-Saving Features ........................................................................................................................................................... 529
34.0 Special Features ...................................................................................................................................................................... 535
35.0 Instruction Set .......................................................................................................................................................................... 559
36.0 Development Support............................................................................................................................................................... 561
37.0 Electrical Characteristics .......................................................................................................................................................... 565
38.0 AC and DC Characteristics Graphs.......................................................................................................................................... 613
39.0 Packaging Information.............................................................................................................................................................. 615
The Microchip Web Site ..................................................................................................................................................................... 663
Customer Change Notification Service .............................................................................................................................................. 663
Customer Support .............................................................................................................................................................................. 663
Product Identification System ............................................................................................................................................................ 664
 2013-2016 Microchip Technology Inc.
DS60001191F-page 11
PIC32MZ Embedded Connectivity (EC) Family
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS60001191F-page 12
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the following documents, refer
to the Documentation > Reference
Manuals section of the Microchip PIC32
website: http://www.microchip.com/pic32.
Section 1. “Introduction” (DS60001127)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupt Controller” (DS60001108)
Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114)
Section 10. “Power-Saving Features” (DS60001130)
Section 12. “I/O Ports” (DS60001120)
Section 13. “Parallel Master Port (PMP)” (DS60001128)
Section 14. “Timers” (DS60001105)
Section 15. “Input Capture” (DS60001122)
Section 16. “Output Compare” (DS60001111)
Section 18. “12-bit Pipelined Analog-to-Digital Converter (ADC)” (DS60001194)
Section 19. “Comparator” (DS60001110)
Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
Section 32. “Configuration” (DS60001124)
Section 33. “Programming and Diagnostics” (DS60001129)
Section 34. “Controller Area Network (CAN)” (DS60001154)
Section 35. “Ethernet Controller” (DS60001155)
Section 41. “Prefetch Module for Devices with L1 CPU Cache” (DS60001183)
Section 42. “Oscillators with Enhanced PLL” (DS60001250)
Section 46. “Serial Quad Interface (SQI)” (DS60001244)
Section 47. “External Bus Interface (EBI)” (DS60001245)
Section 48. “Memory Organization and Permissions” (DS60001214)
Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246)
Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192)
Section 51. “Hi-Speed USB with On-The-Go (OTG)” (DS60001326)
Section 52. “Flash Program Memory with Support for Live Update” (DS60001193)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 13
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 14
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
1.0
DEVICE OVERVIEW
Note:
This data sheet contains device-specific information for
PIC32MZ Embedded Connectivity (EC) devices.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the documents provided in
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 1-1:
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MZ EC family
of devices.
Table 1-21 through Table 1-22 list the pinout I/O
descriptions for the pins shown in the device pin tables
(see Table 2 through Table 5).
PIC32MZ EC FAMILY BLOCK DIAGRAM
OSC2/CLKO
OSC1/CLKI
POSC/SOSC
Oscillators
FRC/LPRC
Oscillators
DIVIDERS
PLL-USB
Power-on
Reset
PBCLKx
Timing
Generation
PORTA
Watchdog
Timer
SYSCLK
6
MCLR
Oscillator
Start-up Timer
Precision
Band Gap
Reference
PLL
VDD, VSS
Power-up
Timer
Voltage
Regulator
PORTB
PORTC
Brown-out
Reset
PORTD
PORTE
PORTF
EVIC
PORTH
PORTJ
Ethernet
Controller
CAN1
CAN2
I-Cache D-Cache
SQI
DMAC
MIPS32®
microAptiv™ Core
HS USB
INT
CRYPTO
EJTAG
PORTG
PORTK
Peripheral
Bus 5
System Bus I/F
I1,
I2
I3, I5, I14 T12 I12, T11 I7 T10
I4 I6
I11
I10
I8
I9
T9
Peripheral
Bus 4
T8
System Bus
Peripheral Bus 1
CFG
PPS
ICD
WDT
DMT
RTCC
Note:
Flash
Controller
T1
Flash
Prefetch
Cache
T2
T3
Data
Ram
Bank 1
Data
Ram
Bank 2
T4
T13
T6
Peripheral
Bus 2
RNG
I13
EBI
T5
T7
Peripheral
Bus 3
Timer1-9
128
128
PFM Flash Wrapper
and ECC
140-bit Wide
Dual Panel
Flash Memory
CVREF
JTAG
BSCAN
SPI1-6
OC1-9
I2C1-5
IC1-9
UART1-6
Comparator
1-2
PMP
6 S&H
ADC
Not all features are available on all devices. Refer to TABLE 1: “PIC32MZ EC Family Features” for the list of features by device.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 15
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-1:
ADC1 PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AN0
16
25
A18
36
I
Analog
AN1
15
24
A17
35
I
Analog
AN2
14
23
A16
34
I
Analog
AN3
13
22
A14
31
I
Analog
AN4
12
21
A13
26
I
Analog
AN5
23
34
B19
49
I
Analog
AN6
24
35
A24
50
I
Analog
AN7
27
41
A27
59
I
Analog
AN8
28
42
B23
60
I
Analog
Pin Name
AN9
29
43
A28
61
I
Analog
AN10
30
44
B24
62
I
Analog
AN11
10
16
B9
21
I
Analog
AN12
6
12
B7
16
I
Analog
AN13
5
11
A8
15
I
Analog
AN14
4
10
B6
14
I
Analog
AN15
3
5
A4
5
I
Analog
AN16
2
4
B2
4
I
Analog
AN17
1
3
A3
3
I
Analog
AN18
64
100
A67
144
I
Analog
AN19
—
9
A7
13
I
Analog
AN20
—
8
B5
12
I
Analog
AN21
—
7
A6
11
I
Analog
AN22
—
6
B3
6
I
Analog
AN23
—
1
A2
1
I
Analog
AN24
—
17
A11
22
I
Analog
AN25
—
18
B10
23
I
Analog
AN26
—
19
A12
24
I
Analog
AN27
—
28
B15
39
I
Analog
AN28
—
29
A20
40
I
Analog
AN29
—
38
B21
56
I
Analog
AN30
—
39
A26
57
I
Analog
AN31
—
40
B22
58
I
Analog
AN32
—
47
B27
69
I
Analog
AN33
—
48
A32
70
I
Analog
AN34
—
2
B1
2
I
Analog
AN35
—
—
A5
7
I
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 16
Description
Analog Input Channels
Analog
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-1:
ADC1 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AN36
—
—
B4
8
I
Analog
AN37
—
—
B12
27
I
Analog
AN38
—
—
B17
43
I
Analog
AN39
—
—
A22
44
I
Analog
AN40
—
—
A30
65
I
Analog
AN41
—
—
B26
66
I
Analog
AN42
—
—
A31
67
I
Analog
AN45
11
20
B11
25
I
Analog
AN46
17
26
B14
37
I
Analog
AN47
18
27
A19
38
I
Analog
AN48
21
32
B18
47
I
Analog
AN49
22
33
A23
48
I
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
Description
Analog Input Channels
Analog
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 17
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-2:
OSCILLATOR PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
CLKI
31
49
B28
71
I
CLKO
32
50
A33
72
O
OSC1
31
49
B28
71
I
OSC2
32
50
A33
72
O
SOSCI
47
72
B41
105
I
SOSCO
48
73
A49
106
O
REFCLKI1
PPS
PPS
PPS
PPS
REFCLKI3
PPS
PPS
PPS
PPS
Pin Name
Buffer
Type
ST/CMOS External clock source input. Always associated with
OSC1 pin function.
—
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions
as CLKO in RC and EC modes.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS
otherwise.
—
32.768 low-power oscillator crystal output.
I
—
Reference Clock Generator Inputs 1-4
I
—
PPS
PPS
PPS
PPS
I
—
REFCLKO1
PPS
PPS
PPS
PPS
O
—
REFCLKO3
PPS
PPS
PPS
PPS
O
—
REFCLKO4
PPS
PPS
PPS
PPS
O
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-3:
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions
as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when configured in
RC mode; CMOS otherwise.
REFCLKI4
Legend:
Description
Reference Clock Generator Outputs 1-4
—
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
IC1
PPS
PPS
PPS
PPS
I
ST
IC2
PPS
PPS
PPS
PPS
I
ST
IC3
PPS
PPS
PPS
PPS
I
ST
IC4
PPS
PPS
PPS
PPS
I
ST
IC5
PPS
PPS
PPS
PPS
I
ST
IC6
PPS
PPS
PPS
PPS
I
ST
IC7
PPS
PPS
PPS
PPS
I
ST
IC8
PPS
PPS
PPS
PPS
I
ST
IC9
PPS
PPS
PPS
PPS
I
Pin Name
Description
Input Capture
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 18
Input Capture Inputs 1-9
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-4:
OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
OC1
PPS
PPS
PPS
PPS
O
—
OC2
PPS
PPS
PPS
PPS
O
—
OC3
PPS
PPS
PPS
PPS
O
—
OC4
PPS
PPS
PPS
PPS
O
—
OC5
PPS
PPS
PPS
PPS
O
—
OC6
PPS
PPS
PPS
PPS
O
—
OC7
PPS
PPS
PPS
PPS
O
—
OC8
PPS
PPS
PPS
PPS
O
—
OC9
PPS
PPS
PPS
PPS
O
—
OCFA
PPS
PPS
PPS
PPS
I
ST
Output Compare Fault A Input
OCFB
30
44
B24
62
I
ST
Output Compare Fault B Input
Pin Name
Description
Output Compare
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-5:
Output Compare Outputs 1-9
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
INT0
46
71
A48
104
I
ST
External Interrupt 0
INT1
PPS
PPS
PPS
PPS
I
ST
External Interrupt 1
INT2
PPS
PPS
PPS
PPS
I
ST
External Interrupt 2
INT3
PPS
PPS
PPS
PPS
I
ST
External Interrupt 3
INT4
PPS
PPS
PPS
PPS
I
ST
External Interrupt 4
Pin Name
Description
External Interrupts
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 19
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RA0
—
17
A11
22
I/O
ST
RA1
—
38
B21
56
I/O
ST
RA2
—
59
A41
85
I/O
ST
RA3
—
60
B34
86
I/O
ST
RA4
—
61
A42
87
I/O
ST
RA5
—
2
B1
2
I/O
ST
RA6
—
89
A61
129
I/O
ST
Pin Name
Buffer
Type
Description
PORTA
RA7
—
90
B51
130
I/O
ST
RA9
—
28
B15
39
I/O
ST
RA10
—
29
A20
40
I/O
ST
RA14
—
66
B37
95
I/O
ST
RA15
—
67
A45
96
I/O
ST
PORTA is a bidirectional I/O port
PORTB
RB0
16
25
A18
36
I/O
ST
RB1
15
24
A17
35
I/O
ST
RB2
14
23
A16
34
I/O
ST
RB3
13
22
A14
31
I/O
ST
RB4
12
21
A13
26
I/O
ST
RB5
11
20
B11
25
I/O
ST
RB6
17
26
B14
37
I/O
ST
RB7
18
27
A19
38
I/O
ST
RB8
21
32
B18
47
I/O
ST
RB9
22
33
A23
48
I/O
ST
RB10
23
34
B19
49
I/O
ST
RB11
24
35
A24
50
I/O
ST
RB12
27
41
A27
59
I/O
ST
RB13
28
42
B23
60
I/O
ST
RB14
29
43
A28
61
I/O
ST
RB15
30
44
B24
62
I/O
ST
PORTB is a bidirectional I/O port
PORTC
RC1
—
6
B3
6
I/O
ST
RC2
—
7
A6
11
I/O
ST
RC3
—
8
B5
12
I/O
ST
RC4
—
9
A7
13
I/O
ST
RC12
31
49
B28
71
I/O
ST
RC13
47
72
B41
105
I/O
ST
RC14
48
73
A49
106
I/O
ST
RC15
32
50
A33
72
I/O
ST
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 20
PORTC is a bidirectional I/O port
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RD0
46
71
A48
104
I/O
ST
RD1
49
76
A52
109
I/O
ST
Pin Name
Buffer
Type
Description
PORTD
RD2
50
77
B42
110
I/O
ST
RD3
51
78
A53
111
I/O
ST
RD4
52
81
A56
118
I/O
ST
RD5
53
82
B46
119
I/O
ST
RD6
—
—
A57
120
I/O
ST
ST
RD7
—
—
B47
121
I/O
RD9
43
68
B38
97
I/O
ST
RD10
44
69
A46
98
I/O
ST
RD11
45
70
B39
99
I/O
ST
RD12
—
79
B43
112
I/O
ST
RD13
—
80
A54
113
I/O
ST
RD14
—
47
B27
69
I/O
ST
RD15
—
48
A32
70
I/O
ST
PORTD is a bidirectional I/O port
PORTE
RE0
58
91
B52
135
I/O
ST
RE1
61
94
A64
138
I/O
ST
RE2
62
98
A66
142
I/O
ST
RE3
63
99
B56
143
I/O
ST
RE4
64
100
A67
144
I/O
ST
RE5
1
3
A3
3
I/O
ST
RE6
2
4
B2
4
I/O
ST
RE7
3
5
A4
5
I/O
ST
RE8
—
18
B10
23
I/O
ST
RE9
—
19
A12
24
I/O
PORTE is a bidirectional I/O port
ST
PORTF
RF0
56
85
A59
124
I/O
ST
RF1
57
86
B49
125
I/O
ST
RF2
—
57
B31
79
I/O
ST
RF3
38
56
A38
78
I/O
ST
RF4
41
64
B36
90
I/O
ST
RF5
42
65
A44
91
I/O
ST
RF8
—
58
A39
80
I/O
ST
RF12
—
40
B22
58
I/O
ST
—
39
A26
57
I/O
RF13
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
PORTF is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 21
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RG0
—
88
B50
128
I/O
ST
RG1
—
87
A60
127
I/O
ST
RG6
4
10
B6
14
I/O
ST
RG7
5
11
A8
15
I/O
ST
RG8
6
12
B7
16
I/O
ST
RG9
10
16
B9
21
I/O
ST
RG12
—
96
A65
140
I/O
ST
RG13
—
97
B55
141
I/O
ST
RG14
—
95
B54
139
I/O
ST
RG15
—
1
A2
1
I/O
ST
RH0
—
—
B17
43
I/O
ST
RH1
—
—
A22
44
I/O
ST
RH2
—
—
—
45
I/O
ST
RH3
—
—
—
46
I/O
ST
RH4
—
—
A30
65
I/O
ST
RH5
—
—
B26
66
I/O
ST
RH6
—
—
A31
67
I/O
ST
RH7
—
—
—
68
I/O
ST
RH8
—
—
B32
81
I/O
ST
Pin Name
Buffer
Type
Description
PORTG
PORTG is a bidirectional I/O port
PORTH
RH9
—
—
A40
82
I/O
ST
RH10
—
—
B33
83
I/O
ST
RH11
—
—
—
84
I/O
ST
RH12
—
—
A47
100
I/O
ST
RH13
—
—
B40
101
I/O
ST
RH14
—
—
—
102
I/O
ST
RH15
—
—
—
103
I/O
PORTH is a bidirectional I/O port
ST
PORTJ
RJ0
—
—
B44
114
I/O
ST
RJ1
—
—
A55
115
I/O
ST
RJ2
—
—
B45
116
I/O
ST
RJ3
—
—
—
117
I/O
ST
RJ4
—
—
A62
131
I/O
ST
RJ5
—
—
—
132
I/O
ST
RJ6
—
—
—
133
I/O
ST
RJ7
—
—
—
134
I/O
ST
RJ8
—
—
A5
7
I/O
ST
RJ9
—
—
B4
8
I/O
ST
RJ10
—
—
—
10
I/O
ST
RJ11
—
—
B12
27
I/O
ST
RJ12
—
—
—
9
I/O
ST
RJ13
—
—
—
28
I/O
ST
RJ14
—
—
—
29
I/O
ST
RJ15
—
—
—
30
I/O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 22
PORTJ is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RK0
—
—
—
19
I/O
ST
RK1
—
—
—
51
I/O
ST
RK2
—
—
—
52
I/O
ST
RK3
—
—
—
53
I/O
ST
RK4
—
—
—
92
I/O
ST
RK5
—
—
—
93
I/O
ST
RK6
—
—
—
94
I/O
ST
RK7
—
—
—
126
I/O
Pin Name
Buffer
Type
Description
PORTK
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
PORTK is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 23
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-7:
TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
T1CK
48
73
A49
106
I
ST
Timer1 External Clock Input
T2CK
PPS
PPS
PPS
PPS
I
ST
Timer2 External Clock Input
T3CK
PPS
PPS
PPS
PPS
I
ST
Timer3 External Clock Input
T4CK
PPS
PPS
PPS
PPS
I
ST
Timer4 External Clock Input
T5CK
PPS
PPS
PPS
PPS
I
ST
Timer5 External Clock Input
T6CK
PPS
PPS
PPS
PPS
I
ST
Timer6 External Clock Input
T7CK
PPS
PPS
PPS
PPS
I
ST
Timer7 External Clock Input
T8CK
PPS
PPS
PPS
PPS
I
ST
Timer8 External Clock Input
T9CK
PPS
PPS
PPS
PPS
I
ST
Timer9 External Clock Input
Pin Name
Description
Timer1 through Timer9
Real-Time Clock and Calendar
RTCC
Legend:
46
71
A48
104
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 24
O
—
Real-Time Clock Alarm/Seconds Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-8:
UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
U1RX
PPS
PPS
PPS
PPS
I
ST
U1TX
PPS
PPS
PPS
PPS
O
—
UART1 Transmit
U1CTS
PPS
PPS
PPS
PPS
I
ST
UART1 Clear to Send
U1RTS
PPS
PPS
PPS
PPS
O
—
UART1 Ready to Send
Pin Name
144-pin
TQFP/
LQFP
Description
Universal Asynchronous Receiver Transmitter 1
UART1 Receive
Universal Asynchronous Receiver Transmitter 2
U2RX
PPS
PPS
PPS
PPS
I
ST
U2TX
PPS
PPS
PPS
PPS
O
—
UART2 Receive
UART2 Transmit
U2CTS
PPS
PPS
PPS
PPS
I
ST
UART2 Clear To Send
U2RTS
PPS
PPS
PPS
PPS
O
—
UART2 Ready To Send
Universal Asynchronous Receiver Transmitter 3
U3RX
PPS
PPS
PPS
PPS
I
ST
U3TX
PPS
PPS
PPS
PPS
O
—
UART3 Receive
UART3 Transmit
U3CTS
PPS
PPS
PPS
PPS
I
ST
UART3 Clear to Send
U3RTS
PPS
PPS
PPS
PPS
O
—
UART3 Ready to Send
Universal Asynchronous Receiver Transmitter 4
U4RX
PPS
PPS
PPS
PPS
I
ST
U4TX
PPS
PPS
PPS
PPS
O
—
UART4 Receive
UART4 Transmit
U4CTS
PPS
PPS
PPS
PPS
I
ST
UART4 Clear to Send
U4RTS
PPS
PPS
PPS
PPS
O
—
UART4 Ready to Send
Universal Asynchronous Receiver Transmitter 5
U5RX
PPS
PPS
PPS
PPS
I
ST
U5TX
PPS
PPS
PPS
PPS
O
—
UART5 Receive
UART5 Transmit
U5CTS
PPS
PPS
PPS
PPS
I
ST
UART5 Clear to Send
U5RTS
PPS
PPS
PPS
PPS
O
—
UART5 Ready to Send
Universal Asynchronous Receiver Transmitter 6
U6RX
PPS
PPS
PPS
PPS
I
ST
U6TX
PPS
PPS
PPS
PPS
O
—
UART6 Transmit
U6CTS
PPS
PPS
PPS
PPS
I
ST
UART6 Clear to Send
PPS
PPS
PPS
PPS
O
—
UART6 Ready to Send
U6RTS
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
UART6 Receive
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 25
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-9:
SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
SCK1
49
76
A52
109
I/O
ST
SPI1 Synchronous Serial Clock Input/Output
SDI1
PPS
PPS
PPS
PPS
I
ST
SPI1 Data In
SDO1
PPS
PPS
PPS
PPS
O
—
SPI1 Data Out
SS1
PPS
PPS
PPS
PPS
I/O
ST
SPI1 Slave Synchronization Or Frame Pulse I/O
Pin Name
Description
Serial Peripheral Interface 1
Serial Peripheral Interface 2
SCK2
4
10
B6
14
I/O
ST
SPI2 Synchronous Serial Clock Input/output
SDI2
PPS
PPS
PPS
PPS
I
ST
SPI2 Data In
SDO2
PPS
PPS
PPS
PPS
O
—
SPI2 Data Out
SS2
PPS
PPS
PPS
PPS
I/O
ST
SPI2 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 3
SCK3
29
43
A28
61
I/O
ST
SPI3 Synchronous Serial Clock Input/Output
SDI3
PPS
PPS
PPS
PPS
I
ST
SPI3 Data In
SDO3
PPS
PPS
PPS
PPS
O
—
SPI3 Data Out
SS3
PPS
PPS
PPS
PPS
I/O
ST
SPI3 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 4
SCK4
44
69
A46
98
I/O
ST
SPI4 Synchronous Serial Clock Input/Output
SDI4
PPS
PPS
PPS
PPS
I
ST
SPI4 Data In
SDO4
PPS
PPS
PPS
PPS
O
—
SPI4 Data Out
SS4
PPS
PPS
PPS
PPS
I/O
ST
SPI4 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 5
SCK5
—
39
A26
57
I/O
ST
SPI5 Synchronous Serial Clock Input/Output
SDI5
—
PPS
PPS
PPS
I
ST
SPI5 Data In
SDO5
—
PPS
PPS
PPS
O
—
SPI5 Data Out
SS5
—
PPS
PPS
PPS
I/O
ST
SPI5 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 6
SCK6
—
48
A32
70
I/O
ST
SPI6 Synchronous Serial Clock Input/Output
SDI6
—
PPS
PPS
PPS
I
ST
SPI6 Data In
SDO6
—
PPS
PPS
PPS
O
—
SPI6 Data Out
SS6
—
PPS
PPS
PPS
I/O
ST
SPI6 Slave Synchronization Or Frame Pulse I/O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 26
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-10:
I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
SCL1
44
66
B37
95
I/O
ST
I2C1 Synchronous Serial Clock Input/Output
SDA1
43
67
A45
96
I/O
ST
I2C1 Synchronous Serial Data Input/Output
Pin Name
Description
Inter-Integrated Circuit 1
Inter-Integrated Circuit 2
SCL2
—
59
A41
85
I/O
ST
I2C2 Synchronous Serial Clock Input/Output
SDA2
—
60
B34
86
I/O
ST
I2C2 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 3
SCL3
51
58
A39
80
I/O
ST
I2C3 Synchronous Serial Clock Input/Output
SDA3
50
57
B31
79
I/O
ST
I2C3 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 4
SCL4
6
12
B7
16
I/O
ST
I2C4 Synchronous Serial Clock Input/Output
SDA4
5
11
A8
15
I/O
ST
I2C4 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 5
SCL5
42
65
A44
91
I/O
ST
I2C5 Synchronous Serial Clock Input/Output
SDA5
41
64
B36
90
I/O
ST
I2C5 Synchronous Serial Data Input/Output
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-11:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS
Pin Number
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
CVREF+
16
29
A20
40
I
Analog
Comparator Voltage Reference (High) Input
CVREF-
15
28
B15
39
I
Analog
Comparator Voltage Reference (Low) Input
CVREFOUT
23
34
B19
49
O
Analog
Comparator Voltage Reference Output
Pin Name
Description
Comparator Voltage Reference
Comparator 1
C1INA
11
20
B11
25
I
Analog
Comparator 1 Positive Input
C1INB
12
21
A13
26
I
Analog
Comparator 1 Selectable Negative Input
C1INC
5
11
A8
15
I
Analog
C1IND
4
10
B6
14
I
Analog
C1OUT
PPS
PPS
PPS
PPS
O
—
Comparator 1 Output
Comparator 2
C2INA
13
22
A14
31
I
Analog
Comparator 2 Positive Input
C2INB
14
23
A16
34
I
Analog
Comparator 2 Selectable Negative Input
C2INC
10
16
B9
21
I
Analog
Analog
C2IND
6
12
B7
16
I
C2OUT
PPS
PPS
PPS
PPS
O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
—
Comparator 2 Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 27
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-12:
PMP PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
PMA0
30
44
B24
30
I/O
TTL/ST
Parallel Master Port Address bit 0 Input (Buffered
Slave modes) and Output (Master modes)
PMA1
29
43
A28
51
I/O
TTL/ST
Parallel Master Port Address bit 1 Input (Buffered
Slave modes) and Output (Master modes)
PMA2
10
16
B9
21
O
—
PMA3
6
12
B7
52
O
—
PMA4
5
11
A8
68
O
—
PMA5
4
2
B1
2
O
—
PMA6
16
6
B3
6
O
—
PMA7
22
33
A23
48
O
—
PMA8
42
65
A44
91
O
—
PMA9
41
64
B36
90
O
—
PMA10
21
32
B18
47
O
—
PMA11
27
41
A27
29
O
—
PMA12
24
7
A6
11
O
—
PMA13
23
34
B19
28
O
—
PMA14
45
61
A42
87
O
—
PMA15
43
68
B38
97
O
—
PMCS1
45
61
A42
87
O
—
PMCS2
43
68
B38
97
O
—
PMD0
58
91
B52
135
I/O
TTL/ST
PMD1
61
94
A64
138
I/O
TTL/ST
PMD2
62
98
A66
142
I/O
TTL/ST
PMD3
63
99
B56
143
I/O
TTL/ST
PMD4
64
100
A67
144
I/O
TTL/ST
PMD5
1
3
A3
3
I/O
TTL/ST
PMD6
2
4
B2
4
I/O
TTL/ST
PMD7
3
5
A4
5
I/O
TTL/ST
PMD8
—
88
B50
128
I/O
TTL/ST
Pin Name
Description
Parallel Master Port Address (Demultiplexed Master
modes)
Parallel Master Port Chip Select 1 Strobe
Parallel Master Port Chip Select 2 Strobe
Parallel Master Port Data (Demultiplexed Master
mode) or Address/Data (Multiplexed Master modes)
PMD9
—
87
A60
127
I/O
TTL/ST
PMD10
—
86
B49
125
I/O
TTL/ST
PMD11
—
85
A59
124
I/O
TTL/ST
PMD12
—
79
B43
112
I/O
TTL/ST
PMD13
—
80
A54
113
I/O
TTL/ST
PMD14
—
77
B42
110
I/O
TTL/ST
PMD15
—
78
A53
111
I/O
TTL/ST
PMALL
30
44
B24
30
O
—
Parallel Master Port Address Latch Enable Low Byte
(Multiplexed Master modes)
PMALH
29
43
A28
51
O
—
Parallel Master Port Address Latch Enable High Byte
(Multiplexed Master modes)
PMRD
53
9
A7
13
O
—
Parallel Master Port Read Strobe
PMWR
52
8
B5
12
O
—
Parallel Master Port Write Strobe
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 28
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-13:
EBI PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
EBIA0
—
44
B24
30
O
—
EBIA1
—
43
A28
51
O
—
EBIA2
—
16
B9
21
O
—
EBIA3
—
12
B7
52
O
—
EBIA4
—
11
A8
68
O
—
EBIA5
—
2
B1
2
O
—
EBIA6
—
6
B3
6
O
—
EBIA7
—
33
A23
48
O
—
EBIA8
—
65
A44
91
O
—
EBIA9
—
64
B36
90
O
—
EBIA10
—
32
B18
47
O
—
EBIA11
—
41
A27
29
O
—
EBIA12
—
7
A6
11
O
—
EBIA13
—
34
B19
28
O
—
EBIA14
—
61
A42
87
O
—
EBIA15
—
68
B38
97
O
—
EBIA16
—
17
A11
19
O
—
EBIA17
—
40
B22
53
O
—
EBIA18
—
39
A26
92
O
—
EBIA19
—
38
B21
93
O
—
EBIA20
—
—
—
94
O
—
EBIA21
—
—
—
126
O
—
EBIA22
—
—
—
117
O
—
EBIA23
—
—
—
103
O
—
EBID0
—
91
B52
135
I/O
ST
EBID1
—
94
A64
138
I/O
ST
EBID2
—
98
A66
142
I/O
ST
EBID3
—
99
B56
143
I/O
ST
EBID4
—
100
A67
144
I/O
ST
EBID5
—
3
A3
3
I/O
ST
EBID6
—
4
B2
4
I/O
ST
EBID7
—
5
A4
5
I/O
ST
EBID8
—
88
B50
128
I/O
ST
Pin Name
EBID9
—
87
A60
127
I/O
ST
EBID10
—
86
B49
125
I/O
ST
EBID11
—
85
A59
124
I/O
ST
EBID12
—
79
B43
112
I/O
ST
EBID13
—
80
A54
113
I/O
ST
EBID14
—
77
B42
110
I/O
ST
EBID15
—
78
A53
111
I/O
ST
EBIBS0
—
—
—
9
O
—
EBIBS1
—
—
—
10
O
—
EBICS0
—
59
A41
131
O
—
EBICS1
—
—
—
132
O
—
EBICS2
—
—
—
133
O
—
EBICS3
—
—
—
134
O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
Description
External Bus Interface Address Bus
External Bus Interface Data I/O Bus
External Bus Interface Byte Select
External Bus Interface Chip Select
—
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 29
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-13:
EBI PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
Description
EBIOE
—
9
A7
13
O
—
External Bus Interface Output Enable
EBIRDY1
—
60
B34
86
I
ST
External Bus Interface Ready Input
EBIRDY2
—
58
A39
84
I
ST
EBIRDY3
—
57
B45
116
I
ST
EBIRP
—
—
—
45
O
—
External Bus Interface Flash Reset Pin
EBIWE
—
8
B5
12
O
—
External Bus Interface Write Enable
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 30
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-14:
USB PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
73
I
Analog
74
P
—
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
VBUS
33
51
A35
VUSB3V3
34
52
A36
Pin Name
Description
USB bus power monitor
USB internal transceiver supply. If the USB module is
not used, this pin must be connected to VSS. When
connected, the shared pin functions on USBID will not
be available.
D+
37
55
B30
77
I/O
Analog
USB D+
D-
36
54
A37
76
I/O
Analog
USB D-
38
56
A38
78
I
USBID
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-15:
ST
USB OTG ID detect
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
C1TX
PPS
PPS
PPS
PPS
O
—
CAN1 Bus Transmit Pin
C1RX
PPS
PPS
PPS
PPS
I
ST
CAN1 Bus Receive Pin
C2TX
PPS
PPS
PPS
PPS
O
—
CAN2 Bus Transmit Pin
C2RX
PPS
PPS
PPS
PPS
I
ST
CAN2 Bus Receive Pin
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
Buffer
Type
Description
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 31
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-16:
ETHERNET MII I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
ERXD0
61
41
B32
81
I
ST
Ethernet Receive Data 0
ERXD1
58
42
B26
66
I
ST
Ethernet Receive Data 1
ERXD2
57
43
A31
67
I
ST
Ethernet Receive Data 2
ERXD3
56
44
A40
82
I
ST
Ethernet Receive Data 3
ERXERR
64
35
A30
65
I
ST
Ethernet Receive Error Input
Pin Name
Description
ERXDV
62
12
B40
101
I
ST
Ethernet Receive Data Valid
ERXCLK
63
16
B12
27
I
ST
Ethernet Receive Clock
ETXD0
2
86
A5
7
O
—
Ethernet Transmit Data 0
ETXD1
3
85
B4
8
O
—
Ethernet Transmit Data 1
ETXD2
43
79
B17
43
O
—
Ethernet Transmit Data 2
ETXD3
46
80
A22
44
O
—
Ethernet Transmit Data 3
ETXERR
50
87
B44
114
O
—
Ethernet Transmit Error
ETXEN
1
77
A57
120
O
—
Ethernet Transmit Enable
ETXCLK
51
78
B47
121
I
ST
Ethernet Transmit Clock
ECOL
44
10
B33
83
I
ST
Ethernet Collision Detect
ECRS
45
11
A47
100
I
ST
Ethernet Carrier Sense
EMDC
30
70
B39
99
O
—
Ethernet Management Data Clock
EMDIO
49
71
A55
115
I/O
—
Ethernet Management Data
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-17:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
ETHERNET RMII PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
ERXD0
61
41
B32
81
I
ST
Ethernet Receive Data 0
ERXD1
58
42
B26
66
I
ST
Ethernet Receive Data 1
ERXERR
64
35
A30
65
I
ST
Ethernet Receive Error Input
ETXD0
2
86
A5
7
O
—
Ethernet Transmit Data 0
ETXD1
3
85
B4
8
O
—
Ethernet Transmit Data 1
ETXEN
1
77
A57
120
O
—
Ethernet Transmit Enable
EMDC
30
70
B39
99
O
—
Ethernet Management Data Clock
EMDIO
49
71
A55
115
I/O
—
Ethernet Management Data
EREFCLK
63
16
B12
27
I
ST
Ethernet Reference Clock
ECRSDV
62
12
B40
101
I
ST
Ethernet Carrier Sense Data Valid
Pin Name
Description
Ethernet MII Interface
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001191F-page 32
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-18:
ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AERXD0
—
18
—
—
I
ST
Alternate Ethernet Receive Data 0
AERXD1
—
19
—
—
I
ST
Alternate Ethernet Receive Data 1
AERXD2
—
28
—
—
I
ST
Alternate Ethernet Receive Data 2
AERXD3
—
29
—
—
I
ST
Alternate Ethernet Receive Data 3
AERXERR
—
1
—
—
I
ST
Alternate Ethernet Receive Error Input
AERXDV
—
12
—
—
I
ST
Alternate Ethernet Receive Data Valid
AERXCLK
—
16
—
—
I
ST
Alternate Ethernet Receive Clock
AETXD0
—
47
—
—
O
—
Alternate Ethernet Transmit Data 0
AETXD1
—
48
—
—
O
—
Alternate Ethernet Transmit Data 1
AETXD2
—
44
—
—
O
—
Alternate Ethernet Transmit Data 2
AETXD3
—
43
—
—
O
—
Alternate Ethernet Transmit Data 3
AETXERR
—
35
—
—
O
—
Alternate Ethernet Transmit Error
Pin Name
Description
AECOL
—
42
—
—
I
ST
Alternate Ethernet Collision Detect
AECRS
—
41
—
—
I
ST
Alternate Ethernet Carrier Sense
AETXCLK
—
66
—
—
I
ST
Alternate Ethernet Transmit Clock
AEMDC
—
70
—
—
O
—
Alternate Ethernet Management Data Clock
AEMDIO
—
71
—
—
I/O
—
Alternate Ethernet Management Data
AETXEN
—
67
—
—
O
—
Alternate Ethernet Transmit Enable
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-19:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
ALTERNATE ETHERNET RMII PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AERXD0
43
18
—
—
I
ST
Alternate Ethernet Receive Data 0
AERXD1
46
19
—
—
I
ST
Alternate Ethernet Receive Data 1
AERXERR
51
1
—
—
I
ST
Alternate Ethernet Receive Error Input
AETXD0
57
47
—
—
O
—
Alternate Ethernet Transmit Data 0
AETXD1
56
48
—
—
O
—
Alternate Ethernet Transmit Data 1
AEMDC
30
70
—
—
O
—
Alternate Ethernet Management Data Clock
AEMDIO
49
71
—
—
I/O
—
Alternate Ethernet Management Data
AETXEN
50
67
—
—
O
—
Alternate Ethernet Transmit Enable
AEREFCLK
45
16
—
—
I
ST
Alternate Ethernet Reference Clock
AECRSDV
62
12
—
—
I
ST
Alternate Ethernet Carrier Sense Data Valid
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
Description
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 33
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-20:
SQI1 PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
SQICLK
57
89
A61
129
O
—
Serial Quad Interface Clock
SQICS0
52
81
A56
118
O
—
Serial Quad Interface Chip Select 0
SQICS1
53
82
B46
119
O
—
Serial Quad Interface Chip Select 1
SQID0
58
97
B55
141
I/O
ST
Serial Quad Interface Data 0
SQID1
61
96
A65
140
I/O
ST
Serial Quad Interface Data 1
SQID2
62
95
B54
139
I/O
ST
Serial Quad Interface Data 2
SQID3
63
90
B51
130
I/O
ST
Serial Quad Interface Data 3
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-21:
Description
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
AVDD
AVSS
VDD
VSS
VREF+
VREFLegend:
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
Description
Power and Ground
P
P
Positive supply for analog modules. This pin must be
connected at all times.
20
31
A21
42
P
P
Ground reference for analog modules. This pin must
be connected at all times
8, 26, 39, 14, 37, B8, A15, 18, 33,
P
—
Positive supply for peripheral logic and I/O pins. This
54, 60
46, 62,
A25,
55, 64,
pin must be connected at all times.
74, 83, 93
B25,
88, 107,
B35,
122, 137
A50,
A58, B53
7, 25, 35, 13, 36, A9, B13, 17, 32,
P
—
Ground reference for logic, I/O pins, and USB. This pin
40, 55, 59 45, 53,
B20,
54, 63,
must be connected at all times.
63, 75,
B29,
75, 89,
84, 92
A29,
108,
A43,
123, 136
A51,
B48, A63
Voltage Reference
16
29
A20
40
I
Analog Analog Voltage Reference (High) Input
15
28
B15
39
I
Analog Analog Voltage Reference (Low) Input
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
19
DS60001191F-page 34
30
B16
41
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 1-22:
JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
TCK
27
38
B21
56
I
ST
TDI
28
39
A26
57
I
ST
JTAG Test Data Input Pin
TDO
24
40
B22
58
O
—
JTAG Test Data Output Pin
TMS
23
17
A11
22
I
ST
JTAG Test Mode Select Pin
Pin Name
Buffer
Type
Description
JTAG
JTAG Test Clock Input Pin
Trace
TRCLK
57
89
A61
129
O
—
Trace Clock
TRD0
58
97
B55
141
O
—
Trace Data bits 0-3
TRD1
61
96
A65
140
O
—
TRD2
62
95
B54
139
O
—
TRD3
63
90
B51
130
O
—
Programming/Debugging
PGED1
16
25
A18
36
I/O
ST
Data I/O pin for Programming/Debugging
Communication Channel 1
PGEC1
15
24
A17
35
I
ST
Clock input pin for Programming/Debugging
Communication Channel 1
PGED2
18
27
A19
38
I/O
ST
Data I/O pin for Programming/Debugging
Communication Channel 2
PGEC2
17
26
B14
37
I
ST
Clock input pin for Programming/Debugging
Communication Channel 2
MCLR
9
15
A10
20
I/P
ST
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
 2013-2016 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001191F-page 35
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 36
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
2.0
Note:
2.1
Note:
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the documents provided in
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Basic Connection Requirements
The PIC32MZ EC family of devices
require a unique VDD ramp-up time.
Please refer to parameter DC17 in
Table 37-4 of 37.0 “Electrical Characteristics” before finalizing regulator design.
Getting started with the PIC32MZ EC family of 32-bit
Microcontrollers (MCUs) requires attention to a minimal
set of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling
Capacitors”)
• All AVDD and AVSS pins, even if the ADC module
is not used (see 2.2 “Decoupling Capacitors”)
• MCLR pin (see 2.3 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming (ICSP™) and debugging purposes
(see 2.4 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.7 “External Oscillator
Pins”)
The following pin(s) may be required as well:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance (lowESR) capacitor and have resonance frequency in
the range of 20 MHz and higher. It is further
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally
important is to keep the trace length between the
capacitor and the power pins to a minimum thereby
reducing PCB track inductance.
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 37
PIC32MZ Embedded Connectivity (EC) Family
Note:
The PIC32MZ EC family of devices
require a unique VDD ramp-up time.
Please refer to parameter DC17 in
Table 37-4 of 37.0 “Electrical Characteristics” before finalizing regulator design.
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
VDD
0.1 µF
Ceramic
VSS
MCLR
VDD
VSS
R1
VDD
R
VDD
VSS
VDD
C
PIC32
VSS
Connect(2)
VDD
0.1 µF
Ceramic
VSS
VSS
AVSS
0.1 µF
Ceramic
VDD
AVDD
VDD
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
VSS
VUSB3V3(1)
VDD
VSS
2.3
0.1 µF
Ceramic
0.1 µF
Ceramic
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
L1(2)
VDD
1:
If the USB module is not used, this pin must not be
connected to VDD .
2:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.

Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC 
R
1
5
4
2
3
6
(i.e., ADC conversion rate/2)
Note
DS60001191F-page 38
C
1 k
VDD
VSS
NC
PGECx(3)
PGEDx(3)
1:
470 R1  1 will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
R1(1)
PIC32
1 - 2
L =  --------------------  2f C 
2.2.1
10k
MCLR
0.1 µF(2)
ICSP™
Note
EXAMPLE OF MCLR PIN
CONNECTIONS(1,2,3)
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
2.4
ICSP Pins
2.6
Trace
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on
the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series
resistor is recommended, with the value in the range
of a few tens of Ohms, not to exceed 100 Ohms.
The trace pins can be connected to a hardware
trace-enabled programmer to provide a compressed
real-time instruction trace. When used for trace, the
TRD3, TRD2, TRD1, TRD0 and TRCLK pins should
be dedicated for this use. The trace hardware
requires a 22 Ohm series resistor between the trace
pins and the trace connector.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
2.7
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available from the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster)
(DS50001749)
2.5
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 39
PIC32MZ Embedded Connectivity (EC) Family
2.7.1
CRYSTAL OSCILLATOR DESIGN
CONSIDERATION
The following example assumptions are used to
calculate the Primary Oscillator loading capacitor
values:
• CIN = PIC32_OSC2_Pin Capacitance = ~4-5 pF
• COUT = PIC32_OSC1_Pin Capacitance = ~4-5 pF
• C1 and C2 = XTAL manufacturing recommended
loading capacitance
• Estimated PCB stray capacitance, (i.e.,12 mm
length) = 2.5 pF
Crystals with a speed of 4 MHz to 12 MHz that meet the
following requirements will meet the PIC32MZ EC
oscillation requirements when configured, as depicted
in Figure 8-1.
1.
2.
Manufacturer Drive Level (min)  10 µW (hard
requirements, 1 µW preferred).
Manufacturer ESR  50 (hard requirement,
lower is better).
2.7.1.1
1.
2.
3.
Calculating XTAL Capacitive
Loading:
PIC32 CIN = COUT = ~4 pF (PIC32 OSCI and
OSCO package pin capacitance).
C1MFG = C2MFG = Manufacturer Recommended
Load Capacitance.
CLOAD = {([CIN + C1MFG] [C2MFG + COUT]) /
[CIN + C1MFG + C2MFG + COUT]} + estimated
PCB stray capacitance (2.5 pF).
(Simplified) CLOAD = (((CIN + C1MFG) / 2) + 2.5 pF).
Actual C1, C2 Load value to use:
• C2 = CLOAD
• C1 = (CLOAD - 2 pF)
Note:
2.7.1.2
These recommendations are atypical, and
are only applicable to the PIC32MZ EC
family.
Validated Crystals
Temperature Range: (-45ºC to +110ºC)
VDD = 2.4V to 3.6V, RP = 1 M, RK = 10 k
• ABLS-12.000 MHz-L4Q-T (12 MHz surface mount)
Note:
These recommendations are atypical, and
only applicable to the PIC32MZ EC family.
DS60001191F-page 40
2.7.1.3
Additional Microchip References
• AN588 “PICmicro® Microcontroller Oscillator
Design Guide”
• AN826 “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849 “Basic PICmicro® Oscillator Design”
2.8
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
2.9
Designing for High-Speed
Peripherals
The PIC32MZ EC family devices have peripherals that
operate at frequencies much higher than typical for an
embedded environment. Table 2-1 lists the peripherals
that produce high-speed signals on their external pins:
TABLE 2-1:
PERIPHERALS THAT
PRODUCE HS SIGNALS ON
EXTERNAL PINS
Peripheral High-Speed Signal Pins
EBI
SQI1
HS USB
EBIAx, EBIDx
Maximum
Speed on
Signal Pin
50 MHz
SQICLK, SQICSx, SQIDx
50 MHz
D+, D-
480 MHz
Due to these high-speed signals, it is important to take
into consideration several factors when designing a
product that uses these peripherals, as well as the PCB
on which these components will be placed. Adhering to
these recommendations will help achieve the following
goals:
• Minimize the effects of electromagnetic interference
to the proper operation of the product
• Ensure signals arrive at their intended destination at
the same time
• Minimize crosstalk
• Maintain signal integrity
• Reduce system noise
• Minimize ground bounce and power sag
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
2.9.1
2.9.1.1
SYSTEM DESIGN
Impedance Matching
When selecting parts to place on high-speed buses,
particularly the SQI bus, if the impedance of the peripheral device does not match the impedance of the pins
on the PIC32MZ EC device to which it is connected,
signal reflections could result, thereby degrading the
quality of the signal.
If it is not possible to select a product that matches
impedance, place a series resistor at the load to create
the matching impedance. See Figure 2-4 for an
example.
FIGURE 2-4:
SERIES RESISTOR
PIC32MZ
50
2.9.1.2
SQI
Flash
Device
PCB Layout Recommendations
The following list contains recommendations that will
help ensure the PCB layout will promote the goals
previously listed.
• Component Placement
- Place bypass capacitors as close to their
component power and ground pins as possible,
and place them on the same side of the PCB
- Devices on the same bus that have larger setup
times should be placed closer to the PIC32MZ EC
device
• Power and Ground
- Multi-layer PCBs will allow separate power and
ground planes
- Each ground pin should be connected to the
ground plane individually
- Place bypass capacitor vias as close to the pad
as possible (preferably inside the pad)
- If power and ground planes are not used,
maximize width for power and ground traces
- Use low-ESR, surface-mount bypass capacitors
 2013-2016 Microchip Technology Inc.
• Clocks and Oscillators
- Place crystals as close as possible to the
PIC32MZ EC device OSC/SOSC pins
- Do not route high-speed signals near the clock or
oscillator
- Avoid via usage and branches in clock lines
(SQICLK)
- Place termination resistors at the end of clock
lines
• Traces
- Higher-priority signals should have the shortest
traces
- Match trace lengths for parallel buses (EBIAx,
EBIDx, SQIDx)
- Avoid long run lengths on parallel traces to reduce
coupling
- Make the clock traces as straight as possible
- Use rounded turns rather than right-angle turns
- Have traces on different layers intersect on right
angles to minimize crosstalk
- Maximize the distance between traces, preferably
no less than three times the trace width
- Power traces should be as short and as wide as
possible
- High-speed traces should be placed close to the
ground plane
DS60001191F-page 41
PIC32MZ Embedded Connectivity (EC) Family
2.10
2.10.1
Considerations When Interfacing
to Remotely Powered Circuits
NON-5V TOLERANT INPUT PINS
A quick review of the absolute maximum rating section
in 37.0 “Electrical Characteristics” will indicate that
the voltage on any non-5v tolerant pin may not exceed
AVDD/VDD + 0.3V. Figure 2-5 shows an example of a
remote circuit using an independent power source,
which is powered while connected to a PIC32 non-5V
tolerant circuit that is not powered.
FIGURE 2-5:
Note:
PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
When VDD power is OFF.
PIC32
Non-5V Tolerant
Pin Architecture
On/Off
VDD
ANSEL
I/O IN
AN2/RB0
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
0.3V dVIH d 3.6V
PIC32
POWER
SUPPLY
Current Flow
VSS
DS60001191F-page 42
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 2-6:
Opto Coupling
Analog/Digital Switch
EXAMPLES OF DIGITAL/
ANALOG ISOLATORS WITH
OPTIONAL LEVEL
TRANSLATION
Capacitive Coupling
TABLE 2-2:
Inductive Coupling
Without proper signal isolation, on non-5V tolerant
pins, the remote signal can power the PIC32 device
through the high side ESD protection diodes.
Besides violating the absolute maximum rating
specification when VDD of the PIC32 device is
restored and ramping up or ramping down, it can
also negatively affect the internal Power-on Reset
(POR) and Brown-out Reset (BOR) circuits, which
can lead to improper initialization of internal PIC32
logic circuits. In these cases, it is recommended to
implement digital or analog signal isolation as
depicted in Figure 2-6, as appropriate. This is
indicative of all industry microcontrollers and not just
Microchip products.
X
—
—
—
ADuM7241 / 40 CRZ (25 Mbps)
X
—
—
—
ISO721
—
X
—
—
LTV-829S (2 Channel)
—
—
X
—
LTV-849S (4 Channel)
—
—
X
—
FSA266 / NC7WB66
—
—
—
X
Example Digital/Analog
Signal Isolation Circuits
ADuM7241 / 40 ARZ (1 Mbps)
DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Conn
PIC32 VDD
Digital Isolator
External VDD
IN
REMOTE_IN
PIC32
PIC32 VDD
Digital Isolator
External VDD
REMOTE_IN
IN1
REMOTE_OUT
OUT1
PIC32
VSS
VSS
PIC32 VDD
Opto Digital
ISOLATOR
External VDD
PIC32 VDD
Analog / Digital Isolator
Conn
IN1
ENB
Analog_OUT2
PIC32
External_VDD1
ENB
PIC32
S
Analog_IN1
REMOTE_IN
Analog_IN2
Analog Switch
VSS
VSS
 2013-2016 Microchip Technology Inc.
DS60001191F-page 43
PIC32MZ Embedded Connectivity (EC) Family
2.10.2
5V TOLERANT INPUT PINS
The internal high side diode on 5V tolerant pins are
bussed to an internal floating node, rather than being
connected to VDD, as shown in Figure 2-7. Voltages
on these pins, if VDD < 2.3V, should not exceed
roughly 3.2V relative to VSS of the PIC32 device.
Voltage of 3.6V or higher will violate the absolute
maximum specification, and will stress the oxide
layer separating the high side floating node, which
impacts device reliability. If a remotely powered
“digital-only” signal can be guaranteed to always be
 3.2V relative to Vss on the PIC32 device side, a
5V tolerant pin could be used without the need for a
digital isolator. This is assuming there is not a
ground loop issue, logic ground of the two circuits
not at the same absolute level, and a remote logic
low input is not less than VSS - 0.3V.
FIGURE 2-7:
PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
PIC32
5V Tolerant Pin
Architecture
Floating Bus
Oxide BV = 3.6V
if VDD < 2.3V
OXIDE
On/Off
VDD
ANSEL
I/O IN
RG10
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
VIH = 2.5V
PIC32
POWER
SUPPLY
VSS
DS60001191F-page 44
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
2.10.2.1
EMI Suppression Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/
Boost regulators as the local power source for
PIC32MZ EF devices, as well as in electrically noisy
environments, users should evaluate the use of TFilters (i.e., L-C-L) on the power pins, as shown in
Figure 2-8. In addition to a more stable power
source, use of this type of T-Filter can greatly reduce
susceptibility to EMI sources and events.
FIGURE 2-8:
Ferrite Chip SMD
DCR = 0.15ȍ(max)
600 ma ISAT
300ȍ@ 100 MHz
PN#: VDD
0.01 µF
Ferrite
Chips
0.1 µF
VSS
VDD
VDD
VSS
0.1 µF
VSS
VDD
VSS
VDD
VSS
0.1 µF
PIC32MZ
VSS
0.1 µF
VSS
VDD
AVDD
AVSS
0.1 µF
VSS
VUSB3V3
VDD
0.1 µF
VDD
0.1 µF
0.1 µF
0.1 µF
Ferrite
Chips
VDD
0.01 µF
 2013-2016 Microchip Technology Inc.
DS60001191F-page 45
PIC32MZ Embedded Connectivity (EC) Family
2.11
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-9 and Figure 2-10.
FIGURE 2-9:
AUDIO PLAYBACK APPLICATION
PMD<7:0>
USB
Host
PMP
USB
Display
PMWR
PIC32
I2S
SPI
Stereo Headphones
3
REFCLKO
3
Audio
Codec
Speaker
3
MMC SD
SDI
FIGURE 2-10:
LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH
PROJECTED CAPACITIVE TOUCH
PIC32
Microchip
mTouch™
Library
Microchip
GFX Library
ANx
ADC
Render
LCD Display
Refresh
DMA
Projected Capacitive
Touch Overlay
EBI
SRAM
DS60001191F-page 46
External Frame Buffer
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
3.0
Note:
CPU
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 50. “CPU
for
Devices
with
MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).

MIPS32® microAptiv™ Microprocessor
Core resources are available at:
www.imgtec.com.
The MIPS32® microAptiv™ Microprocessor Core is the
heart of the PIC32MZ EC family device processor. The
CPU fetches instructions, decodes each instruction,
fetches source operands, executes each instruction
and writes the results of instruction execution to the
proper destinations.
3.1
Features
PIC32MZ EC family processor core key features:
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32® Enhanced Architecture (Release 2):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency for
interrupt handlers
- Bit field manipulation instructions
- Virtual memory support
• microMIPS™ compatible instruction set:
- Improves code size density over MIPS32, while
maintaining MIPS32 performance.
- Supports all MIPS32 instructions (except branchlikely instructions)
- Fifteen additional 32-bit instructions and 39 16-bit
instructions corresponding to commonly-used
MIPS32 instructions
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI compatible
 2013-2016 Microchip Technology Inc.
• MMU with Translation Lookaside Buffer (TLB)
mechanism:
- 16 dual-entry fully associative Joint TLB
- 4-entry fully associative Instruction TLB
- 4-entry fully associative Data TLB
- 4 KB pages
• Separate L1 data and instruction caches:
- 16 KB 4-way Instruction Cache (I-Cache)
- 4 KB 4-way Data Cache (D-Cache)
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x32 multiply per
clock
- Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- Hardware breakpoint supports both address
match and address range triggering.
- Eight instruction and four data complex
breakpoints
• iFlowtrace® version 2.0 support:
- Real-time instruction program counter
- Special events trace capability
- Two performance counters with 34 userselectable countable events
- Disabled if the processor enters Debug mode
• Four Watch registers:
- Instruction, Data Read, Data Write options
- Address match masking options
• DSP ASE Extension:
- Native fractional format data type operations
- Register Single Instruction Multiple Data
(SIMD) operations (add, subtract, multiply,
shift)
- GPR-based shift
- Bit manipulation
- Compare-Pick
- DSP Control Access
- Indexed-Load
- Branch
- Multiplication of complex operands
- Variable bit insertion and extraction
- Virtual circular buffers
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations
DS60001191F-page 47
PIC32MZ Embedded Connectivity (EC) Family
A block diagram of the PIC32MZ EC family processor
core is shown in Figure 3-1.
FIGURE 3-1:
PIC32MZ EC FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM
microAptiv™ Microprocessor Core
PBCLK7
Decode
(MIPS32®/microMIPS™)
microMIPS™
GPR
(8 sets)
Execution Unit
ALU/Shift
Atomic/LdSt
DSP ASE
Enhanced MDU
(with DSP ASE)
Debug/Profiling
System
Interface
System
Coprocessor
Interrupt
Interface
2-wire Debug
DS60001191F-page 48
Break Points
iFlowtrace®
Fast Debug Channel
Performance Counters
Sampling
Secure Debug
I-Cache
Controller
MMU
(TLB)
I-Cache
BIU
System Bus
D-Cache
Controller
D-Cache
Power
Management
EJTAG
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
3.2
Architecture Overview
The MIPS32 microAptiv Microprocessor core in
PIC32MZ EC family devices contains several logic
blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
•
•
•
•
•
•
•
•
•
•
Execution unit
General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
System control coprocessor (CP0)
Memory Management Unit (MMU)
Instruction/Data cache controllers
Power Management
Instructions and data caches
microMIPS support
Enhanced JTAG (EJTAG) controller
3.2.1
3.2.2
MULTIPLY/DIVIDE UNIT (MDU)
The processor core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer
Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially
masked by system stalls and/or other integer unit
instructions.
EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous
multiply/divide unit. The core contains thirty-two 32-bit
General Purpose Registers (GPRs) used for integer
operations and address calculation. Seven additional
register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
TABLE 3-1:
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing arithmetic
and bitwise logical operations
• Shifter and store aligner
• DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare
operations
The high-performance MDU consists of a 32x32 booth
recoded multiplier, four pairs of result/accumulation
registers (HI and LO), a divide state machine, and the
necessary multiplexers and control logic. The first number shown (‘32’ of 32x32) represents the rs operand.
The second number (‘32’ of 32x32) represents the rt
operand.
The MDU supports execution of one multiply or
multiply-accumulate operation every clock cycle.
Divide operations are implemented with a simple 1-bitper-clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For
a 16-bit wide rs, 15 iterations are skipped and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is
still active causes an IU pipeline stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the processor
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32 microAptiv MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU (HI/LO destination)
16 bits
5
1
32 bits
5
1
MUL (GPR destination)
16 bits
5
1
32 bits
5
1
DIV/DIVU
 2013-2016 Microchip Technology Inc.
8 bits
12/14
12/14
16 bits
20/22
20/22
24 bits
28/30
28/30
32 bits
36/38
36/38
DS60001191F-page 49
PIC32MZ Embedded Connectivity (EC) Family
The MIPS architecture defines that the result of a
multiply or divide operation be placed in one of four
pairs of HI and LO registers. Using the Move-From-HI
(MFHI) and Move-From-LO (MFLO) instructions, these
values can be transferred to the General Purpose
Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by supporting multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
The MDU also implements various shift instructions
operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all
of the data types required for this purpose and includes
three extra HI/LO registers as defined by the ASE.
DS60001191F-page 50
Table 3-2 lists the latencies and repeat rates for the
DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of
pipeline clocks.
TABLE 3-2:
DSP-RELATED LATENCIES
AND REPEAT RATES
Op code
Latency
Repeat
Rate
Multiply and dot-product without
saturation after accumulation
5
1
Multiply and dot-product with
saturation after accumulation
5
1
Multiply without accumulation
5
1
3.2.3
SYSTEM CONTROL 
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation and cache protocols, the exception control system, the processor’s
diagnostics capability, the operating modes (Kernel,
User and Debug) and whether interrupts are enabled or
disabled. Configuration information, such as cache
size and set associativity, and the presence of options
like microMIPS, is also available by accessing the CP0
registers, listed in Table 3-3.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 3-3:
Register
Number
COPROCESSOR 0 REGISTERS
Register
Name
Function
0
Index
Index into the TLB array (microAptiv MPU only).
1
2
Random
EntryLo0
3
EntryLo1
Randomly generated index into the TLB array (microAptiv MPU only).
Low-order portion of the TLB entry for even-numbered virtual pages (microAptiv MPU
only).
Low-order portion of the TLB entry for odd-numbered virtual pages (microAptiv MPU
only).
4
Context/
UserLocal
5
PageMask/
PageGrain
6
7
Wired
HWREna
8
BadVAddr
Controls the number of fixed (i.e., wired) TLB entries (microAptiv MPU only).
Enables access via the RDHWR instruction to selected hardware registers in 
Non-privileged mode.
Reports the address for the most recent address-related exception.
9
10
Count
EntryHi
Processor cycle count.
High-order portion of the TLB entry (microAptiv MPU only).
11
12
Compare
Status
Core timer interrupt control.
Processor status and control.
IntCtl
SRSCtl
Interrupt control of vector spacing.
Shadow register set control.
SRSMap
View_IPL
Shadow register mapping control.
Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
SRSMAP2
Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
13
Cause
NestedExc
View_RIPL
Describes the cause of the last exception.
Contains the error and exception level status bit values that existed prior to the current
exception.
Enables read access to the RIPL bit that is available in the Cause register.
14
EPC
NestedEPC
Program counter at last exception.
Contains the exception program counter that existed prior to the current exception.
15
PRID
Ebase
Processor identification and revision
Exception base address of exception vectors.
CDMMBase
Config
Common device memory map base.
Configuration register.
Config1
Config2
Configuration register 1.
Configuration register 2.
Config3
Config4
Configuration register 3.
Configuration register 4.
Config5
Config7
Configuration register 5.
Configuration register 7.
17
18
LLAddr
WatchLo
Load link address (microAptiv MPU only).
Low-order watchpoint address (microAptiv MPU only).
19
20-22
WatchHi
Reserved
High-order watchpoint address (microAptiv MPU only).
Reserved in the PIC32 core.
16
Pointer to the page table entry in memory (microAptiv MPU only).
User information that can be written by privileged software and read via the RDHWR
instruction.
PageMask controls the variable page sizes in TLB entries. PageGrain enables support
of 1 KB pages in the TLB (microAptiv MPU only).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 51
PIC32MZ Embedded Connectivity (EC) Family
TABLE 3-3:
Register
Number
23
COPROCESSOR 0 REGISTERS (CONTINUED)
Register
Name
Function
Debug
EJTAG debug register.
TraceControl
TraceControl2
EJTAG trace control.
EJTAG trace control 2.
UserTraceData1 EJTAG user trace data 1 register.
TraceBPC
EJTAG trace breakpoint register.
24
Debug2
DEPC
Debug control/exception status 1.
Program counter at last debug exception.
25
UserTraceData2 EJTAG user trace data 2 register.
PerfCtl0
Performance counter 0 control.
PerfCnt0
PerfCtl1
Performance counter 0.
Performance counter 1 control.
PerfCnt1
ErrCtl
27
Reserved
Performance counter 1.
Software test enable of way-select and data RAM arrays for I-Cache and D-Cache
(microAptiv MPU only).
Reserved in the PIC32 core.
28
29
TagLo/DataLo
Reserved
Low-order portion of cache tag interface (microAptiv MPU only).
Reserved in the PIC32 core.
30
31
ErrorEPC
DeSave
Program counter at last error exception.
Debug exception save.
26
DS60001191F-page 52
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
3.3
Power Management
The processor core offers a number of power management features, including low-power design, active power
management and power-down modes of operation. The
core is a static design that supports slowing or halting
the clocks, which reduces system power consumption
during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 33.0
“Power-Saving Features”.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The
PIC32MZ family makes extensive use of local gatedclocks to reduce this dynamic power consumption.
3.4
3.4.1
L1 Instruction and Data Caches
INSTRUCTION CACHE (I-CACHE)
The I-Cache is an on-core memory block of 16 Kbytes.
Because the I-Cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access rather than having to wait for the physical
address translation. The tag holds 22 bits of physical
address, a valid bit, and a lock bit. The LRU
replacement bits are stored in a separate array.
The I-Cache block also contains and manages the
instruction line fill buffer. Besides accumulating data to
be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a
bypass of that data, or data coming from the external
interface. The I-Cache control logic controls the bypass
function.
The processor core supports I-Cache locking. Cache
locking allows critical code or data segments to be
locked into the cache on a per-line basis, enabling the
system programmer to maximize the efficiency of the
system cache.
The cache locking function is always available on all
I-Cache entries. Entries can then be marked as
locked or unlocked on a per entry basis using the
CACHE instruction.
3.4.2
DATA CACHE (D-CACHE)
The D-Cache is an on-core memory block of 4 Kbytes.
This virtually indexed, physically tagged cache is protected. Because the D-Cache is virtually indexed, the
virtual-to-physical address translation occurs in parallel
with the cache access. The tag holds 22 bits of physical
address, a valid bit, and a lock bit. There is an additional array holding dirty bits and LRU replacement
algorithm bits for each set of the cache.
 2013-2016 Microchip Technology Inc.
In addition to I-Cache locking, the processor core also
supports a D-Cache locking mechanism identical to the
I-Cache. Critical data segments are locked into the
cache on a per-line basis. The locked contents can be
updated on a store hit, but cannot be selected for
replacement on a cache miss.
The D-Cache locking function is always available on
all D-Cache entries. Entries can then be marked as
locked or unlocked on a per-entry basis using the
CACHE instruction.
3.4.3
ATTRIBUTES
The processor core I-Cache and D-Cache attributes
are listed in the Configuration registers (see
Register 3-1 through Register 3-4).
3.5
EJTAG Debug Support
The processor core provides for an Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard
User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification specify which
registers are selected and how they are used.
3.6
MIPS DSP ASE Extension
The MIPS DSP Application-Specific Extension
Revision 2 is an extension to the MIPS32 architecture.
This extension comprises new integer instructions and
states that include new HI/LO accumulator register
pairs and a DSP control register. This extension is
crucial in a wide range of DSP, multimedia, and DSPlike algorithms covering Audio and Video processing
applications. The extension supports native fractional
format data type operations, register Single Instruction
Multiple Data (SIMD) operations, such as add,
subtract, multiply, and shift. In addition, the extension
includes the following features that are essential in
making DSP algorithms computationally efficient:
•
•
•
•
Support for multiplication of complex operands
Variable bit insertion and extraction
Implementation and use of virtual circular buffers
Arithmetic saturation and overflow handling
support
• Zero cycle overhead saturation and rounding
operations
DS60001191F-page 53
PIC32MZ Embedded Connectivity (EC) Family
3.7
microAptiv™ Core Configuration
Register 3-1 through Register 3-4 show the default
configuration of the microAptiv core, which is included
on PIC32MZ EC family devices.
REGISTER 3-1:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-1
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
ISP
R-1
R-0
R-0
R-1
R-0
U-0
DSP
UDI
SB
MDU
—
R-0
R-0
R-0
R-0
BE
AT<1:0>
R-0
R-1
U-0
U-0
U-0
U-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
R-0
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R-0
MM<1:0>
R-1
AR<2:0>
MT<0>
Bit
24/16/8/0
BM
R-0
R-0
MT<2:1>
R/W-0
R/W-1
R/W-0
K0<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as ‘0’
bit 24
ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23
DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22
UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21
SB: SimpleBE bit
1 = Only Simple Byte Enables are allowed on the internal bus interface
bit 20
MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19
Unimplemented: Read as ‘0’
bit 18-17 MM<1:0>: Merge Mode bits
10 = Merging is allowed
bit 16
BM: Burst Mode bit
0 = Burst order is sequential
bit 15
BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT<1:0>: Architecture Type bits
00 = MIPS32
bit 12-10 AR<2:0>: Architecture Revision Level bits
001 = MIPS32 Release 2
bit 9-7
MT<2:0>: MMU Type bits
001 = microAptiv MPU Microprocessor core uses a TLB-based MMU
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
K0<2:0>: Kseg0 Coherency Algorithm bits
011 = Cacheable, non-coherent, write-back, write allocate
010 = Uncached
001 = Cacheable, non-coherent, write-through, write allocate
000 = Cacheable, non-coherent, write-through, no write allocate
All other values are not used and are mapped to other values. Values 100, 101, and 110 are mapped
to 010. Value 111 is mapped to 010.
DS60001191F-page 54
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 3-2:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
r-1
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R-1
R-1
R-1
R-1
—
R-0
MMU Size<5:0>
R-1
R-0
R-0
R-0
R-0
IS<1:0>
R-0
R-1
IS<2>
R-1
R-0
R-1
R-1
IL<2:0>
R-1
R-1
IA<2:0>
R-0
DS<2:0>
R-0
DL<2:0>
R-1
DA<2:1>
R-1
U-0
U-0
R-1
R-1
R-0
R-1
R-0
DA<0>
—
—
PC
WR
CA
EP
FP
Legend:
R = Readable bit
r = Reserved bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Bit
24/16/8/0
x = Bit is unknown
Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.
bit 30-25 MMU Size<5:0>: Contains the number of TLB entries minus 1
001111 = 16 TLB entries
bit 24-22 IS<2:0>: Instruction Cache Sets bits
010 = Contains 256 instruction cache sets per way
bit 21-19 IL<2:0>: Instruction-Cache Line bits
011 = Contains instruction cache line size of 16 bytes
bit 18-16 IA<2:0: Instruction-Cache Associativity bits
011 = Contains 4-way instruction cache associativity
bit 15-13 DS<2:0>: Data-Cache Sets bits
000 = Contains 64 data cache sets per way
bit 12-10 DL<2:0>: Data-Cache Line bits
011 = Contains data cache line size of 16 bytes
bit 9-7
DA<2:0>: Data-Cache Associativity bits
011 = Contains the 4-way set associativity for the data cache
bit 6-5
bit 4
Unimplemented: Read as ‘0’
PC: Performance Counter bit
1 = The processor core contains Performance Counters
bit 3
WR: Watch Register Presence bit
1 = No Watch registers are present
bit 2
CA: Code Compression Implemented bit
0 = No MIPS16e® present
bit 1
EP: EJTAG Present bit
1 = Core implements EJTAG
FP: Floating Point Unit bit
0 = Floating Point Unit is not implemented
bit 0
 2013-2016 Microchip Technology Inc.
DS60001191F-page 55
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 3-3:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
r-1
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
R-1
R-0
R-0
R-0
R-1
R/W-y
MCU
ISAONEXC(1)
—
R-y
IPLW<1:0>
R-y
ISA<1:0>(1)
MMAR<2:0>
R-1
R-1
R-1
R-1
U-0
R-1
ULRI
RXI
DSP2P
DSPP
—
ITL
U-0
R-1
R-1
R-0
R-1
U-0
U-0
R-0
—
VEIC
VINT
SP
CDMM
—
—
TL
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
y = Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired as ‘1’ to indicate the presence of the Config4 register
bit 30-23 Unimplemented: Read as ‘0’
bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8-bits in width
bit 20-18 MMAR<2:0>: microMIPS Architecture Revision Level bits
000 = Release 1
bit 17
MCU: MIPS MCU ASE Implemented bit
1 = MCU ASE is implemented
bit 16
ISAONEXC: ISA on Exception bit(1)
1 = microMIPS is used on entrance to an exception vector
0 = MIPS32 ISA is used on entrance to an exception vector
bit 15-14 ISA<1:0>: Instruction Set Availability bits(1)
11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset
10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset
bit 13
ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12
RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11
DSP2P: MIPS DSP ASE Revision 2 Presence bit
1 = DSP Revision 2 is present
bit 10
DSPP: MIPS DSP ASE Presence bit
1 = DSP is present
bit 9
Unimplemented: Read as ‘0’
bit 8
ITL: Indicates that iFlowtrace hardware is present
1 = The iFlowtrace is implemented in the core
bit 7
Unimplemented: Read as ‘0’
bit 6
VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5
VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4
SP: Small Page bit
0 = 4 KB page size
bit 3
CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TL: Trace Logic bit
0 = Trace logic is not implemented
Note 1:
These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0<6>).
DS60001191F-page 56
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 3-4:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-1
—
—
—
—
—
—
—
NF
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
NF: Nested Fault bit
1 = Nested Fault feature is implemented
REGISTER 3-5:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CONFIG7: CONFIGURATION REGISTER 7; CP0 REGISTER 16, SELECT 7
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
WII
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
WII: Wait IE Ignore bit
1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction
bit 30-0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 57
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 58
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. This document is
not intended to be a comprehensive
reference
source.
For
detailed
information, refer to Section 48. “Memory Organization and Permissions”
(DS60001214), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MZ EC microcontrollers provide 4 GB of unified
virtual memory address space. All memory regions,
including program, data memory, Special Function
Registers (SFRs) and Configuration registers, reside in
this address space at their respective unique
addresses. The program and data memories can be
optionally partitioned into user and kernel memories. In
addition, PIC32MZ EC devices allow execution from
data memory.
4.1
Memory Layout
PIC32MZ EC microcontrollers implement two address
schemes: virtual and physical. All hardware resources,
such as program memory, data memory and peripherals, are located at their respective physical addresses.
Virtual addresses are exclusively used by the CPU to
fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master
peripherals, such as DMA and the Flash controller, that
access memory independently of the CPU.
The main memory maps for the PIC32MZ EC devices
are illustrated in Figure 4-1 through Figure 4-4.
Figure 4-5 provides memory map information for boot
Flash and boot alias. Table 4-1 provides memory map
information for SFRs.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1/KSEG2/KSEG3) mode address space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept 
runaway code
• Cacheable (KSEG0/KSEG2) and non-cacheable
(KSEG1/KSEG3) address regions
• Read-Write permission access to predefined
memory regions
 2013-2016 Microchip Technology Inc.
DS60001191F-page 59
PIC32MZ Embedded Connectivity (EC) Family
MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY(1,2)
0xD4000000
0xD3FFFFFF
0xD0000000
0xC4000000
0xC3FFFFFF
0xC0000000
0xBFFFFFFF
0xBFC74000
0xBFC73FFF
0xBFC00000
0xBF900000
0xBF8FFFFF
0xBF800000
0xBD080000
0xBD07FFFF
Reserved
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
KSEG3(4)
(not cacheable)
0xE4000000
0xE3FFFFFF
0xE0000000
Physical
Memory Map
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
External Memory via
EBI
Reserved
Boot Flash
(see Figure 4-5)
Reserved
Reserved
Boot Flash
(see Figure 4-5)
SFRs
(see Table 4-1)
Reserved
SFRs
(see Table 4-1)
Reserved
0x30000000
0x24000000
0x23FFFFFF
0x20000000
0x1FC74000
0x1FC73FFF
0x1FC00000
0x1F900000
0x1F8FFFFF
0x1F800000
0x1D080000
0x1D07FFFF
Program Flash
0x1D000000
RAM(3)
Reserved
0xFFFFFFFF
0x40000000
0x3FFFFFFF
0x34000000
0x33FFFFFF
Reserved
Reserved
Program Flash
0xBD000000
0xA0020000
External Memory via
SQI
Reserved
KSEG2(4)
(cacheable)
0xFFFFFFFF
0xF4000000
0xF3FFFFFF
0xF0000000
Virtual
Memory Map
KSEG1
(not cacheable)
FIGURE 4-1:
0x00020000
0x0001FFFF
0x00000000
0xA001FFFF
RAM(3)
0xA0000000
0x9FC00000
Reserved
Boot Flash
(see Figure 4-5)
Reserved
0x9D080000
0x9D07FFFF
Program Flash
KSEG0
(cacheable)
0x9FC74000
0x9FC73FFF
0x9D000000
0x80020000
0x8001FFFF
Reserved
RAM(3)
0x80000000
0x00000000
Note
DS60001191F-page 60
1:
2:
3:
4:
Reserved
Memory areas are not shown to scale.
The Cache, MMU, and TLB are initialized by compiler start-up code.
RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
The MMU must be enabled and the TLB must be set up to access this segment.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND
256 KB OF RAM(1,2)
0xD4000000
0xD3FFFFFF
0xD0000000
0xC4000000
0xC3FFFFFF
0xC0000000
0xBFFFFFFF
0xBFC74000
0xBFC73FFF
0xBFC00000
0xBF900000
0xBF8FFFFF
0xBF800000
0xBD080000
0xBD0FFFFF
Reserved
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
KSEG3(4)
(not cacheable)
0xE4000000
0xE3FFFFFF
0xE0000000
Physical
Memory Map
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
External Memory via
EBI
Reserved
Boot Flash
(see Figure 4-5)
Reserved
Reserved
Boot Flash
(see Figure 4-5)
SFRs
(see Table 4-1)
Reserved
SFRs
(see Table 4-1)
Reserved
0x34000000
0x33FFFFFF
0x30000000
0x24000000
0x23FFFFFF
0x20000000
0x1FC74000
0x1FC73FFF
0x1FC00000
0x1F900000
0x1F8FFFFF
0x1F800000
0x1D100000
0x1D0FFFFF
Program Flash
0x1D000000
(3)
RAM
Reserved
0xFFFFFFFF
Reserved
Reserved
Program Flash
0xBD000000
0xA0020000
External Memory via
SQI
Reserved
KSEG2(4)
(cacheable)
0xFFFFFFFF
0xF4000000
0xF3FFFFFF
0xF0000000
Virtual
Memory Map
KSEG1
(not cacheable)
FIGURE 4-2:
0x00080000
0x0003FFFF
0x00000000
0xA003FFFF
RAM(3)
0xA0000000
0x9FC00000
Reserved
Boot Flash
(see Figure 4-5)
Reserved
0x9D080000
0x9D0FFFFF
Program Flash
KSEG0
(cacheable)
0x9FC74000
0x9FC73FFF
0x9D000000
0x80020000
0x8003FFFF
Reserved
RAM(3)
0x80000000
0x00000000
Note
1:
2:
3:
4:
Reserved
Memory areas are not shown to scale.
The Cache, MMU, and TLB are initialized by compiler start-up code.
RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
The MMU must be enabled and the TLB must be set up to access this segment.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 61
PIC32MZ Embedded Connectivity (EC) Family
MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND
512 KB OF RAM(1,2)
0xD4000000
0xD3FFFFFF
0xD0000000
0xC4000000
0xC3FFFFFF
0xC0000000
0xBFFFFFFF
0xBFC74000
0xBFC73FFF
0xBFC00000
0xBF900000
0xBF8FFFFF
0xBF800000
0xBD080000
0xBD0FFFFF
Reserved
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
KSEG3(4)
(not cacheable)
0xE4000000
0xE3FFFFFF
0xE0000000
Physical
Memory Map
External Memory via
SQI
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
External Memory via
EBI
Reserved
Boot Flash
(see Figure 4-5)
Reserved
Reserved
Boot Flash
(see Figure 4-5)
SFRs
(see Table 4-1)
Reserved
SFRs
(see Table 4-1)
Reserved
0x30000000
0x24000000
0x23FFFFFF
0x20000000
0x1FC74000
0x1FC73FFF
0x1FC00000
0x1F900000
0x1F8FFFFF
0x1F800000
0x1D100000
0x1D0FFFFF
Program Flash
0x1D000000
(3)
RAM
Reserved
0x34000000
0x33FFFFFF
Reserved
Reserved
Program Flash
0xBD000000
0xA0020000
0xFFFFFFFF
Reserved
KSEG2(4)
(cacheable)
0xFFFFFFFF
0xF4000000
0xF3FFFFFF
0xF0000000
Virtual
Memory Map
KSEG1
(not cacheable)
FIGURE 4-3:
0x00080000
0x0007FFFF
0x00000000
0xA007FFFF
RAM(3)
0xA0000000
0x9FC00000
Reserved
Boot Flash
(see Figure 4-5)
Reserved
0x9D080000
0x9D0FFFFF
Program Flash
KSEG0
(cacheable)
0x9FC74000
0x9FC73FFF
0x9D000000
0x80020000
0x8007FFFF
Reserved
RAM(3)
0x80000000
0x00000000
Note
DS60001191F-page 62
1:
2:
3:
4:
Reserved
Memory areas are not shown to scale.
The Cache, MMU, and TLB are initialized by compiler start-up code.
RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
The MMU must be enabled and the TLB must be set up to access this segment.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
MEMORY MAP FOR DEVICES WITH 2048 KB OF PROGRAM MEMORY(1,2)
0xD4000000
0xD3FFFFFF
0xD0000000
0xC4000000
0xC3FFFFFF
0xC0000000
0xBFFFFFFF
0xBFC74000
0xBFC73FFF
0xBFC00000
0xBF900000
0xBF8FFFFF
0xBF800000
0xBD080000
0xBD1FFFFF
Reserved
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
KSEG3(4)
(not cacheable)
0xE4000000
0xE3FFFFFF
0xE0000000
Physical
Memory Map
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
External Memory via
EBI
Reserved
Boot Flash
(see Figure 4-5)
Reserved
Reserved
Boot Flash
(see Figure 4-5)
SFRs
(see Table 4-1)
Reserved
SFRs
(see Table 4-1)
Reserved
0x34000000
0x33FFFFFF
0x30000000
0x24000000
0x23FFFFFF
0x20000000
0x1FC74000
0x1FC73FFF
0x1FC00000
0x1F900000
0x1F8FFFFF
0x1F800000
0x1D200000
0x1D1FFFFF
Program Flash
0x1D000000
RAM(3)
Reserved
0xFFFFFFFF
Reserved
Reserved
Program Flash
0xBD000000
0xA0020000
External Memory via
SQI
Reserved
KSEG2(4)
(cacheable)
0xFFFFFFFF
0xF4000000
0xF3FFFFFF
0xF0000000
Virtual
Memory Map
KSEG1
(not cacheable)
FIGURE 4-4:
0x00080000
0x0007FFFF
0x00000000
0xA007FFFF
RAM(3)
0xA0000000
0x9FC00000
Reserved
Boot Flash
(see Figure 4-5)
Reserved
0x9D080000
0x9D1FFFFF
Program Flash
KSEG0
(cacheable)
0x9FC74000
0x9FC73FFF
0x9D000000
0x80020000
0x8007FFFF
Reserved
RAM(3)
0x80000000
0x00000000
Note
1:
2:
3:
4:
Reserved
Memory areas are not shown to scale.
The Cache, MMU, and TLB are initialized by compiler start-up code.
RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
The MMU must be enabled and the TLB must be set up to access this segment.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 63
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 4-5:
BOOT AND ALIAS
MEMORY MAP
0x1FC74000
Sequence/Configuration Space(3)
0x1FC70000
0x1FC6FF00
Boot Flash 2
0x1FC60000
Reserved
0x1FC54028
Number(5)
ADC Calibration Space
SFR MEMORY MAP
Virtual Address
Peripheral
Physical Memory Map(1)
Serial
TABLE 4-1:
(3)
System Bus(1)
Sequence/Configuration Space
0x6000
Crypto
0x5000
USB
0xBF8E0000
SQI1
0x1FC54000
0x0000
0x1FC50000
0x1FC4FF00
0xBF880000
CAN1 and CAN2
PORTA-PORTK
0xBF860000
0x1FC30000
0x1FC2FF00
0x1FC14000
0x1FC10000
0x1FC0FF00
Lower Boot Alias
4:
5:
6:
Memory areas are not shown to scale.
Memory locations 0x1FC0FF40
through 0x1FC0FFFC are used to
initialize Configuration registers (see
Section 34.0 “Special Features”).
Memory locations 0x1FC54000 through
0x1FC54010 are used to initialize the
ADC Calibration registers (see
Section 34.0 “Special Features”).
Refer toSection 4.1.1 “Boot Flash
Sequence and Configuration
Spaces” for more information.
Memory locations 0x1FC54020 and
0x1FC54024 contain a unique device
serial number (see Section 34.0
“Special Features”).
This configuration space cannot be
used for executing code in the upper
boot alias.
DS60001191F-page 64
0x0000
ADC1
0xB000
0xBF840000
0x4000
IC1-IC9
0x2000
Timer1-Timer9
0x0000
PMP
0xE000
0xBF820000
SPI1-SPI6
I2C1-I2C5
0x2000
0x1000
0x0000
DMA
Reserved
0x0000
0xC000
UART1-UART6
0x1FC20000
0x2000
Comparator 1, 2
OC1-OC9
Upper Boot Alias
3:
0x2000
0x1000
0x1FC34000
Note 1:
2:
0x3000
Prefetch
Reserved
Configuration Space(2,3)
0x0000
EBI
0x1FC40000
Unused Configuration Space
0xBF8F0000
0x1FC54020
Boot Flash 1
(6)
Offset
Start
RNG
Ethernet
(4)
Base
Interrupt Controller
0xBF810000
0x1000
0x0000
PPS
0x1400
Oscillator
0x1200
CVREF
0x0E00
RTCC
Deadman Timer
0xBF800000
0x0C00
0x0A00
Watchdog Timer
0x0800
Flash Controller
0x0600
Configuration
0x0000
Note 1:
Refer to 4.2 “System Bus Arbitration”
for important legal information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
4.1.1
BOOT FLASH SEQUENCE AND
CONFIGURATION SPACES
Sequence space is used to identify which boot Flash is
aliased by aliased regions. If the value programmed
into the TSEQ<15:0> bits of the BF1SEQ0 word is
equal to or greater than the value programmed into the
TSEQ<15:0> bits of the BF2SEQ0 word, Boot Flash 1
is aliased by the lower boot alias region, and Boot
Flash 2 is aliased by the upper boot alias region. If
TSEQ<15:0> bits of BF2SEQ0 is greater than
TSEQ<15:0> bits of BF1SEQ0, the opposite is true
(see Table 4-2 and Table 4-3 for BFxSEQ0 word
memory locations).
4.1.2
ALTERNATE SEQUENCE AND
CONFIGURATION WORDS
Every word in the configuration space and sequence
space has an associated alternate word (designated by
the letter A as the first letter in the name of the word).
During device start-up, primary words are read and if
uncorrectable ECC errors are found, the BCFGERR
(RCON<27>) flag is set and alternate words are used.
If uncorrectable ECC errors are found in primary and
alternate words, the BCFGFAIL (RCON<26>) flag is
set and the default configuration is used.
The CSEQ<15:0> bits must contain the complement
value of the TSEQ<15:0> bits; otherwise, the value of
TSEQ<15:0> is considered invalid, and an alternate
sequence is used. See Section 4.1.2 “Alternate
Sequence and Configuration Words” for more
information.
Once boot Flash memories are aliased, configuration
space located in the lower boot alias region is used as
the basis for the Configuration words, DEVSIGN0,
DEVCP0, and DEVCFGx (and the associated alternate
configuration registers). This means that the boot Flash
region to be aliased by lower boot alias region memory
must contain configuration values in the appropriate
memory locations.
Note:
Do not use word program operation
(NVMOP<3:0> = 0001) when programming data into the sequence and
configuration spaces.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 65
BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY
ABF1DEVCFG3
ABF1DEVCFG2
ABF1DEVCFG1
ABF1DEVCFG0
ABF1DEVCP3
ABF1DEVCP2
ABF1DEVCP1
ABF1DEVCP0
ABF1DEVSIGN3
ABF1DEVSIGN2
ABF1DEVSIGN1
ABF1DEVSIGN0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
 2013-2016 Microchip Technology Inc.
31:0
31:0
31:0
31:0
31:0
31:0
Note: See Table 34-2 for the bit descriptions.
31:0
31:0
31:0
31:0
31:0
31:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF70 ABF1SEQ3
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
FF74 ABF1SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF78 ABF1SEQ1
—
—
—
—
—
—
—
—
—
—
—
15:0
CSEQ<15:0>
31:16
FF7C ABF1SEQ0
15:0
TSEQ<15:0>
31:0
FFC0 BF1DEVCFG3
FFC4 BF1DEVCFG2
31:0
FFC8 BF1DEVCFG1
31:0
FFCC BF1DEVCFG0
31:0
FFD0 BF1DEVCP3
31:0
FFD4 BF1DEVCP2
31:0
Note: See Table 34-1 for the bit descriptions.
FFD8 BF1DEVCP1
31:0
FFDC BF1DEVCP0
31:0
FFE0 BF1DEVSIGN3
31:0
FFE4 BF1DEVSIGN2
31:0
FFE8 BF1DEVSIGN1
31:0
FFEC BF1DEVSIGN0
31:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF0 BF1SEQ3
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF4 BF1SEQ2
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF8 BF1SEQ1
15:0
—
—
—
—
—
—
—
—
—
—
—
CSEQ<15:0>
31:16
FFFC BF1SEQ0
15:0
TSEQ<15:0>
Legend:
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Reset
Register
Name
FF40
FF44
FF48
FF4C
FF50
FF54
FF58
FF5C
FF60
FF64
FF68
FF6C
Bit Range
Virtual Address
(BFC4_#)
Bits
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 66
TABLE 4-2:
BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY
ABF2DEVCFG3
ABF2DEVCFG2
ABF2DEVCFG1
ABF2DEVCFG0
ABF2DEVCP3
ABF2DEVCP2
ABF2DEVCP1
ABF2DEVCP0
ABF2DEVSIGN3
ABF2DEVSIGN2
ABF2DEVSIGN1
ABF2DEVSIGN0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
DS60001191F-page 67
31:0
31:0
31:0
31:0
31:0
31:0
Note: See Table 34-2 for the bit descriptions.
31:0
31:0
31:0
31:0
31:0
31:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF70 ABF2SEQ3
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
FF74 ABF2SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF78 ABF2SEQ1
—
—
—
—
—
—
—
—
—
—
—
15:0
CSEQ<15:0>
31:16
FF7C ABF2SEQ0
15:0
TSEQ<15:0>
31:0
FFC0 BF2DEVCFG3
FFC4 BF2DEVCFG2
31:0
FFC8 BF2DEVCFG1
31:0
FFCC BF2DEVCFG0
31:0
FFD0 BF2DEVCP3
31:0
FFD4 BF2DEVCP2
31:0
Note: See Table 34-1 for the bit descriptions.
FFD8 BF2DEVCP1
31:0
FFDC BF2DEVCP0
31:0
FFE0 BF2DEVSIGN3
31:0
FFE4 BF2DEVSIGN2
31:0
FFE8 BF2DEVSIGN1
31:0
FFEC BF2DEVSIGN0
31:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF0 BF2SEQ3
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF4 BF2SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF8 BF2SEQ1
15:0
—
—
—
—
—
—
—
—
—
—
—
CSEQ<15:0>
31:16
FFFC BF2SEQ0
15:0
TSEQ<15:0>
Legend:
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Register
Name
FF40
FF44
FF48
FF4C
FF50
FF54
FF58
FF5C
FF60
FF64
FF68
FF6C
Bit Range
Virtual Address
(BFC6_#)
Bits
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-3:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-1:
Bit
Range
31:24
23:16
15:8
7:0
BFxSEQ0/ABFxSEQ0: BOOT FLASH ‘x’ SEQUENCE WORD 0 REGISTER 
(‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
CSEQ<15:8>
CSEQ<7:0>
R/P
R/P
R/P
R/P
TSEQ<15:8>
R/P
R/P
R/P
R/P
R/P
TSEQ<7:0>
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 CSEQ<15:0>: Boot Flash Complement Sequence Number bits
bit 15-0
Note:
TSEQ<15:0>: Boot Flash True Sequence Number bits
The BFxSEQ1 through BFxSEQ3 and ABFxSEQ1 through ABFxSEQ3 registers are used for Quad Word
programming operation when programming the BFxSEQ0/ABFxSEQ0 registers, and do not contain any
valid information.
DS60001191F-page 68
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
4.2
Note:
System Bus Arbitration
The
System
Bus
interconnect
implements one or more instantiations of
the SonicsSX® interconnect from Sonics,
Inc. This document contains materials
that are (c) 2003-2015 Sonics, Inc., and
that constitute proprietary information of
Sonics, Inc. SonicsSX is a registered
trademark of Sonics, Inc. All such
materials and trademarks are used under
license from Sonics, Inc.
As shown in the PIC32MZ EC Family Block Diagram
(see Figure 1-1), there are multiple initiator modules
(I1 through I14) in the system that can access
various target modules (T1 through T13). Table 4-4
illustrates which initiator can access which target.
The System Bus supports simultaneous access to
targets by initiators, so long as the initiators are
accessing different targets. The System Bus will
perform arbitration, if multiple initiators attempt to
access the same target.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 69
INITIATORS TO TARGETS ACCESS ASSOCIATION
Initiator ID
Target
#
2
3
4
CPU
DMA Read
Flash Memory:
Program Flash
Boot Flash
Prefetch Module
X
X
2
RAM Bank 1 Memory
X
X
3
RAM Bank 2 Memory
X
X
4
External Memory via EBI and EBI Module
X
5
Peripheral Set 1:
System Control, Flash Control, DMT,
RTCC, CVR, PPS Input, PPS Output, 
Interrupts, DMA, WDT
1
Name
1
5
6
DMA Write
7
USB
8
9
Ethernet Ethernet
Read
Write
10
11
12
13
14
CAN1
CAN2
SQI1
Flash
Controller
Crypto
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Peripheral Set 2:
SPI1-SPI6
I2C1-I2C5
UART1-UART6
PMP
X
X
X
Peripheral Set 3:
Timer1-Timer9
IC1-IC9
OC1-OC9
ADC1
Comparator 1
Comparator 2
X
X
X
8
Peripheral Set 4:
PORTA-PORTK
X
X
X
9
Peripheral Set 5:
CAN1
CAN2
Ethernet Controller
X
X
X
10
Peripheral Set 6:
USB
X
11
External Memory via SQI1 and
SQI1 Module
X
12
Peripheral Set 7:
Crypto Engine
X
13
Peripheral Set 8:
RNG Module
X
6
7
X
X
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 70
TABLE 4-4:
PIC32MZ Embedded Connectivity (EC) Family
The System Bus arbitration scheme implements a nonprogrammable, Least Recently Serviced (LRS) priority,
which provides Quality Of Service (QOS) for most
initiators. However, some initiators can use Fixed High
Priority (HIGH) arbitration to guarantee their access to
data.
4.3
The arbitration scheme for the available initiators is
shown in Table 4-5.
The System Bus divides the entire memory space into
fourteen target regions and permits access to each
target by initiators via permission groups. Four
Permission Groups (0 through 3) can be assigned to
each initiator. Each permission group is independent
of the others and can have exclusive or shared
access to a region.
TABLE 4-5:
Name
INITIATOR ID AND QOS
ID
QOS
CPU
1
LRS(1)
CPU
2
HIGH(1,2)
DMA Read
3
LRS(1)
DMA Read
4
HIGH(1,2)
DMA Write
5
LRS(1)
DMA Write
6
HIGH(1,2)
USB
7
LRS
Ethernet Read
8
LRS
Ethernet Write
9
LRS
CAN1
10
LRS
CAN2
11
LRS
SQI1
12
LRS
Flash Controller
13
HIGH(2)
Crypto
14
LRS
Note 1:
2:
When accessing SRAM, the DMAPRI bit
(CFGCON<25>) and the CPUPRI bit
(CFGCON<24>) provide arbitration control for the DMA and CPU (when servicing
an interrupt (i.e., EXL = 1)), respectively,
by selecting the use of LRS or HIGH
When using HIGH, the DMA and CPU get
arbitration preference over all initiators
using LRS.
Using HIGH arbitration can have serious
negative effects on other initiators.
Therefore, it is recommended to not
enable this type of arbitration for an
initiator that uses significant system bandwidth. HIGH arbitration is intended to be
used for low bandwidth applications that
require low latency, such as LCC graphics
applications.
 2013-2016 Microchip Technology Inc.
Permission Access and System
Bus Registers
The System Bus on PIC32MZ EC family of
microcontrollers provides access control capabilities
for the transaction initiators on the System Bus.
Using the CFGPG register (see Register 34-10 in
Section 34.0 “Special Features”), Boot firmware can
assign a permission group to each initiator, which can
make requests on the System Bus.
The available targets and their regions, as well as the
associated control registers to assign protection, are
described and listed in Table 4-6.
Register 4-2 through Register 4-10 are used for setting
and controlling access permission groups and regions.
To change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PGLOCK Configuration bit (CFGCON<11>). Setting
PGLOCK prevents writes to the control registers;
clearing PGLOCK allows writes.
To set or clear the PGLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
DS60001191F-page 71
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS
SBTxREGy Register
Target
Number
Target Description(5)
Name
System Bus
0
SBT0REG0
SBT0REG1
Flash Memory(6):
Program Flash
Boot Flash
Prefetch Module
1
RAM Bank 1 Memory
2
RAM Bank 2 Memory
3
Physical
Start
Address
Region Size
(SIZE<4:0>)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
R
0x1F8F0000
R
64 KB
—
0
R
0x1F8F8000
R
0x1D000000
SBT1REG2
R
0x1F8E0000
R
R
(4)
R
32 KB
R
(4)
4 KB
—
3
Name
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
 2013-2016 Microchip Technology Inc.
Legend:
Note 1:
2:
3:
4:
5:
6:
Name
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
SBT0RD0
R/W(1)
SBT0WR0
R/W(1)
SBT0RD1
R/W
(1)
SBT0WR1
R/W(1)
(1)
—
0
SBT1RD0
R/W
SBT1WR0
0, 0, 0, 0
1
2
SBT1RD2
R/W(1)
SBT1WR2
R/W(1)
SBT1REG3
R/W
R/W
R/W
R/W
1
2
SBT1RD3
SBT1WR3
0, 0, 0, 0
SBT1REG4
R/W
R/W
R/W
R/W
1
2
SBT1RD4
R/W(1)
SBT1WR4
0, 0, 0, 0
SBT1REG5
R/W
R/W
R/W
R/W
1
2
SBT1RD5
R/W(1)
SBT1WR5
0, 0, 0, 0
SBT1REG6
R/W
R/W
R/W
R/W
1
2
SBT1RD6
R/W(1)
SBT1WR6
0, 0, 0, 0
SBT1REG7
R/W
R/W
R/W
R/W
0
1
SBT1RD7
R/W(1)
SBT1WR7
0, 0, 0, 0
SBT1REG8
R/W
R/W
R/W
R/W
0
1
SBT1RD8
R/W(1)
SBT1WR8
0, 0, 0, 0
SBT2REG0
R
0x00000000
R(4)
R(4)
—
0
SBT2RD0
R/W(1)
SBT2WR0
R/W(1)
SBT2RD1
R/W(1)
SBT2WR1
R/W(1)
SBT2REG1
R/W
R/W
R/W
R/W
SBT2REG2
R/W
R/W
R/W
R/W
0
1
SBT2RD2
R/W(1)
SBT2WR2
R/W(1)
SBT3REG0
R(4)
R(4)
R(4)
R(4)
—
0
SBT3RD0
R/W(1)
SBT3WR0
R/W(1)
SBT3RD1
R/W
(1)
SBT3WR1
R/W(1)
SBT3RD2
R/W(1)
SBT3WR2
R/W(1)
SBT4RD0
R/W(1)
SBT4WR0
R/W(1)
SBT4RD2
R/W(1)
SBT4WR2
R/W(1)
SBT4REG0
SBT4REG2
R/W
R/W
R
R
R/W
R/W
0x20000000
0x1F8E1000
R/W
R/W
R
R
R/W
R/W
64 MB
4 KB
—
—
0
—
0
3
3
1
0
1
R/W(1)
5
SBTxWRy Register
R/W(1)
SBT3REG2
4
Region Base
(BASE<21:0>)
(see Note 2)
SBT1REG0
SBT3REG1
External Memory via EBI and EBI
Module(6)
SBTxRDy Register
Peripheral Set 1:
—
0
SBT5RD0
SBT5WR0
R/W(1)
SBT5REG0
R
0x1F800000
R
128 KB
System Control
SBT5REG1
R/W
R/W
R/W
R/W
—
3
SBT5RD1
R/W(1)
SBT5WR1
R/W(1)
Flash Control
DMT/WDT
RTCC
CVR
PPS Input
SBT5REG2
R/W
R/W
R/W
R/W
0
1
SBT5RD2
R/W(1)
SBT5WR2
R/W(1)
PPS Output
Interrupts
DMA
R = Read;
R/W = Read/Write;
‘x’ in a register name = 0-13;
‘y’ in a register name = 0-8.
Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
See Table 4-1for information on specific target memory size and start addresses.
The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 72
TABLE 4-6:
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)
SBTxREGy Register
Target
Number
6
7
8
9
10
11
12
13
Legend:
Note 1:
2:
3:
4:
5:
6:
Target Description(5)
Peripheral Set 5:
CAN1
CAN2
Ethernet Controller
Peripheral Set 6:
USB
External Memory via SQI1 and
SQI1 Module
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
SBTxWRy Register
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Region Base
(BASE<21:0>)
(see Note 2)
Physical
Start
Address
Region Size
(SIZE<4:0>)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
SBT6REG0
R
0x1F820000
R
64 KB
—
0
SBT6RD0
R/W(1)
SBT6WR0
R/W(1)
SBT6REG1
R/W
R/W
R/W
R/W
—
3
SBT6RD1
R/W(1)
SBT6WR1
R/W(1)
SBT7REG0
R
0x1F840000
R
64 KB
—
0
SBT7RD0
R/W(1)
SBT7WR0
R/W(1)
SBT7REG1
R/W
R/W
R/W
R/W
—
3
SBT7RD1
R/W(1)
SBT7WR1
R/W(1)
SBT8REG0
R
0x1F860000
R
64 KB
—
0
SBT8RD0
R/W(1)
SBT8WR0
R/W(1)
SBT8REG1
R/W
R/W
R/W
R/W
—
3
SBT8RD1
R/W(1)
SBT8WR1
R/W(1)
SBT9WR0
R/W(1)
Name
Peripheral Set 2:
SPI1-SPI6
I2C1-I2C5
UART1-UART6
PMP
Peripheral Set 3:
Timer1-Timer9
IC1-IC9
OC1-OC9
ADC1
Comparator 1
Comparator 2
Peripheral Set 4:
PORTA-PORTK
SBTxRDy Register
Name
Name
SBT9REG0
R
0x1F880000
R
64 KB
—
0
SBT9RD0
R/W(1)
SBT9REG1
R/W
R/W
R/W
R/W
—
3
SBT9RD1
R/W(1)
SBT9WR1
R/W(1)
SBT10REG0
R
0x1F8E3000
R
4 KB
—
0
SBT10RD0
R/W(1)
SBT10WR0
R/W(1)
SBT11REG0
R
0x30000000
R
64 MB
—
0
SBT11RD0
R/W(1)
SBT11WR0
R/W(1)
SBT11RD1
(1)
SBT11WR1
R/W(1)
SBT11REG1
R
0x1F8E2000
R
4 KB
—
3
R/W
Peripheral Set 7:
SBT12REG0
R
0x1F8E5000
R
4 KB
—
0
SBT12RD0
R/W(1)
SBT12WR0
R/W(1)
Crypto Engine
Peripheral Set 8:
SBT13REG0
R
0x1F8E6000
R
4 KB
—
0
SBT13RD0
R/W(1)
SBT13WR0
R/W(1)
RNG Module
R = Read;
R/W = Read/Write;
‘x’ in a register name = 0-13;
‘y’ in a register name = 0-8.
Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
See Table 4-1for information on specific target memory size and start addresses.
The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.
DS60001191F-page 73
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-6:
Virtual Address
(BF8F_#)
Register
Name
Bit Range
SYSTEM BUS REGISTER MAP
0510
SBFLAG
31:16
15:0
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T13PGV
T12PGV
T11PGV
T10PGV
T9PGV
T8PGV
T7PGV
T6PGV
T5PGV
T4PGV
T3PGV
T2PGV
T1PGV
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bits
—
0000
T0PGV 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2013-2016 Microchip Technology Inc.
Register
Name
SYSTEM BUS TARGET 0 REGISTER MAP
Virtual Address
(BF8F_#)
TABLE 4-8:
8020
SBT0ELOG1
31:16 MULTI
15:0
—
8024
SBT0ELOG2
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8028
SBT0ECON
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
8030
SBT0ECLRS
31:16
15:0
—
—
—
—
—
—
—
—
—
—
8038 SBT0ECLRM
31:16
15:0
—
—
—
—
—
—
—
—
—
—
8040
SBT0REG0
31:16
15:0
8050
SBT0RD0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
8058
SBT0WR0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
8060
SBT0REG1
31:16
15:0
8070
SBT0RD1
31:16
15:0
—
—
—
—
—
—
—
—
—
—
8078
SBT0WR1
31:16
15:0
—
—
—
—
—
—
—
—
—
—
Legend:
Note:
31/15
30/14
29/13
28/12
—
—
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
—
—
REGION<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CLEAR 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CLEAR 0000
PRI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PRI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
INITID<7:0>
—
CMD<2:0>
16/0
—
All
Resets
Bit Range
Bits
—
—
GROUP<1:0>
—
—
BASE<21:6>
BASE<5:0>
SIZE<4:0>
—
BASE<21:6>
BASE<5:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
SIZE<4:0>
—
—
—
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 74
TABLE 4-7:
Virtual Address
(BF8F_#)
Register
Name
8420
SBT1ELOG1
8424
SBT1ELOG2
8428
SBT1ECON
8430
SYSTEM BUS TARGET 1 REGISTER MAP
SBT1ECLRS
8438 SBT1ECLRM
DS60001191F-page 75
8440
SBT1REG0
8450
SBT1RD0
8458
SBT1WR0
8480
SBT1REG2
8490
SBT1RD2
8498
SBT1WR2
84A0
SBT1REG3
84B0
SBT1RD3
84B8
SBT1WR3
84C0
SBT1REG4
84D0
SBT1RD4
84D8
SBT1WR4
Legend:
Note:
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
REGION<3:0>
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Bits
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-9:
Virtual Address
(BF8F_#)
Register
Name
84E0
SBT1REG5
84F0
SBT1RD5
84F8
SBT1WR5
8500
SBT1REG6
8510
SBT1RD6
8518
SBT1WR6
8520
SBT1REG7
8530
SBT1RD7
8538
SBT1WR7
8540
SBT1REG8
8550
SBT1RD8
8558
SBT1WR8
SYSTEM BUS TARGET 1 REGISTER MAP (CONTINUED)
 2013-2016 Microchip Technology Inc.
Legend:
Note:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
PRI
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
—
—
—
xxxx
—
—
—
xxxx
BASE<21:6>
15:0
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<21:6>
15:0
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 76
TABLE 4-9:
8824
8828
8830
SBT2ELOG2
SBT2ECON
SBT2ECLRS
8838 SBT2ECLRM
8840
SBT2REG0
8850
SBT2RD0
8858
SBT2WR0
8860
SBT2REG1
8870
SBT2RD1
8878
SBT2WR1
8880
SBT2REG2
DS60001191F-page 77
8890
SBT2RD2
8898
SBT2WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Register
Name
SBT2ELOG1
Bit Range
Virtual Address
(BF8F_#)
8820
SYSTEM BUS TARGET 2 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-10:
8C24 SBT3ELOG2
8C28
SBT3ECON
8C30 SBT3ECLRS
8C38 SBT3ECLRM
8C40
SBT3REG0
8C50
SBT3RD0
8C58
SBT3WR0
8C60
SBT3REG1
 2013-2016 Microchip Technology Inc.
8C70
SBT3RD1
8C78
SBT3WR1
8C80
SBT3REG2
8C90
SBT3RD2
8C98
SBT3WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
8C20 SBT3ELOG1
SYSTEM BUS TARGET 3 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 78
TABLE 4-11:
9024
9028
9030
SBT4ELOG2
SBT4ECON
SBT4ECLRS
9038 SBT4ECLRM
9040
SBT4REG0
9050
SBT4RD0
9058
SBT4WR0
9080
SBT4REG2
9090
SBT4RD2
9098
SBT4WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Register
Name
SBT4ELOG1
Bit Range
Virtual Address
(BF8F_#)
9020
SYSTEM BUS TARGET 4 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
DS60001191F-page 79
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-12:
9424
9428
9430
SBT5ELOG2
SBT5ECON
SBT5ECLRS
9438 SBT5ECLRM
9440
SBT5REG0
9450
SBT5RD0
9458
SBT5WR0
9460
SBT5REG1
 2013-2016 Microchip Technology Inc.
9470
SBT5RD1
9478
SBT5WR1
9480
SBT5REG2
9490
SBT5RD2
9498
SBT5WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Register
Name
SBT5ELOG1
Bit Range
Virtual Address
(BF8F_#)
9420
SYSTEM BUS TARGET 5 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 80
TABLE 4-13:
9824
9828
9830
SBT6ELOG2
SBT6ECON
SBT6ECLRS
9838 SBT6ECLRM
9840
SBT6REG0
9850
SBT6RD0
9858
SBT6WR0
9860
SBT6REG1
9870
SBT6RD1
9878
SBT6WR1
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Register
Name
SBT6ELOG1
Bit Range
Virtual Address
(BF8F_#)
9820
SYSTEM BUS TARGET 6 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
DS60001191F-page 81
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-14:
9C24 SBT7ELOG2
9C28
SBT7ECON
9C30 SBT7ECLRS
9C38 SBT7ECLRM
9C40
SBT7REG0
9C50
SBT7RD0
9C58
SBT7WR0
9C60
SBT7REG1
9C70
SBT7RD1
9C78
SBT7WR1
 2013-2016 Microchip Technology Inc.
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
9C20 SBT7ELOG1
SYSTEM BUS TARGET 7 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 82
TABLE 4-15:
A024 SBT8ELOG2
A028
SBT8ECON
A030 SBT8ECLRS
A038 SBT8ECLRM
A040
SBT8REG0
A050
SBT8RD0
A058
SBT8WR0
A060
SBT8REG1
A070
SBT8RD1
A078
SBT8WR1
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
A020 SBT8ELOG1
SYSTEM BUS TARGET 8 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
DS60001191F-page 83
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-16:
A424 SBT9ELOG2
A428
SBT9ECON
A430 SBT9ECLRS
A438 SBT9ECLRM
A440
SBT9REG0
A450
SBT9RD0
A458
SBT9WR0
A460
SBT9REG1
A470
SBT9RD1
A478
SBT9WR1
 2013-2016 Microchip Technology Inc.
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
A420 SBT9ELOG1
SYSTEM BUS TARGET 9 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 84
TABLE 4-17:
A824 SBT10ELOG2
A828 SBT10ECON
A830 SBT10ECLRS
A838 SBT10ECLRM
A840
SBT10REG0
A850
SBT10RD0
A858
SBT10WR0
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
A820 SBT10ELOG1
SYSTEM BUS TARGET 10 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
DS60001191F-page 85
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 4-18:
AC24 SBT11ELOG2
AC28 SBT11ECON
AC30 SBT11ECLRS
AC38 SBT11ECLRM
AC40 SBT11REG0
AC50
SBT11RD0
AC58
SBT11WR0
AC60 SBT11REG1
AC70
SBT11RD1
AC78
SBT11WR1
 2013-2016 Microchip Technology Inc.
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
AC20 SBT11ELOG1
SYSTEM BUS TARGET 11 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE<21:6>
15:0
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 86
TABLE 4-19:
B024 SBT12ELOG2
B028 SBT12ECON
B030 SBT12ECLRS
B038 SBT12ECLRM
B040
SBT12REG0
B050
SBT12RD0
B058
SBT12WR0
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
B020 SBT12ELOG1
SYSTEM BUS TARGET 12 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 87
TABLE 4-20:
B424 SBT13ELOG2
B428 SBT13ECON
B430 SBT13ECLRS
B438 SBT13ECLRM
B440
SBT13REG0
B450
SBT13RD0
B458
SBT13WR0
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE<3:0>
23/7
—
INITID<7:0>
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION<3:0>
—
17/1
16/0
—
—
CMD<2:0>
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
B420 SBT13ELOG1
SYSTEM BUS TARGET 13 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP<1:0>
CLEAR 0000
—
BASE<5:0>
xxxx
SIZE<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
0000
CLEAR 0000
BASE<21:6>
15:0
0000
0000
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 88
TABLE 4-21:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-2:
Bit
Range
31:24
23:16
15:8
7:0
SBFLAG: SYSTEM BUS STATUS FLAG REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
T8PGV
—
—
T13PGV
T12PGV
T11PGV
T10PGV
T9PGV
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
T7PGV
T6PGV
T5PGV
T4PGV
T3PGV
T2PGV
T1PGV
T0PGV
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31-14 Unimplemented: Read as ‘0’
bit 13-0 TxPGV: Target ‘x’ Permission Group Violation Status bits (‘x’ = 0-13)
Refer to Table 4-6 for the list of available targets and their descriptions.
1 = Target is reporting a Permission Group (PG) violation
0 = Target is not reporting a PG violation
Note:
All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 89
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-3:
Bit
Range
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1 
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, C
U-0
U-0
U-0
R/W-0, C
R/W-0, C
R/W-0, C
R/W-0, C
MULTI
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
23:16
15:8
CODE<3:0>
U-0
INITID<7:0>
7:0
U-0
REGION<3:0>
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R-0
—
CMD<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31
MULTI: Multiple Permission Violations Status bit
This bit is cleared by writing a ‘1’.
1 = Multiple errors have been detected
0 = No multiple errors have been detected
bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CODE<3:0>: Error Code bits
Indicates the type of error that was detected. These bits are cleared by writing a ‘1’.
1111 = Reserved
1101 = Reserved
•
•
•
0011 = Permission violation
0010 = Reserved
0001 = Reserved
0000 = No error
bit 23-16 Unimplemented: Read as ‘0’
bit 15-8 INITID<7:0>: Initiator ID of Requester bits
11111111 = Reserved
•
•
•
00001111 = Reserved
00001110 = Crypto Engine
00001101 = Flash Controller
00001100 = SQI1
00001011 = CAN2
00001010 = CAN1
00001001 = Ethernet Write
00001000 = Ethernet Read
00000111 = USB
00000110 = DMA Write (DMAPRI (CFGCON<25>) = 1)
00000101 = DMA Write (DMAPRI (CFGCON<25>) = 0)
00000100 = DMA Read (DMAPRI (CFGCON<25>) = 1)
00000011 = DMA Read (DMAPRI (CFGCON<25>) = 0)
00000010 = CPU (CPUPRI (CFGCON<24>) = 1)
00000001 = CPU (CPUPRI (CFGCON<25>) = 0)
00000000 = Reserved
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
DS60001191F-page 90
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-3:
bit 7-4
bit 3
bit 2-0
Note:
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1 
(‘x’ = 0-13) (CONTINUED)
REGION<3:0>: Requested Region Number bits
1111 - 0000 = Target’s region that reported a permission group violation
Unimplemented: Read as ‘0’
CMD<2:0>: Transaction Command of the Requester bits
111 = Reserved
110 = Reserved
101 = Write (a non-posted write)
100 = Reserved
011 = Read (a locked read caused by a Read-Modify-Write transaction)
010 = Read
001 = Write
000 = Idle
Refer to Table 4-6 for the list of available targets and their descriptions.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 91
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-4:
Bit
Range
31:24
23:16
15:8
7:0
SBTxELOG2: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 2 (‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
GROUP<1:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 1-0
GROUP<1:0>: Requested Permissions Group bits
11 = Group 3
10 = Group 2
01 = Group 1
00 = Group 0
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
REGISTER 4-5:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECON: SYSTEM BUS TARGET ‘x’ ERROR CONTROL REGISTER 
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ERRP
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ERRP: Error Control bit
1 = Report protection group violation errors
0 = Do not report protection group violation errors
bit 23-0
Unimplemented: Read as ‘0’
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
DS60001191F-page 92
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-6:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRS: SYSTEM BUS TARGET ‘x’ SINGLE ERROR CLEAR REGISTER 
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Single Error on Read bit
A single error as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
REGISTER 4-7:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRM: SYSTEM BUS TARGET ‘x’ MULTIPLE ERROR CLEAR REGISTER
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Multiple Errors on Read bit
Multiple errors as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 93
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-8:
Bit
Range
31:24
23:16
15:8
7:0
SBTxREGy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ REGISTER 
(‘x’ = 0-13; ‘y’ = 0-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASE<21:14>
R/W-0
BASE<13:6>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
U-0
PRI
—
U-0
U-0
U-0
—
—
—
BASE<5:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIZE<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-10 BASE<21:0>: Region Base Address bits
bit 9
PRI: Region Priority Level bit
1 = Level 2
0 = Level 1
bit 8
Unimplemented: Read as ‘0’
bit 7-3
SIZE<4:0>: Region Size bits
Permissions for a region are only active is the SIZE is non-zero.
11111 = Region size = 2(SIZE – 1) x 1024 (bytes)
•
•
•
00001 = Region size = 2(SIZE – 1) x 1024 (bytes)
00000 = Region is not present
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
Refer to Table 4-6 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for
more information.
DS60001191F-page 94
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-9:
Bit
Range
31:24
23:16
15:8
7:0
SBTxRDy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ READ PERMISSIONS
REGISTER (‘x’ = 0-13; ‘y’ = 0-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
Group3: Group3 Read Permissions bits
1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission
bit 2
Group2: Group2 Read Permissions bits
1 = Privilege Group 2 has read permission
0 = Privilege Group 2 does not have read permission
bit 1
Group1: Group1 Read Permissions bits
1 = Privilege Group 1 has read permission
0 = Privilege Group 1 does not have read permission
bit 0
Group0: Group0 Read Permissions bits
1 = Privilege Group 0 has read permission
0 = Privilege Group 0 does not have read permission
Note 1:
2:
Refer to Table 4-6 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for
more information.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 95
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 4-10:
Bit
Range
31:24
23:16
15:8
7:0
SBTxWRy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ WRITE PERMISSIONS
REGISTER (‘x’ = 0-13; ‘y’ = 0-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
Group3: Group 3 Write Permissions bits
1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission
bit 2
Group2: Group 2 Write Permissions bits
1 = Privilege Group 2 has write permission
0 = Privilege Group 2 does not have write permission
bit 1
Group1: Group 1 Write Permissions bits
1 = Privilege Group 1 has write permission
0 = Privilege Group 1 does not have write permission
bit 0
Group0: Group 0 Write Permissions bits
1 = Privilege Group 0 has write permission
0 = Privilege Group 0 does not have write permission
Note 1:
2:
Refer to Table 4-6 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for
more information.
DS60001191F-page 96
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
5.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 52. “Flash
Program Memory with Support for Live
Update” (DS60001193), which is available from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
PIC32MZ EC devices contain an internal Flash
program memory for executing user code, which
includes the following features:
•
•
•
•
Two Flash banks for live update support
Dual boot support
Write protection for program and boot Flash
ECC support
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 52. “Flash
Program Memory with Support for Live Update”
(DS60001193) in the “PIC32 Family Reference
Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which is available for download from
the Microchip website.
Note:
In PIC32MZ EC devices, the Flash page
size is 16 KB (4096 IW) and the row size
is 2 KB (512 IW).
There are three methods by which the user can
program this memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 97
Flash Control Registers
Register
Name
FLASH CONTROLLER REGISTER MAP
Virtual Address
(BF80_#)
TABLE 5-1:
0600
NVMCON(1)
0610
NVMKEY
0620
NVMADDR(1)
0630
0640
0650
NVMDATA0
NVMDATA1
NVMDATA2
0660
NVMDATA3
0670
NVMSRC
ADDR
0680
NVMPWP(1)
0690
(1)
NVMBWP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
—
—
—
—
SWAP
—
—
—
31:16
31:16
0000
0000
0000
NVMADDR<31:0>
15:0
31:16
0000
0000
NVMDATA0<31:0>
15:0
31:16
0000
0000
NVMDATA1<31:0>
15:0
31:16
0000
0000
NVMDATA2<31:0>
15:0
31:16
0000
0000
NVMDATA3<31:0>
15:0
31:16
0000
0000
NVMSRCADDR<31:0>
15:0
31:16 PWPULOCK
—
—
—
—
—
—
0000
—
15:0
PWP<23:16>
8000
PWP<15:0>
—
15:0 LBWPULOCK
—
—
—
—
—
—
—
—
LBWP4
LBWP3
LBWP2
LBWP1
—
—
LBWP0 UBWPULOCK
0000
—
—
—
—
—
—
—
0000
—
—
UBWP4
UBWP3
UBWP2
UBWP1
UBWP0
9FDF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information.
1:
0000
0000
NVMKEY<31:0>
15:0
31:16
NVMOP<3:0>
All Resets
Bit Range
Bits
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 98
5.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-1:
Bit
Range
31:24
23:16
15:8
7:0
NVMCON: PROGRAMMING CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS, HC
(1)
R-0, HS, HC
(1)
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0, HC
(1)
WR
R/W-0
(1)
WREN
WRERR
LVDERR
R/W-0
U-0
U-0
U-0
SWAP
—
—
—
NVMOP<3:0>
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit(1)
This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been
performed.
1 = Initiate a Flash operation
0 = Flash operation is complete or inactive
bit 14
WREN: Write Enable bit(1)
1 = Enable writes to the WR bit and disables writes to the NVMOP<3:0> bits
0 = Disable writes to WR bit and enables writes to the NVMOP<3:0> bits
bit 13
WRERR: Write Error bit(1)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12
LVDERR: Low-Voltage Detect Error bit(1)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11-8
Unimplemented: Read as ‘0’
bit 7
SWAP: Program Flash Bank Swap Control bit
This bit can be modified only when the WREN bit is ‘0’ and the unlock sequence has been performed.
1 = Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to
the upper mapped region
0 = Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to
the upper mapped region
bit 6-4
Unimplemented: Read as ‘0’
Note 1:
2:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This operation results in a “no operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. “Flash Program Memory
with Support for Live Update” (DS60001193) for information regarding ECC and Flash programming.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 99
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-1:
bit 3-0
NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
NVMOP<3:0>: NVM Operation bits
These bits are only writable when WREN = 0.
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected,
PWP<23:0> = 0x000000)
0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program
Flash (all pages in that region must be unprotected)
0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program
Flash (all pages in that region must be unprotected)
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR, 
if it is not write-protected
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected(2)
0000 = No operation
Note 1:
2:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This operation results in a “no operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. “Flash Program Memory
with Support for Live Update” (DS60001193) for information regarding ECC and Flash programming.
DS60001191F-page 100
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-2:
Bit
Range
31:24
23:16
15:8
7:0
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Note:
W-0
31:24
23:16
15:8
7:0
W-0
W-0
W-0
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<15:8>
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMKEY<31:0>: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
NVMADDR: FLASH ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR<31:24>(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR<23:16>(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR<15:8>(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR<7:0>(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
W-0
Bit
25/17/9/1
NVMKEY<23:16>
REGISTER 5-3:
Bit
Range
W-0
Bit
26/18/10/2
NVMKEY<31:24>
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMADDR<31:0>: Flash Address bits(1)
NVMOP<3:0>
Selection
Flash Address Bits (NVMADDR<31:0>)
Page Erase
Row Program
Word Program
Quad Word Program
Note 1:
Note:
Address identifies the page to erase (NVMADDR<13:0> are ignored).
Address identifies the row to program (NVMADDR<11:0> are ignored).
Address identifies the word to program (NVMADDR<1:0> are ignored).
Address identifies the quad word (128-bit) to program (NVMADDR<3:0> bits are
ignored).
For all other NVMOP<3:0> bit settings, the Flash address is ignored. See the NVMCON
register (Register 5-1) for additional information on these bits.
The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 101
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-4:
Bit
Range
31:24
23:16
15:8
7:0
NVMDATAx: FLASH DATA REGISTER (x = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA<23:16>
R/W-0
NVMDATA<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
NVMDATA<31:0>: Flash Data bits
Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR
Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address
defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.
Note:
The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
REGISTER 5-5:
Bit
Range
31:24
23:16
15:8
7:0
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR<23:16>
R/W-0
R/W-0
NVMSRCADDR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
x = Bit is unknown
NVMSRCADDR<31:0>: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.
The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
DS60001191F-page 102
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-6:
Bit
Range
31:24
23:16
15:8
7:0
NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
PWPULOCK
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PWP<23:16>
R-0
R-0
PWP<15:8>
R-0
R-0
R-0
R-0
R-0
PWP<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
PWPULOCK: Program Flash Memory Page Write-protect Unlock bit
1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 30-24 Unimplemented: Read as ‘0’
bit 23-0
Note:
PWP<23:0>: Flash Program Write-protect (Page) Address bits
Physical memory below address 0x1Dxxxxxx is write protected, where ‘xxxxxx’ is specified by PWP<23:0>.
When PWP<23:0> has a value of ‘0’, write protection is disabled for the entire program Flash. If the specified
address falls within the page, the entire page and all pages below the current page will be protected.
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 103
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-7:
Bit
Range
31:24
23:16
15:8
7:0
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LBWPULOCK
—
—
LBWP4(1)
LBWP3(1)
LBWP2(1)
LBWP1(1)
LBWP0(1)
R/W-1
r-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
UBWPULOCK
—
—
(1)
UBWP4
Legend:
(1)
UBWP3
(1)
UBWP2
UBWP1
(1)
UBWP0(1)
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
LBWPULOCK: Lower Boot Alias Write-protect Unlock bit
1 = LBWPx bits are not locked and can be modified
0 = LBWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 14-13 Unimplemented: Read as ‘0’
bit 12
LBWP4: Lower Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled
bit 11
LBWP3: Lower Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled
bit 10
LBWP2: Lower Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled
bit 9
LBWP1: Lower Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled
bit 8
LBWP0: Lower Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled
bit 7
UBWPULOCK: Upper Boot Alias Write-protect Unlock bit
1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified
This bit is only user-clearable and cannot be set except by any reset.
bit 6
Reserved: This bit is reserved for use by development tools
bit 5
Unimplemented: Read as ‘0’
Note 1:
These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
DS60001191F-page 104
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 5-7:
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
bit 4
UBWP4: Upper Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF enabled
0 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF disabled
bit 3
UBWP3: Upper Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled
0 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF disabled
bit 2
UBWP2: Upper Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF enabled
0 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF disabled
bit 1
UBWP1: Upper Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF enabled
0 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF disabled
bit 0
UBWP0: Upper Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF enabled
0 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF disabled
Note 1:
These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 105
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 106
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
6.0
Note:
RESETS
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 7. “Resets”
(DS60001118), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
device Reset sources are as follows:
•
•
•
•
•
•
•
Power-on Reset (POR)
Master Clear Reset pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Brown-out Reset (BOR)
Configuration Mismatch Reset (CMR)
Deadman Timer Reset (DMTR)
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
MCLR
DMTR/WDTR
NMI
Time-out
WDT
Time-out
DMT
Time-out
Voltage Regulator Enabled
Power-up
Timer
POR
SYSRST
VDD
VDD Rise
Detect
Configuration
Mismatch
Reset
Software Reset
 2013-2016 Microchip Technology Inc.
Brown-out
Reset
BOR
CMR
SWR
DS60001191F-page 107
Reset Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 6-1:
1240
RCON
1250
1260
1270
RESETS REGISTER MAP
RSWRST
RNMICON
PWRCON
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
15:0
—
—
—
—
25/9
24/8
—
—
—
—
—
—
—
—
—
—
—
—
0000
CMR
—
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
BOR
POR
31:16
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
SWRST
31:16
—
—
—
—
0000
—
—
DMTO
WDTO
SWNMI
—
—
—
—
—
CF
WDTS
15:0
—
—
—
0000
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
VREGS
0000
BCFGERR BCFGFAIL
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
NMICNT<7:0>
0000
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 108
6.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 6-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
RCON: RESET CONTROL REGISTER
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
RW-0, HS
R/W-0, HS
U-0
—
—
—
—
BCFGERR
BCFGFAIL
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
U-0
—
—
—
—
—
—
CMR
—
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
R/W-1, HS
(1)
R/W-1, HS
(1)
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
BOR
POR
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27
BCFGERR: Primary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary configuration registers
0 = No error occurred during a read of the primary configuration registers
bit 26
BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary and alternate configuration registers
0 = No error occurred during a read of the primary and alternate configuration registers
bit 25-10 Unimplemented: Read as ‘0’
bit 9
CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8
Unimplemented: Read as ‘0’
bit 7
EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5
DMTO: Deadman Timer Time-out Flag bit
1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3
SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2
IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1
BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1:
User software must clear this bit to view the next detection.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 109
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 6-2:
Bit
Range
31:24
23:16
15:8
7:0
RSWRST: SOFTWARE RESET REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
W-0, HC
—
—
—
—
—
—
—
SWRST(1,2)
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-1
Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1,2)
1 = Enable software Reset event
0 = No effect
Note 1:
The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for
details.
Once this bit is set, any read of the RSWRST register will cause a reset to occur.
2:
DS60001191F-page 110
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 6-3:
Bit
Range
31:24
23:16
15:8
7:0
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
DMTO
WDTO
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
SWNMI
—
—
—
—
—
CF
WDTS
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NMICNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
DMTO: Deadman Timer Time-out Flag bit
1 = DMT time-out has occurred and caused a NMI
0 = DMT time-out has not occurred
Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.
bit 24
WDTO: Watchdog Timer Time-Out Flag bit
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.
bit 23
SWNMI: Software NMI Trigger.
1 = An NMI will be generated
0 = An NMI will not be generated
bit 22-18 Unimplemented: Read as ‘0’
bit 17
CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
bit 16
bit 15-8
bit 7-0
Setting this bit will cause a a CF NMI event, but will not cause a clock switch to the BFRC.
WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
Unimplemented: Read as ‘0’
NMICNT<7:0>: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI reset counter.
11111111-00000001 = Number of SYSCLK cycles before a device Reset occurs(1)
00000000 = No delay between NMI assertion and device Reset event
Note 1:
When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered
the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset
counter is only applicable to these two specific NMI events.
Note:
The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 111
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 6-4:
Bit
Range
31:24
23:16
15:8
7:0
PWRCON: POWER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
VREGS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
VREGS: Voltage Regulator Stand-by Enable bit
1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep
DS60001191F-page 112
x = Bit is unknown
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
7.0
Note:
CPU EXCEPTIONS AND
INTERRUPT CONTROLLER
The CPU handles interrupt events as part of the exception handling mechanism, which is described in
Section 7.1 “CPU Exceptions”.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 8. “Interrupt Controller” (DS60001108) and Section 50.
“CPU for Devices with MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192), which are available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MZ EC devices generate interrupt requests in
response to interrupt events from peripheral modules.
The Interrupt Controller module exists outside of the
CPU and prioritizes the interrupt events before
presenting them to the CPU.
• Up to 190 interrupt sources and vectors with
dedicated programmable offsets, eliminating the
need for redirection
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
• Seven shadow register sets that can be used for any
priority level, eliminating software context switch and
reducing interrupt latency
• Software can generate any interrupt
Figure 7-1 shows the block diagram for the Interrupt
Controller and CPU exceptions.
CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Interrupt Requests
FIGURE 7-1:
The Interrupt Controller module includes the following
features:
Vector Number and Offset
Interrupt Controller
Priority Level
CPU Core
(Exception Handling)
Shadow Set Number
SYSCLK
 2013-2016 Microchip Technology Inc.
DS60001191F-page 113
CPU Exceptions
CPU coprocessor 0 contains the logic for identifying and managing exceptions.
Exceptions can be caused by a variety of sources, including boundary cases in
data, external events or program errors. Table 7-1 lists the exception types in
order of priority.
TABLE 7-1:
Exception Type
(In Order of
Priority)
MIPS32® microAptiv™ MICROPROCESSOR CORE EXCEPTION TYPES
Description
Branches to
Status
Bits Set
Debug Bits
Set
EXCCODE
XC32 Function Name
Highest Priority
Reset
Assertion MCLR or a Power-on Reset (POR).
0xBFC0_0000
BEV, ERL
—
—
_on_reset
Soft Reset
Assertion of a software Reset.
0xBFC0_0000
—
—
_on_reset
DSS
DINT
0xBFC0_0480
0xBFC0_0480
DSS
DINT
—
—
NMI
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of
the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
BEV, SR,
ERL
—
—
—
—
Machine Check
TLB write that conflicts with an existing entry.
EBASE+0x180
—
0x18
_general_exception_handler
Interrupt
Assertion of unmasked hardware or software inter- See Table 7-2.
rupt signal.
Deferred watch (unmasked by K|DM=>!(K|DM)
EBASE+0x180
transition).
EJTAG debug hardware instruction break matched.
0xBFC0_0480
A reference to an address that is in one of the
EBASE+0x180
Watch registers (fetch).
Fetch address alignment error. Fetch reference to
EBASE+0x180
protected address.
Fetch TLB miss or fetch TLB hit to page with V = 0. EBASE if Status.EXL = 0
EBASE+0x180 if
Status.EXL == 1
An instruction fetch matched a valid TLB entry that
EBASE+0x180
had the XI bit set.
Instruction fetch bus error.
EBASE+0x180
BEV, NMI,
ERL
MCHECK,
EXL
IPL<2:0>
—
0x00
See Table 7-2.
WP, EXL
—
0x17
_general_exception_handler
—
EXL
DIB
—
—
0x17
—
_general_exception_handler
EXL
—
0x04
_general_exception_handler
—
—
—
—
0x02
0x02
—
_general_exception_handler
EXL
—
0x14
_general_exception_handler
EXL
—
0x06
_general_exception_handler
Deferred Watch
 2013-2016 Microchip Technology Inc.
DIB
WATCH
AdEL
TLBL
TLBL Execute
Inhibit
IBE
0xBFC0_0000
—
—
_nmi_handler
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 114
7.1
Exception Type
(In Order of
Priority)
Instruction
Validity
Exceptions
Execute
Exception
Tr
DDBL/DDBS
WATCH
AdEL
AdES
TLBL
TLBS
DBE
DDBL
CBrk
MIPS32® microAptiv™ MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED)
Description
Branches to
Status
Bits Set
Debug Bits
Set
An instruction could not be completed because it
was not allowed to access the required resources
(Coprocessor Unusable) or was illegal (Reserved
Instruction). If both exceptions occur on the same
instruction, the Coprocessor Unusable Exception
takes priority over the Reserved Instruction
Exception.
An instruction-based exception occurred: Integer
overflow, trap, system call, breakpoint, floating
point, or DSP ASE state disabled exception.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or
EJTAG data value break on store (address +
value).
A reference to an address that is in one of the
Watch registers (data).
Load address alignment error. User mode load
reference to kernel address.
Store address alignment error. User mode store to
kernel address.
Load TLB miss or load TLB hit to page with V = 0.
Store TLB miss or store TLB hit to page with V = 0.
Load or store bus error.
EJTAG data hardware breakpoint matched in load
data compare.
EJTAG complex breakpoint.
EBASE+0x180
EXL
—
EBASE+0x180
EXL
—
EBASE+0x180
0xBFC0_0480
EXL
—
—
DDBL or
DDBS
0x0D
—
_general_exception_handler
—
EBASE+0x180
EXL
—
0x17
_general_exception_handler
EBASE+0x180
EXL
—
0x04
_general_exception_handler
EBASE+0x180
EXL
—
0x05
_general_exception_handler
EBASE+0x180
EBASE+0x180
EBASE+0x180
0xBFC0_0480
EXL
EXL
EXL
—
—
—
—
DDBL
0x02
0x03
0x07
—
_general_exception_handler
_general_exception_handler
_general_exception_handler
—
0xBFC0_0480
—
DIBIMPR,
DDBLIMPR,
and/or
DDBSIMPR
—
—
DS60001191F-page 115
Lowest Priority
EXCCODE
XC32 Function Name
0x0A or
0x0B
_general_exception_handler
0x08-0x0C _general_exception_handler
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-1:
For details on the Variable Offset feature, refer to 8.5.2 “Variable Offset” in
Section 8. “Interrupt Controller” (DS60001108) of the “PIC32 Family
Reference Manual”.
Interrupts
The PIC32MZ EC family uses variable offsets for vector spacing. This allows
the interrupt vector spacing to be configured according to application needs. A
unique interrupt vector offset can be set for each vector using its associated
OFFx register.
TABLE 7-2:
Table 7-2 provides the Interrupt IRQ, vector and bit location information.
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
IRQ
#
XC32 Vector Name
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
Highest Natural Order Priority
 2013-2016 Microchip Technology Inc.
Core Timer Interrupt
_CORE_TIMER_VECTOR
0
OFF000<17:1>
IFS0<0>
IEC0<0>
IPC0<4:2>
IPC0<1:0>
No
Core Software Interrupt 0
_CORE_SOFTWARE_0_VECTOR
1
OFF001<17:1>
IFS0<1>
IEC0<1>
IPC0<12:10>
IPC0<9:8>
No
Core Software Interrupt 1
_CORE_SOFTWARE_1_VECTOR
2
OFF002<17:1>
IFS0<2>
IEC0<2>
IPC0<20:18>
IPC0<17:16>
No
External Interrupt
_EXTERNAL_0_VECTOR
3
OFF003<17:1>
IFS0<3>
IEC0<3>
IPC0<28:26>
IPC0<25:24>
No
Timer1
_TIMER_1_VECTOR
4
OFF004<17:1>
IFS0<4>
IEC0<4>
IPC1<4:2>
IPC1<1:0>
No
Input Capture 1 Error
_INPUT_CAPTURE_1_ERROR_VECTOR
5
OFF005<17:1>
IFS0<5>
IEC0<5>
IPC1<12:10>
IPC1<9:8>
Yes
Input Capture 1
_INPUT_CAPTURE_1_VECTOR
6
OFF006<17:1>
IFS0<6>
IEC0<6>
IPC1<20:18>
IPC1<17:16>
Yes
Output Compare 1
_OUTPUT_COMPARE_1_VECTOR
7
OFF007<17:1>
IFS0<7>
IEC0<7>
IPC1<28:26>
IPC1<25:24>
No
External Interrupt 1
_EXTERNAL_1_VECTOR
8
OFF008<17:1>
IFS0<8>
IEC0<8>
IPC2<4:2>
IPC2<1:0>
No
Timer2
_TIMER_2_VECTOR
9
OFF009<17:1>
IFS0<9>
IEC0<9>
IPC2<12:10>
IPC2<9:8>
No
Input Capture 2 Error
_INPUT_CAPTURE_2_ERROR_VECTOR
10
OFF010<17:1> IFS0<10> IEC0<10> IPC2<20:18>
IPC2<17:16>
Yes
Input Capture 2
_INPUT_CAPTURE_2_VECTOR
11
OFF011<17:1> IFS0<11> IEC0<11> IPC2<28:26>
IPC2<25:24>
Yes
Output Compare 2
_OUTPUT_COMPARE_2_VECTOR
12
OFF012<17:1> IFS0<12> IEC0<12> IPC3<4:2>
IPC3<1:0>
No
External Interrupt 2
_EXTERNAL_2_VECTOR
13
OFF013<17:1> IFS0<13> IEC0<13> IPC3<12:10>
IPC3<9:8>
No
Timer3
_TIMER_3_VECTOR
14
OFF014<17:1> IFS0<14> IEC0<14> IPC3<20:18>
IPC3<17:16>
No
Input Capture 3 Error
_INPUT_CAPTURE_3_ERROR_VECTOR
15
OFF015<17:1> IFS0<15> IEC0<15> IPC3<28:26>
IPC3<25:24>
Yes
Input Capture 3
_INPUT_CAPTURE_3_VECTOR
16
OFF016<17:1> IFS0<16> IEC0<16> IPC4<4:2>
IPC4<1:0>
Yes
Output Compare 3
_OUTPUT_COMPARE_3_VECTOR
17
OFF017<17:1> IFS0<17> IEC0<17> IPC4<12:10>
IPC4<9:8>
No
External Interrupt 3
_EXTERNAL_3_VECTOR
18
OFF018<17:1> IFS0<18> IEC0<18> IPC4<20:18>
IPC4<17:16>
No
Timer4
_TIMER_4_VECTOR
19
OFF019<17:1> IFS0<19> IEC0<19> IPC4<28:26>
IPC4<25:24>
No
_INPUT_CAPTURE_4_ERROR_VECTOR
20
OFF020<17:1> IFS0<20> IEC0<20> IPC5<4:2>
IPC5<1:0>
Yes
Input Capture 4 Error
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 116
7.2
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
Input Capture 4
_INPUT_CAPTURE_4_VECTOR
21
OFF021<17:1> IFS0<21> IEC0<21> IPC5<12:10>
IPC5<9:8>
Yes
Output Compare 4
_OUTPUT_COMPARE_4_VECTOR
22
OFF022<17:1> IFS0<22> IEC0<22> IPC5<20:18>
IPC5<17:16>
No
External Interrupt 4
_EXTERNAL_4_VECTOR
23
OFF023<17:1> IFS0<23> IEC0<23> IPC5<28:26>
IPC5<25:24>
No
Timer5
_TIMER_5_VECTOR
24
OFF024<17:1> IFS0<24> IEC0<24> IPC6<4:2>
IPC6<1:0>
No
Input Capture 5 Error
_INPUT_CAPTURE_5_ERROR_VECTOR
25
OFF025<17:1> IFS0<25> IEC0<25> IPC6<12:10>
IPC6<9:8>
Yes
Input Capture 5
_INPUT_CAPTURE_5_VECTOR
26
OFF026<17:1> IFS0<26> IEC0<26> IPC6<20:18>
IPC6<17:16>
Yes
Output Compare 5
_OUTPUT_COMPARE_5_VECTOR
27
OFF027<17:1> IFS0<27> IEC0<27> IPC6<28:26>
IPC6<25:24>
No
Timer6
_TIMER_6_VECTOR
28
OFF028<17:1> IFS0<28> IEC0<28> IPC7<4:2>
IPC7<1:0>
No
Input Capture 6 Error
_INPUT_CAPTURE_6_ERROR_VECTOR
29
OFF029<17:1> IFS0<29> IEC0<29> IPC7<12:10>
IPC7<9:8>
Yes
Input Capture 6
_INPUT_CAPTURE_6_VECTOR
30
OFF030<17:1> IFS0<30> IEC0<30> IPC7<20:18>
IPC7<17:16>
Yes
Output Compare 6
_OUTPUT_COMPARE_6_VECTOR
31
OFF031<17:1> IFS0<31> IEC0<31> IPC7<28:26>
IPC7<25:24>
No
Timer7
_TIMER_7_VECTOR
32
OFF032<17:1>
IFS1<0>
IEC1<0>
IPC8<4:2>
IPC8<1:0>
No
Input Capture 7 Error
_INPUT_CAPTURE_7_ERROR_VECTOR
33
OFF033<17:1>
IFS1<1>
IEC1<1>
IPC8<12:10>
IPC8<9:8>
Yes
Input Capture 7
_INPUT_CAPTURE_7_VECTOR
34
OFF034<17:1>
IFS1<2>
IEC1<2>
IPC8<20:18>
IPC8<17:16>
Yes
Output Compare 7
_OUTPUT_COMPARE_7_VECTOR
35
OFF035<17:1>
IFS1<3>
IEC1<3>
IPC8<28:26>
IPC8<25:24>
No
Timer8
_TIMER_8_VECTOR
36
OFF036<17:1>
IFS1<4>
IEC1<4>
IPC9<4:2>
IPC9<1:0>
No
Input Capture 8 Error
_INPUT_CAPTURE_8_ERROR_VECTOR
37
OFF037<17:1>
IFS1<5>
IEC1<5>
IPC9<12:10>
IPC9<9:8>
Yes
Input Capture 8
_INPUT_CAPTURE_8_VECTOR
38
OFF038<17:1>
IFS1<6>
IEC1<6>
IPC9<20:18>
IPC9<17:16>
Yes
Output Compare 8
_OUTPUT_COMPARE_8_VECTOR
39
OFF039<17:1>
IFS1<7>
IEC1<7>
IPC9<28:26>
IPC9<25:24>
No
Timer9
_TIMER_9_VECTOR
40
OFF040<17:1>
IFS1<8>
IEC1<8>
IPC10<4:2>
IPC10<1:0>
No
Input Capture 9 Error
_INPUT_CAPTURE_9_ERROR_VECTOR
41
OFF041<17:1>
IFS1<9>
IEC1<9>
IPC10<12:10> IPC10<9:8>
Yes
Input Capture 9
_INPUT_CAPTURE_9_VECTOR
42
OFF042<17:1> IFS1<10> IEC1<10> IPC10<20:18> IPC10<17:16>
Output Compare 9
_OUTPUT_COMPARE_9_VECTOR
43
OFF043<17:1> IFS1<11> IEC1<11> IPC10<28:26> IPC10<25:24>
No
ADC1 Global Interrupt
_ADC1_VECTOR
44
OFF044<17:1> IFS1<12> IEC1<12> IPC11<4:2>
Yes
DS60001191F-page 117
Reserved
—
45
—
—
—
IPC11<1:0>
—
Yes
—
—
ADC1 Digital Comparator 1
_ADC1_DC1_VECTOR
46
OFF046<17:1> IFS1<14> IEC1<14> IPC11<20:18>
IPC11<17:16>
Yes
ADC1 Digital Comparator 2
_ADC1_DC2_VECTOR
47
OFF047<17:1> IFS1<15> IEC1<15> IPC11<28:26>
IPC11<25:24>
Yes
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
ADC1 Digital Comparator 3
_ADC1_DC3_VECTOR
48
OFF048<17:1> IFS1<16> IEC1<16> IPC12<4:2>
IPC12<1:0>
Yes
ADC1 Digital Comparator 4
_ADC1_DC4_VECTOR
49
OFF049<17:1> IFS1<17> IEC1<17> IPC12<12:10> IPC12<9:8>
Yes
ADC1 Digital Comparator 5
_ADC1_DC5_VECTOR
50
OFF050<17:1> IFS1<18> IEC1<18> IPC12<20:18> IPC12<17:16>
Yes
ADC1 Digital Comparator 6
_ADC1_DC6_VECTOR
51
OFF051<17:1> IFS1<19> IEC1<19> IPC12<28:26> IPC12<25:24>
Yes
ADC1 Digital Filter 1
_ADC1_DF1_VECTOR
52
OFF052<17:1> IFS1<20> IEC1<20> IPC13<4:2>
IPC13<1:0>
Yes
ADC1 Digital Filter 2
_ADC1_DF2_VECTOR
53
OFF053<17:1> IFS1<21> IEC1<21> IPC13<12:10> IPC13<9:8>
Yes
ADC1 Digital Filter 3
_ADC1_DF3_VECTOR
54
OFF054<17:1> IFS1<22> IEC1<22> IPC13<20:18> IPC13<17:16>
Yes
ADC1 Digital Filter 4
_ADC1_DF4_VECTOR
55
OFF055<17:1> IFS1<23> IEC1<23> IPC13<28:26> IPC13<25:24>
Yes
ADC1 Digital Filter 5
_ADC1_DF5_VECTOR
56
OFF056<17:1> IFS1<24> IEC1<24> IPC14<4:2>
IPC14<1:0>
Yes
ADC1 Digital Filter 6
_ADC1_DF6_VECTOR
57
OFF057<17:1> IFS1<25> IEC1<25> IPC14<12:10> IPC14<9:8>
Yes
—
58
Reserved
—
—
—
—
—
—
 2013-2016 Microchip Technology Inc.
ADC1 Data 0
_ADC1_DATA0_VECTOR
59
OFF059<17:1> IFS1<27> IEC1<27> IPC14<28:26> IPC14<25:24>
Yes
ADC1 Data 1
_ADC1_DATA1_VECTOR
60
OFF060<17:1> IFS1<28> IEC1<28> IPC15<4:2>
IPC15<1:0>
Yes
ADC1 Data 2
_ADC1_DATA2_VECTOR
61
OFF061<17:1> IFS1<29> IEC1<29> IPC15<12:10> IPC15<9:8>
Yes
ADC1 Data 3
_ADC1_DATA3_VECTOR
62
OFF062<17:1> IFS1<30> IEC1<30> IPC15<20:18> IPC15<17:16>
Yes
ADC1 Data 4
_ADC1_DATA4_VECTOR
63
OFF063<17:1> IFS1<31> IEC1<31> IPC15<28:26> IPC15<25:24>
Yes
ADC1 Data 5
_ADC1_DATA5_VECTOR
64
OFF064<17:1>
IFS2<0>
IEC2<0>
IPC16<4:2>
IPC16<1:0>
Yes
ADC1 Data 6
_ADC1_DATA6_VECTOR
65
OFF065<17:1>
IFS2<1>
IEC2<1>
IPC16<12:10> IPC16<9:8>
Yes
ADC1 Data 7
_ADC1_DATA7_VECTOR
66
OFF066<17:1>
IFS2<2>
IEC2<2>
IPC16<20:18> IPC16<17:16>
Yes
ADC1 Data 8
_ADC1_DATA8_VECTOR
67
OFF067<17:1>
IFS2<3>
IEC2<3>
IPC16<28:26> IPC16<25:24>
Yes
ADC1 Data 9
_ADC1_DATA9_VECTOR
68
OFF068<17:1>
IFS2<4>
IEC2<4>
IPC17<4:2>
IPC17<1:0>
Yes
ADC1 Data 10
_ADC1_DATA10_VECTOR
69
OFF069<17:1>
IFS2<5>
IEC2<5>
IPC17<12:10> IPC17<9:8>
Yes
ADC1 Data 11
_ADC1_DATA11_VECTOR
70
OFF070<17:1>
IFS2<6>
IEC2<6>
IPC17<20:18> IPC17<17:16>
Yes
ADC1 Data 12
_ADC1_DATA12_VECTOR
71
OFF071<17:1>
IFS2<7>
IEC2<7>
IPC17<28:26> IPC17<25:24>
Yes
ADC1 Data 13
_ADC1_DATA13_VECTOR
72
OFF072<17:1>
IFS2<8>
IEC2<8>
IPC18<4:2>
IPC18<1:0>
Yes
ADC1 Data 14
_ADC1_DATA14_VECTOR
73
OFF073<17:1>
IFS2<9>
IEC2<9>
IPC18<12:10> IPC18<9:8>
Yes
ADC1 Data 15
_ADC1_DATA15_VECTOR
74
OFF074<17:1> IFS2<10> IEC2<10> IPC18<20:18> IPC18<17:16>
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
Yes
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 118
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
ADC1 Data 16
_ADC1_DATA16_VECTOR
75
OFF075<17:1> IFS2<11> IEC2<11> IPC18<28:26> IPC18<25:24>
Yes
ADC1 Data 17
_ADC1_DATA17_VECTOR
76
OFF076<17:1> IFS2<12> IEC2<12> IPC19<4:2>
IPC19<1:0>
Yes
ADC1 Data 18
_ADC1_DATA18_VECTOR
77
OFF077<17:1> IFS2<13> IEC2<13> IPC19<12:10> IPC19<9:8>
Yes
ADC1 Data 19(2)
_ADC1_DATA19_VECTOR
78
OFF078<17:1> IFS2<14> IEC2<14> IPC19<20:18> IPC19<17:16>
Yes
20(2)
_ADC1_DATA20_VECTOR
79
OFF079<17:1> IFS2<15> IEC2<15> IPC19<28:26> IPC19<25:24>
Yes
ADC1 Data 21(2)
_ADC1_DATA21_VECTOR
80
OFF080<17:1> IFS2<16> IEC2<16> IPC20<4:2>
IPC20<1:0>
Yes
22(2)
_ADC1_DATA22_VECTOR
81
OFF081<17:1> IFS2<17> IEC2<17> IPC20<12:10> IPC20<9:8>
Yes
ADC1 Data 23(2)
_ADC1_DATA23_VECTOR
82
OFF082<17:1> IFS2<18> IEC2<18> IPC20<20:18> IPC20<17:16>
Yes
ADC1 Data 24(2)
_ADC1_DATA24_VECTOR
83
OFF083<17:1> IFS2<19> IEC2<19> IPC20<28:26> IPC20<25:24>
Yes
(2)
_ADC1_DATA25_VECTOR
84
OFF084<17:1> IFS2<20> IEC2<20> IPC21<4:2>
IPC21<1:0>
Yes
ADC1 Data 26(2)
_ADC1_DATA26_VECTOR
85
OFF085<17:1> IFS2<21> IEC2<21> IPC21<12:10> IPC21<9:8>
Yes
ADC1 Data 27(2)
_ADC1_DATA27_VECTOR
86
OFF086<17:1> IFS2<22> IEC2<22> IPC21<20:18> IPC21<17:16>
Yes
28(2)
_ADC1_DATA28_VECTOR
87
OFF087<17:1> IFS2<23> IEC2<23> IPC21<28:26> IPC21<25:24>
Yes
ADC1 Data 29(2)
_ADC1_DATA29_VECTOR
88
OFF088<17:1> IFS2<24> IEC2<24> IPC22<4:2>
IPC22<1:0>
Yes
30(2)
_ADC1_DATA30_VECTOR
89
OFF089<17:1> IFS2<25> IEC2<25> IPC22<12:10> IPC22<9:8>
Yes
ADC1 Data 31(2)
_ADC1_DATA31_VECTOR
90
OFF090<17:1> IFS2<26> IEC2<26> IPC22<20:18> IPC22<17:16>
Yes
ADC1 Data 32(2)
_ADC1_DATA32_VECTOR
91
OFF091<17:1> IFS2<27> IEC2<27> IPC22<28:26> IPC22<25:24>
Yes
(2)
_ADC1_DATA33_VECTOR
92
OFF092<17:1> IFS2<28> IEC2<28> IPC23<4:2>
IPC23<1:0>
Yes
ADC1 Data 34(2)
_ADC1_DATA34_VECTOR
93
OFF093<17:1> IFS2<29> IEC2<29> IPC23<12:10> IPC23<9:8>
Yes
ADC1 Data 35(2,3)
_ADC1_DATA35_VECTOR
94
OFF094<17:1> IFS2<30> IEC2<30> IPC23<20:18> IPC23<17:16>
Yes
36(2,3)
_ADC1_DATA36_VECTOR
95
OFF095<17:1> IFS2<31> IEC2<31> IPC23<28:26> IPC23<25:24>
Yes
ADC1 Data 37(2,3)
_ADC1_DATA37_VECTOR
96
OFF096<17:1>
IFS3<0>
IEC3<0>
IPC24<4:2>
IPC24<1:0>
Yes
38(2,3)
_ADC1_DATA38_VECTOR
97
OFF097<17:1>
IFS3<1>
IEC3<1>
IPC24<12:10> IPC24<9:8>
Yes
ADC1 Data 39(2,3)
_ADC1_DATA39_VECTOR
98
OFF098<17:1>
IFS3<2>
IEC3<2>
IPC24<20:18> IPC24<17:16>
Yes
ADC1 Data 40(2,3)
_ADC1_DATA40_VECTOR
99
OFF099<17:1>
IFS3<3>
IEC3<3>
IPC24<28:26> IPC24<25:24>
Yes
(2,3)
_ADC1_DATA41_VECTOR
100 OFF100<17:1>
IFS3<4>
IEC3<4>
IPC25<4:2>
IPC25<1:0>
Yes
ADC1 Data 42(2,3)
_ADC1_DATA42_VECTOR
101 OFF101<17:1>
IFS3<5>
IEC3<5>
IPC25<12:10> IPC25<9:8>
Yes
ADC1 Data
ADC1 Data
ADC1 Data 25
ADC1 Data
ADC1 Data
ADC1 Data 33
ADC1 Data
ADC1 Data
DS60001191F-page 119
ADC1 Data 41
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
ADC1 Data 43
_ADC1_DATA43_VECTOR
102 OFF102<17:1>
IFS3<6>
IEC3<6>
IPC25<20:18> IPC25<17:16>
Yes
ADC1 Data 44
_ADC1_DATA44_VECTOR
103 OFF103<17:1>
IFS3<7>
IEC3<7>
IPC25<28:26> IPC25<25:24>
Yes
Core Performance Counter Interrupt _CORE_PERF_COUNT_VECTOR
104 OFF104<17:1>
IFS3<8>
IEC3<8>
IPC26<4:2>
IPC26<1:0>
No
Core Fast Debug Channel Interrupt
_CORE_FAST_DEBUG_CHAN_VECTOR
105 OFF105<17:1>
IFS3<9>
IEC3<9>
IPC26<12:10> IPC26<9:8>
Yes
System Bus Protection Violation
_SYSTEM_BUS_PROTECTION_VECTOR
106 OFF106<17:1> IFS3<10> IEC3<10> IPC26<20:18> IPC26<17:16>
Yes
Crypto Engine Event
_CRYPTO_VECTOR
107 OFF107<17:1> IFS3<11> IEC3<11> IPC26<28:26> IPC26<25:24>
Yes
Reserved
—
108
—
—
—
—
—
—
SPI1 Fault
_SPI1_FAULT_VECTOR
109 OFF109<17:1> IFS3<13> IEC3<13> IPC27<12:10> IPC27<9:8>
Yes
SPI1 Receive Done
_SPI1_RX_VECTOR
110
OFF110<17:1> IFS3<14> IEC3<14> IPC27<20:18> IPC27<17:16>
Yes
SPI1 Transfer Done
_SPI1_TX_VECTOR
111
OFF111<17:1> IFS3<15> IEC3<15> IPC27<28:26> IPC27<25:24>
Yes
UART1 Fault
_UART1_FAULT_VECTOR
112
OFF112<17:1> IFS3<16> IEC3<16> IPC28<4:2>
IPC28<1:0>
Yes
UART1 Receive Done
_UART1_RX_VECTOR
113
OFF113<17:1> IFS3<17> IEC3<17> IPC28<12:10> IPC28<9:8>
Yes
UART1 Transfer Done
_UART1_TX_VECTOR
114
OFF114<17:1> IFS3<18> IEC3<18> IPC28<20:18> IPC28<17:16>
Yes
I2C1 Bus Collision Event
_I2C1_BUS_VECTOR
115
OFF115<17:1> IFS3<19> IEC3<19> IPC28<28:26> IPC28<25:24>
Yes
I2C1 Slave Event
_I2C1_SLAVE_VECTOR
116
OFF116<17:1> IFS3<20> IEC3<20> IPC29<4:2>
IPC29<1:0>
Yes
I2C1 Master Event
_I2C1_MASTER_VECTOR
117
OFF117<17:1> IFS3<21> IEC3<21> IPC29<12:10> IPC29<9:8>
Yes
PORTA Input Change
Interrupt(2)
 2013-2016 Microchip Technology Inc.
_CHANGE_NOTICE_A_VECTOR
118
OFF118<17:1> IFS3<22> IEC3<22> IPC29<20:18> IPC29<17:16>
Yes
PORTB Input Change Interrupt
_CHANGE_NOTICE_B_VECTOR
119
OFF119<17:1> IFS3<23> IEC3<23> IPC29<28:26> IPC29<25:24>
Yes
PORTC Input Change Interrupt
_CHANGE_NOTICE_C_VECTOR
120 OFF120<17:1> IFS3<24> IEC3<24> IPC30<4:2>
IPC30<1:0>
Yes
PORTD Input Change Interrupt
_CHANGE_NOTICE_D_VECTOR
121 OFF121<17:1> IFS3<25> IEC3<25> IPC30<12:10> IPC30<9:8>
Yes
PORTE Input Change Interrupt
_CHANGE_NOTICE_E_VECTOR
122 OFF122<17:1> IFS3<26> IEC3<26> IPC30<20:18> IPC30<17:16>
Yes
PORTF Input Change Interrupt
_CHANGE_NOTICE_F_VECTOR
123 OFF123<17:1> IFS3<27> IEC3<27> IPC30<28:26> IPC30<25:24>
Yes
PORTG Input Change Interrupt
_CHANGE_NOTICE_G_VECTOR
124 OFF124<17:1> IFS3<28> IEC3<28> IPC31<4:2>
IPC31<1:0>
Yes
PORTH Input Change Interrupt(2,3)
_CHANGE_NOTICE_H_VECTOR
125 OFF125<17:1> IFS3<29> IEC3<29> IPC31<12:10> IPC31<9:8>
Yes
Interrupt(2,3)
PORTJ Input Change
_CHANGE_NOTICE_J_VECTOR
126 OFF126<17:1> IFS3<30> IEC3<30> IPC31<20:18> IPC31<17:16>
Yes
PORTK Input Change Interrupt(2,3,4) _CHANGE_NOTICE_K_VECTOR
127 OFF127<17:1> IFS3<31> IEC3<31> IPC31<28:26> IPC31<25:24>
Yes
Parallel Master Port
128 OFF128<17:1>
Yes
Note 1:
2:
3:
4:
_PMP_VECTOR
IFS4<0>
IEC4<0>
IPC32<4:2>
IPC32<1:0>
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 120
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
Parallel Master Port Error
_PMP_ERROR_VECTOR
129 OFF129<17:1>
IFS4<1>
IEC4<1>
IPC32<12:10> IPC32<9:8>
Yes
Comparator 1 Interrupt
_COMPARATOR_1_VECTOR
130 OFF130<17:1>
IFS4<2>
IEC4<2>
IPC32<20:18> IPC32<17:16>
No
Comparator 2 Interrupt
_COMPARATOR_2_VECTOR
131 OFF131<17:1>
IFS4<3>
IEC4<3>
IPC32<28:26> IPC32<25:24>
No
USB General Event
_USB1_VECTOR
132 OFF132<17:1>
IFS4<4>
IEC4<4>
IPC33<4:2>
IPC33<1:0>
Yes
USB DMA Event
_USB1_DMA_VECTOR
133 OFF133<17:1>
IFS4<5>
IEC4<5>
IPC33<12:10> IPC33<9:8>
Yes
DMA Channel 0
_DMA0_VECTOR
134 OFF134<17:1>
IFS4<6>
IEC4<6>
IPC33<20:18> IPC33<17:16>
No
DMA Channel 1
_DMA1_VECTOR
135 OFF135<17:1>
IFS4<7>
IEC4<7>
IPC33<28:26> IPC33<25:24>
No
DMA Channel 2
_DMA2_VECTOR
136 OFF136<17:1>
IFS4<8>
IEC4<8>
IPC34<4:2>
IPC34<1:0>
No
DMA Channel 3
_DMA3_VECTOR
137 OFF137<17:1>
IFS4<9>
IEC4<9>
IPC34<12:10> IPC34<9:8>
No
DMA Channel 4
_DMA4_VECTOR
138 OFF138<17:1> IFS4<10> IEC4<10> IPC34<20:18> IPC34<17:16>
No
DMA Channel 5
_DMA5_VECTOR
139 OFF139<17:1> IFS4<11> IEC4<11> IPC34<28:26> IPC34<25:24>
No
DMA Channel 6
_DMA6_VECTOR
140 OFF140<17:1> IFS4<12> IEC4<12> IPC35<4:2>
No
DMA Channel 7
_DMA7_VECTOR
141 OFF141<17:1> IFS4<13> IEC4<13> IPC35<12:10> IPC35<9:8>
No
SPI2 Fault
_SPI2_FAULT_VECTOR
142 OFF142<17:1> IFS4<14> IEC4<14> IPC35<20:18> IPC35<17:16>
Yes
SPI2 Receive Done
_SPI2_RX_VECTOR
143 OFF143<17:1> IFS4<15> IEC4<15> IPC35<28:26> IPC35<25:24>
Yes
SPI2 Transfer Done
_SPI2_TX_VECTOR
144 OFF144<17:1> IFS4<16> IEC4<16> IPC36<4:2>
IPC36<1:0>
Yes
UART2 Fault
_UART2_FAULT_VECTOR
145 OFF145<17:1> IFS4<17> IEC4<17> IPC36<12:10> IPC36<9:8>
Yes
UART2 Receive Done
_UART2_RX_VECTOR
146 OFF146<17:1> IFS4<18> IEC4<18> IPC36<20:18> IPC36<17:16>
Yes
UART2 Transfer Done
_UART2_TX_VECTOR
147 OFF147<17:1> IFS4<19> IEC4<19> IPC36<28:26> IPC36<25:24>
Yes
I2C2 Bus Collision Event(2)
_I2C2_BUS_VECTOR
148 OFF148<17:1> IFS4<20> IEC4<20> IPC37<4:2>
IPC37<1:0>
Yes
I2C2 Slave
Event(2)
IPC35<1:0>
DS60001191F-page 121
_I2C2_SLAVE_VECTOR
149 OFF149<17:1> IFS4<21> IEC4<21> IPC37<12:10> IPC37<9:8>
Yes
I2C2 Master Event(2)
_I2C2_MASTER_VECTOR
150 OFF150<17:1> IFS4<22> IEC4<22> IPC37<20:18> IPC37<17:16>
Yes
Control Area Network 1
_CAN1_VECTOR
151 OFF151<17:1> IFS4<23> IEC4<23> IPC37<28:26> IPC37<25:24>
Yes
Control Area Network 2
_CAN2_VECTOR
152 OFF152<17:1> IFS4<24> IEC4<24> IPC38<4:2>
IPC38<1:0>
Yes
Ethernet Interrupt
_ETHERNET_VECTOR
153 OFF153<17:1> IFS4<25> IEC4<25> IPC38<12:10> IPC38<9:8>
Yes
SPI3 Fault
_SPI3_FAULT_VECTOR
154 OFF154<17:1> IFS4<26> IEC4<26> IPC38<20:18> IPC38<17:16>
Yes
SPI3 Receive Done
_SPI3_RX_VECTOR
155 OFF155<17:1> IFS4<27> IEC4<27> IPC38<28:26> IPC38<25:24>
Yes
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
 2013-2016 Microchip Technology Inc.
SPI3 Transfer Done
_SPI3_TX_VECTOR
156 OFF156<17:1> IFS4<28> IEC4<28> IPC39<4:2>
IPC39<1:0>
Yes
UART3 Fault
_UART3_FAULT_VECTOR
157 OFF157<17:1> IFS4<29> IEC4<29> IPC39<12:10> IPC39<9:8>
Yes
UART3 Receive Done
_UART3_RX_VECTOR
158 OFF158<17:1> IFS4<30> IEC4<30> IPC39<20:18> IPC39<17:16>
Yes
UART3 Transfer Done
_UART3_TX_VECTOR
159 OFF159<17:1> IFS4<31> IEC4<31> IPC39<28:26> IPC39<25:24>
Yes
I2C3 Bus Collision Event
_I2C3_BUS_VECTOR
160 OFF160<17:1>
IFS5<0>
IEC5<0>
IPC40<4:2>
IPC40<1:0>
Yes
I2C3 Slave Event
_I2C3_SLAVE_VECTOR
161 OFF161<17:1>
IFS5<1>
IEC5<1>
IPC40<12:10> IPC40<9:8>
Yes
I2C3 Master Event
_I2C3_MASTER_VECTOR
162 OFF162<17:1>
IFS5<2>
IEC5<2>
IPC40<20:18> IPC40<17:16>
Yes
SPI4 Fault
_SPI4_FAULT_VECTOR
163 OFF163<17:1>
IFS5<3>
IEC5<3>
IPC40<28:26> IPC40<25:24>
Yes
SPI4 Receive Done
_SPI4_RX_VECTOR
164 OFF164<17:1>
IFS5<4>
IEC5<4>
IPC41<4:2>
IPC41<1:0>
Yes
SPI4 Transfer Done
_SPI4_TX_VECTOR
165 OFF165<17:1>
IFS5<5>
IEC5<5>
IPC41<12:10> IPC41<9:8>
Yes
Real Time Clock
_RTCC_VECTOR
166 OFF166<17:1>
IFS5<6>
IEC5<6>
IPC41<20:18> IPC41<17:16>
No
Flash Control Event
_FLASH_CONTROL_VECTOR
167 OFF167<17:1>
IFS5<7>
IEC5<7>
IPC41<28:26> IPC41<25:24>
No
Prefetch Module SEC Event
_PREFETCH_VECTOR
168 OFF168<17:1>
IFS5<8>
IEC5<8>
IPC42<4:2>
IPC42<1:0>
Yes
SQI1 Event
_SQI1_VECTOR
169 OFF169<17:1>
IFS5<9>
IEC5<9>
IPC42<12:10> IPC42<9:8>
Yes
UART4 Fault
_UART4_FAULT_VECTOR
170 OFF170<17:1> IFS5<10> IEC5<10> IPC42<20:18> IPC42<17:16>
Yes
UART4 Receive Done
_UART4_RX_VECTOR
171 OFF171<17:1> IFS5<11> IEC5<11> IPC42<28:26> IPC42<25:24>
Yes
UART4 Transfer Done
_UART4_TX_VECTOR
172 OFF172<17:1> IFS5<12> IEC5<12> IPC43<4:2>
IPC43<1:0>
Yes
I2C4 Bus Collision Event
_I2C4_BUS_VECTOR
173 OFF173<17:1> IFS5<13> IEC5<13> IPC43<12:10> IPC43<9:8>
Yes
I2C4 Slave Event
_I2C4_SLAVE_VECTOR
174 OFF174<17:1> IFS5<14> IEC5<14> IPC43<20:18> IPC43<17:16>
Yes
I2C4 Master Event
_I2C4_MASTER_VECTOR
175 OFF175<17:1> IFS5<15> IEC5<15> IPC43<28:26> IPC43<25:24>
Yes
SPI5 Fault(2)
_SPI5_FAULT_VECTOR
176 OFF176<17:1> IFS5<16> IEC5<16> IPC44<4:2>
IPC44<1:0>
Yes
(2)
_SPI5_RX_VECTOR
177 OFF177<17:1> IFS5<17> IEC5<17> IPC44<12:10> IPC44<9:8>
Yes
SPI5 Transfer Done(2)
_SPI5_TX_VECTOR
178 OFF178<17:1> IFS5<18> IEC5<18> IPC44<20:18> IPC44<17:16>
Yes
UART5 Fault
_UART5_FAULT_VECTOR
179 OFF179<17:1> IFS5<19> IEC5<19> IPC44<28:26> IPC44<25:24>
Yes
UART5 Receive Done
_UART5_RX_VECTOR
180 OFF180<17:1> IFS5<20> IEC5<20> IPC45<4:2>
IPC45<1:0>
Yes
UART5 Transfer Done
_UART5_TX_VECTOR
181 OFF181<17:1> IFS5<21> IEC5<21> IPC45<12:10> IPC45<9:8>
Yes
I2C5 Bus Collision Event
_I2C5_BUS_VECTOR
182 OFF182<17:1> IFS5<22> IEC5<22> IPC45<20:18> IPC45<17:16>
Yes
SPI5 Receive Done
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 122
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
I2C5 Slave Event
_I2C5_SLAVE_VECTOR
183 OFF183<17:1> IFS5<23> IEC5<23> IPC45<28:26> IPC45<25:24>
Yes
I2C5 Master Event
_I2C5_MASTER_VECTOR
184 OFF184<17:1> IFS5<24> IEC5<24> IPC46<4:2>
IPC46<1:0>
Yes
SPI6 Fault(2)
_SPI6_FAULT_VECTOR
185 OFF185<17:1> IFS5<25> IEC5<25> IPC46<12:10> IPC46<9:8>
Yes
SPI6 Receive Done(2)
_SPI6_RX_VECTOR
186 OFF186<17:1> IFS5<26> IEC5<26> IPC46<20:18> IPC46<17:16>
Yes
Done(2)
SPI6 Transfer
_SPI6_TX_VECTOR
187 OFF187<17:1> IFS5<27> IEC5<27> IPC46<28:26> IPC46<25:24>
Yes
UART6 Fault
_UART6_FAULT_VECTOR
188 OFF188<17:1> IFS5<28> IEC5<28> IPC47<4:2>
IPC47<1:0>
Yes
UART6 Receive Done
_UART6_RX_VECTOR
189 OFF189<17:1> IFS5<29> IEC5<29> IPC47<12:10> IPC47<9:8>
Yes
UART6 Transfer Done
_UART6_TX_VECTOR
190 OFF190<17:1> IFS5<30> IEC5<30> IPC47<20:18> IPC47<17:16>
Yes
Lowest Natural Order Priority
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EC Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
DS60001191F-page 123
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-2:
Interrupt Control Registers
Virtual Address
(BF81_#)
Register
Name(1)
TABLE 7-3:
0000
INTCON
0010
0020
0030
0040
0050
0060
PRISS
INTSTAT
IPTMR
IFS0
IFS1
IFS2
(5)
IFS3(6)
0080
IFS4
00C0
 2013-2016 Microchip Technology Inc.
00D0
IFS5
IEC0
IEC1
00E0
IEC2(5)
00F0
IEC3(6)
Legend:
Note
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
TPC<2:0>
31:16
PRI7SS<3:0>
PRI6SS<3:0>
PRI5SS<3:0>
15:0
PRI3SS<3:0>
PRI2SS<3:0>
PRI1SS<3:0>
31:16
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
SRIPL<2:0>
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
0070
0090
INTERRUPT REGISTER MAP
PRI4SS<3:0>
—
0000
—
—
—
SS0
0000
—
—
—
—
0000
SIRQ<7:0>
31:16
0000
0000
IPTMR<31:0>
15:0
0000
31:16
OC6IF
IC6IF
IC6EIF
T6IF
OC5IF
IC5IF
IC5EIF
T5IF
INT4IF
OC4IF
IC4IF
IC4EIF
T4IF
INT3IF
OC3IF
IC3IF
0000
15:0
IC3EIF
T3IF
INT2IF
OC2IF
IC2IF
IC2EIF
T2IF
INT1IF
OC1IF
IC1IF
IC1EIF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
AD1D3IF
AD1D2IF
AD1D1IF
AD1D0IF
—
AD1DF6IF
AD1DF5IF
AD1DF4IF
AD1DF3IF
AD1DF2IF
—
AD1IF
31:16 AD1D4IF
15:0 AD1DC2IF AD1DC1IF
AD1DF1IF AD1DC6IF AD1DC5IF AD1DC4IF AD1DC3IF 0000
OC9IF
IC9IF
IC9EIF
T9IF
OC8IF
IC8IF
IC8EIF
31:16 AD1D36IF AD1D35IF AD1D34IF AD1D33IF
AD1D32IF
AD1D31IF
AD1D30IF
AD1D29IF
AD1D28IF
AD1D27IF
AD1D26IF
AD1D25IF AD1D24IF AD1D23IF
AD1D22IF AD1D21IF 0000
15:0 AD1D20IF AD1D19IF AD1D18IF AD1D17IF
31:16
CNKIF
CNJIF
15:0 SPI1TXIF SPI1RXIF
T8IF
OC7IF
IC7IF
IC7EIF
AD1D16IF
AD1D15IF
AD1D14IF
AD1D13IF
AD1D12IF
AD1D11IF
AD1D10IF
AD1D9IF
AD1D8IF
AD1D7IF
AD1D6IF
CNHIF
CNGIF
CNFIF
CNEIF
CNDIF
CNCIF
CNBIF
CNAIF
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
SPI1EIF
—
CRPTIF
SBIF
CFDCIF
CPCIF
AD1D44IF
AD1D43IF
AD1D42IF
AD1D41IF AD1D40IF AD1D39IF
U3RXIF
U3EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
ETHIF
CAN2IF(3)
CAN1IF(3)
I2C2MIF(2)
I2C2SIF(2)
I2C2BIF(2)
U2TXIF
U2RXIF
U2EIF
SPI2EIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
USBDMAIF
USBIF
CMP2IF
CMP1IF
PMPEIF
31:16
—
U6TXIF
U6RXIF
U6EIF
SPI6TX(2)
SPI6RXIF(2)
SPI6IF(2)
I2C5MIF
I2C5SIF
I2C5BIF
U5TXIF
U5RXIF
U5EIF
U3TXIF
0000
AD1D5IF 0000
U1EIF
0000
AD1D38IF AD1D37IF 0000
15:0 SPI2RXIF
31:16
T7IF
SPI2TXIF 0000
PMPIF
0000
SPI5TXIF(2) SPI5RXIF(2) SPI5EIF(2) 0000
15:0
I2C4MIF
I2C4SIF
I2C4BIF
U4TXIF
U4RXIF
U4EIF
SQI1IF
PREIF
FCEIF
RTCCIF
SPI4TXIF
SPI4RXIF
SPI4EIF
I2C3MIF
I2C3SIF
I2C3BIF
0000
31:16
OC6IE
IC6IE
IC6EIE
T6IE
OC5IE
IC5IE
IC5EIE
T5IE
INT4IE
OC4IE
IC4IE
IC4EIE
T4IE
INT3IE
OC3IE
IC3IE
0000
15:0
IC3EIE
T3IE
INT2IE
OC2IE
IC2IE
IC2EIE
T2IE
INT1IE
OC1IE
IC1IE
IC1EIE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
AD1D3IE
AD1D2IE
AD1D1IE
AD1D0IE
—
AD1DF6IE
AD1DF5IE
AD1DF4IE
AD1DF3IE
AD1DF2IE
—
AD1IE
31:16 AD1D4IE
15:0 AD1DC2IE AD1DC1IE
AD1DF1IE AD1DC6IE AD1DC5IE AD1DC4IE AD1DC3IE 0000
OC9IE
IC9IE
IC9EIE
T9IE
OC8IE
IC8IE
IC8EIE
31:16 AD1D36IE AD1D35IE AD1D34IE AD1D33IE
AD1D32IE
AD1D31IE
AD1D30IE
AD1D29IE
AD1D28IE
AD1D27IE
AD1D26IE
AD1D25IE AD1D24IE AD1D23IE
AD1D22IE AD1D21IE 0000
15:0 AD1D20IE AD1D19IE AD1D18IE AD1D17IE
31:16
CNKIE
CNJIE
15:0 SPI1TXIE SPI1RXIE
T8IE
OC7IE
IC7IE
IC7EIE
AD1D16IE
AD1D15IE
AD1D14IE
AD1D13IE
AD1D12IE
AD1D11IE
AD1D10IE
AD1D9IE
AD1D8IE
AD1D7IE
AD1D6IE
CNHIE
CNGIE
CNFIE
CNEIE
CNDIE
CNCIE
CNBIE
CNAIE
I2C1MIE
I2C1SIE
I2C1BIE
U1TXIE
U1RXIE
SPI1EIE
—
CRPTIE
SBIE
CFDCIE
CPCIE
AD1D44IE
AD1D43IE
AD1D42IE
AD1D41IE AD1D40IE AD1D39IE
T7IE
0000
AD1D5IE 0000
U1EIE
0000
AD1D38IE AD1D37IE 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 124
7.3
Virtual Address
(BF81_#)
Register
Name(1)
0100
IEC4
0110
0140
0150
0160
0170
0180
0190
01A0
01B0
01C0
01D0
01E0
01F0
0200
IEC5
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC10
IPC11
IPC12
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
U3TXIE
U3RXIE
U3EIE
SPI3TXIE
SPI3RXIE
SPI3EIE
ETHIE
CAN2IE(3)
CAN1IE(3)
I2C2MIE(2)
I2C2SIE(2)
I2C2BIE(2)
U2TXIE
U2RXIE
U2EIE
15:0 SPI2RXIE
SPI2EIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
USBDMAIE
USBIE
CMP2IE
CMP1IE
PMPEIE
31:16
—
U6TXIE
U6RXIE
U6EIE
SPI6IE(2)
I2C5MIE
I2C5SIE
I2C5BIE
U5TXIE
U5RXIE
U5EIE
U4TXIE
SQI1IE
PREIE
SPI4RXIE
31:16
SPI6TXIE(2) SPI6RXIE(2)
17/1
16/0
SPI2TXIE 0000
PMPIE
0000
SPI5TXIE(2) SPI5RXIE(2) SPI5EIE(2) 0000
DS60001191F-page 125
15:0
I2C4MIE
I2C4SIE
I2C4BIE
FCEIE
RTCCIE
SPI4TXIE
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
OC1IP<2:0>
OC1IS<1:0>
—
—
—
IC1IP<2:0>
IC1IS<1:0>
0000
15:0
—
—
—
IC1EIP<2:0>
IC1EIS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
IC2EIP<2:0>
IC2EIS<1:0>
0000
15:0
—
—
—
T2IP<2:0>
T2IS<1:0>
—
—
—
INT1IP<2:0>
INT1IS<1:0>
0000
31:16
—
—
—
IC3EIP<2:0>
IC3EIS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
15:0
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
31:16
—
—
—
T4IP<2:0>
T4IS<1:0>
—
—
—
INT3IP<2:0>
INT3IS<1:0>
0000
15:0
—
—
—
OC3IP<2:0>
OC3IS<1:0>
—
—
—
IC3IP<2:0>
IC3IS<1:0>
0000
31:16
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
15:0
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
IC4EIP<2:0>
IC4EIS<1:0>
0000
31:16
—
—
—
OC5IP<2:0>
OC5IS<1:0>
—
—
—
IC5IP<2:0>
IC5IS<1:0>
0000
15:0
—
—
—
IC5EIP<2:0>
IC5EIS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
OC6IP<2:0>
OC6IS<1:0>
—
—
—
IC6IP<2:0>
IC6IS<1:0>
0000
15:0
—
—
—
IC6EIP<2:0>
IC6EIS<1:0>
—
—
—
T6IP<2:0>
T6IS<1:0>
0000
31:16
—
—
—
OC7IP<2:0>
OC7IS<1:0>
—
—
—
IC7IP<2:0>
IC7IS<1:0>
0000
15:0
—
—
—
IC7EIP<2:0>
IC7EIS<1:0>
—
—
—
T7IP<2:0>
T7IS<1:0>
0000
31:16
—
—
—
OC8IP<2:0>
OC8IS<1:0>
—
—
—
IC8IP<2:0>
IC8IS<1:0>
0000
15:0
—
—
—
IC8EIP<2:0>
IC8EIS<1:0>
—
—
—
T8IP<2:0>
T8IS<1:0>
0000
31:16
—
—
—
OC9IP<2:0>
OC9IS<1:0>
—
—
—
IC9IP<2:0>
IC9IS<1:0>
0000
15:0
—
—
—
IC9EIP<2:0>
IC9EIS<1:0>
—
—
—
T9IP<2:0>
T9IS<1:0>
0000
31:16
—
—
—
AD1DC2IP<2:0>
AD1DC2IS<1:0>
—
—
—
AD1DC1IP<2:0>
AD1DC1IS<1:0>
0000
15:0
—
—
—
—
—
—
—
AD1IP<2:0>
AD1IS<1:0>
0000
31:16
—
—
—
AD1DC6IP<2:0>
AD1DC6IS<1:0>
—
—
—
AD1DC5IP<2:0>
AD1DC5IS<1:0>
0000
15:0
—
—
—
AD1DC4IP<2:0>
AD1DC4IS<1:0>
—
—
—
AD1DC3IP<2:0>
AD1DC3IS<1:0>
0000
—
U4EIE
18/2
31:16
—
U4RXIE
19/3
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
—
—
SPI4EIE
I2C3MIE
I2C3SIE
I2C3BIE
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0210
IPC13
0220
0230
0240
0250
0260
0270
0280
0290
02A0
02B0
02C0
 2013-2016 Microchip Technology Inc.
02D0
02E0
02F0
IPC14
IPC15
IPC16
IPC17
IPC18
IPC19
IPC20
IPC21
IPC22
IPC23
IPC24
IPC25
IPC26
IPC27
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
AD1DF4IP<2:0>
15:0
—
—
—
AD1DF2IP<2:0>
31:16
—
—
—
15:0
—
—
31:16
—
15:0
26/10
25/9
24/8
20/4
23/7
22/6
21/5
AD1DF4IS<1:0>
—
—
—
AD1DF3IP<2:0>
AD1DF3IS<1:0>
0000
AD1DF2IS<1:0>
—
—
—
AD1DF1IP<2:0>
AD1DF1IS<1:0>
0000
AD1D0IP<2:0>
AD1D0IS<1:0>
—
—
—
—
AD1DF6IP<2:0>
AD1DF6IS<1:0>
—
—
—
—
—
AD1D4IP<2:0>
AD1D4IS<1:0>
—
—
—
—
—
AD1D2IP<2:0>
AD1D2IS<1:0>
—
31:16
—
—
—
AD1D8IP<2:0>
AD1D8IS<1:0>
15:0
—
—
—
AD1D6IP<2:0>
31:16
—
—
—
15:0
—
—
31:16
—
15:0
—
19/3
16/0
0000
AD1DF5IP<2:0>
AD1DF5IS<1:0>
0000
—
AD1D3IP<2:0>
AD1D3IS<1:0>
0000
—
—
AD1D1IP<2:0>
AD1D1IS<1:0>
0000
—
—
—
AD1D7IP<2:0>
AD1D7IS<1:0>
0000
AD1D6IS<1:0>
—
—
—
AD1D5IP<2:0>
AD1D5IS<1:0>
0000
AD1D12IP<2:0>
AD1D12IS<1:0>
—
—
—
AD1D11IP<2:0>
AD1D11IS<1:0>
0000
—
AD1D10IP<2:0>
AD1D10IS<1:0>
—
—
—
AD1D9IP<2:0>
AD1D9IS<1:0>
0000
—
—
AD1D16IP<2:0>
AD1D16IS<1:0>
—
—
—
AD1D15IP<2:0>
AD1D15IS<1:0>
0000
—
—
—
AD1D14IP<2:0>
AD1D14IS<1:0>
—
—
—
AD1D13IP<2:0>
AD1D13IS<1:0>
0000
31:16
—
—
—
AD1D20IP<2:0>(2)
AD1D20IS<1:0>(2)
—
—
—
AD1D19IP<2:0>(2)
AD1D19IS<1:0>(2)
0000
15:0
—
—
—
AD1D18IP<2:0>
AD1D18IS<1:0>
—
—
—
AD1D17IP<2:0>
AD1D17IS<1:0>
0000
31:16
—
—
—
AD1D24IP<2:0>(2)
AD1D24IS<1:0>(2)
—
—
—
AD1D23IP<2:0>(2)
AD1D23IS<1:0>(2)
0000
15:0
—
—
—
AD1D22IP<2:0>(2)
AD1D22IS<1:0>(2)
—
—
—
AD1D21IP<2:0>(2)
AD1D21IS<1:0>(2)
0000
31:16
—
—
—
AD1D28IP<2:0>(2)
AD1D28IS<1:0>(2)
—
—
—
AD1D27IP<2:0>(2)
AD1D27IS<1:0>(2)
0000
15:0
—
—
—
AD1D26IP<2:0>(2)
AD1D26IS<1:0>(2)
—
—
—
AD1D25IP<2:0>(2)
AD1D25IS<1:0>(2)
0000
31:16
—
—
—
AD1D32IP<2:0>(2)
AD1D32IS<1:0>(2)
—
—
—
AD1D31IP<2:0>(2)
AD1D31IS<1:0>(2)
0000
15:0
—
—
—
AD1D30IP<2:0>(2)
AD1D30IS<1:0>(2)
—
—
—
AD1D29IP<2:0>(2)
AD1D29IS<1:0>(2)
0000
31:16
—
—
—
AD1D36IP<2:0>(2,4)
AD1D36IS<1:0>(2,4)
—
—
—
AD1D35IP<2:0>(2,4)
AD1D35IS<1:0>(2,4)
0000
15:0
—
—
—
AD1D34IP<2:0>(2)
AD1D34IS<1:0>(2)
—
—
—
AD1D33IP<2:0>(2)
AD1D33IS<1:0>(2)
0000
31:16
—
—
—
AD1D40IP<2:0>(2,4)
AD1D40IS<1:0>(2,4)
—
—
—
AD1D39IP<2:0>(2,4)
AD1D39IS<1:0>(2,4)
0000
15:0
—
—
—
AD1D38IP<2:0>(2,4)
AD1D38IS<1:0>(2,4)
—
—
—
AD1D37IP<2:0>(2,4)
AD1D37IS<1:0>(2,4)
0000
31:16
—
—
—
AD1D44IP<2:0>
AD1D44IS<1:0>
—
—
—
AD1D43IP<2:0>
AD1D43IS<1:0>
0000
15:0
—
—
—
AD1D42IP<2:0>(2,4)
AD1D42IS<1:0>(2,4)
—
—
—
AD1D41IP<2:0>(2,4)
AD1D41IS<1:0>(2,4)
0000
31:16
—
—
—
CRPTIP<2:0>(7)
CRPTIS<1:0>(7)
—
—
—
SBIP<2:0>
SBIS<1:0>
0000
15:0
—
—
—
CFDCIP<2:0>
CFDCIS<1:0>
—
—
—
CPCIP<2:0>
CPCIS<1:0>
0000
31:16
—
—
—
SPI1TXIP<2:0>
SPI1TXIS<1:0>
—
—
—
SPI1RXIP<2:0>
SPI1RXIS<1:0>
0000
15:0
—
—
—
SPI1EIP<2:0>
SPI1EIS<1:0>
—
—
—
—
—
17/1
—
—
—
18/2
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
—
—
—
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 126
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0300
IPC28
0310
0320
0330
0340
0350
0360
0370
0380
0390
03A0
03B0
03C0
03D0
03E0
IPC29
IPC30
IPC31
IPC32
IPC33
IPC34
IPC35
IPC36
IPC37
IPC38
IPC39
IPC40
IPC41
IPC42
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
I2C1BIP<2:0>
15:0
—
—
—
U1RXIP<2:0>
31:16
—
—
—
15:0
—
—
31:16
—
15:0
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
DS60001191F-page 127
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
23/7
22/6
21/5
I2C1BIS<1:0>
—
—
—
U1TXIP<2:0>
U1TXIS<1:0>
0000
U1RXIS<1:0>
—
—
—
U1EIP<2:0>
U1EIS<1:0>
0000
CNBIP<2:0>
CNBIS<1:0>
—
—
—
CNAIP<2:0>(2)
CNAIS<1:0>(2)
0000
—
I2C1MIP<2:0>
I2C1MIS<1:0>
—
—
—
I2C1SIP<2:0>
I2C1SIS<1:0>
0000
—
—
CNFIP<2:0>
CNFIS<1:0>
—
—
—
CNEIP<2:0>
CNEIS<1:0>
0000
—
—
—
CNDIP<2:0>
CNDIS<1:0>
—
—
—
CNCIP<2:0>
CNCIS<1:0>
0000
31:16
—
—
—
CNKIP<2:0>(2,4,8)
CNKIS<1:0>(2,4,8)
—
—
—
CNJIP<2:0>(2,4)
CNJIS<1:0>(2,4)
0000
15:0
—
—
—
CNHIP<2:0>(2,4)
CNHIS<1:0>(2,4)
—
—
—
CNGIP<2:0>
CNGIS<1:0>
0000
31:16
—
—
—
CMP2IP<2:0>
CMP2IS<1:0>
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
0000
15:0
—
—
—
PMPEIP<2:0>
PMPEIS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
15:0
—
—
—
USBDMAIP<2:0>
USBDMAIS<1:0>
—
—
—
USBIP<2:0>
USBIS<1:0>
0000
31:16
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
15:0
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
31:16
—
—
—
SPI2RXIP<2:0>
SPI2RXIS<1:0>
—
—
—
SPI2EIP<2:0>
SPI2EIS<1:0>
0000
15:0
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
31:16
—
—
—
U2TXIP<2:0>
U2TXIS<1:0>
—
—
—
U2RXIP<2:0>
U2RXIS<1:0>
0000
15:0
—
—
—
U2EIP<2:0>
U2EIS<1:0>
—
—
—
SPI2TXIP<2:0>
SPI2TXIS<1:0>
0000
31:16
—
—
—
CAN1IP<2:0>(3)
CAN1IS<1:0>(3)
—
—
—
I2C2MIP<2:0>(2)
I2C2MIS<1:0>(2)
0000
15:0
—
—
—
I2C2SIP<2:0>(2)
I2C2SIS<1:0>(2)
—
—
—
I2C2BIP<2:0>(2)
I2C2BIS<1:0>(2)
0000
31:16
—
—
—
SPI3RXIP<2:0>
SPI3RXIS<1:0>
—
—
—
SPI3EIP<2:0>
SPI3EIS<1:0>
0000
15:0
—
—
—
ETHIP<2:0>
ETHIS<1:0>
—
—
—
CAN2IP<2:0>(3)
CAN2IS<1:0>(3)
0000
31:16
—
—
—
U3TXIP<2:0>
U3TXIS<1:0>
—
—
—
U3RXIP<2:0>
U3RXIS<1:0>
0000
15:0
—
—
—
U3EIP<2:0>
U3EIS<1:0>
—
—
—
SPI3TXIP<2:0>
SPI3TXIS<1:0>
0000
31:16
—
—
—
SPI4EIP<2:0>
SPI4EIS<1:0>
—
—
—
I2C3MIP<2:0>
I2C3MIS<1:0>
0000
15:0
—
—
—
I2C3SIP<2:0>
I2C3SIS<1:0>
—
—
—
I2C3BIP<2:0>
I2C3BIS<1:0>
0000
31:16
—
—
—
FCEIP<2:0>
FCEIS<1:0>
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
0000
15:0
—
—
—
SPI4TXIP<2:0>
SPI4TXIS<1:0>
—
—
—
SPI4RXIP<2:0>
SPI4RXIS<1:0>
0000
31:16
—
—
—
U4RXIP<2:0>
U4RXIS<1:0>
—
—
—
U4EIP<2:0>
U4EIS<1:0>
0000
15:0
—
—
—
SQI1IP<2:0>
SQI1IS<1:0>
—
—
—
PREIP<2:0>
PREIS<1:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
03F0
IPC43
0400
0410
0420
0430
0540
0544
0548
054C
0550
0554
0558
 2013-2016 Microchip Technology Inc.
055C
0560
0564
IPC44
IPC45
IPC46
IPC47
OFF000
OFF001
OFF002
OFF003
OFF004
OFF005
OFF006
OFF007
OFF008
OFF009
31/15
30/14
29/13
28/12
23/7
22/6
21/5
31:16
—
—
—
I2C4MIP<2:0>
15:0
—
—
—
I2C4BIP<2:0>
I2C4MIS<1:0>
—
—
—
I2C4SIP<2:0>
I2C4SIS<1:0>
0000
I2C4BIS<1:0>
—
—
—
U4TXIP<2:0>
U4TXIS<1:0>
31:16
—
—
—
0000
U5EIP<2:0>
U5EIS<1:0>
—
—
—
SPI5TXIP<2:0>(2)
SPI5TXIS<1:0>(2)
15:0
—
—
0000
—
SPI5RXIP<2:0>(2)
SPI5RXIS<1:0>(2)
—
—
—
SPI5EIP<2:0>(2)
SPI5EIS<1:0>(2)
31:16
—
0000
—
—
I2C5SIP<2:0>
I2C5SIS<1:0>
—
—
—
I2C5BIP<2:0>
I2C5BIS<1:0>
15:0
0000
—
—
—
U5TXIP<2:0>
U5TXIS<1:0>
—
—
—
U5RXIP<2:0>
U5RXIS<1:0>
0000
31:16
—
—
—
SPI6TXIP<2:0>(2)
SPI6TXIS<1:0>(2)
—
—
—
SPI6RXIP<2:0>(2)
SPI6RXIS<1:0>(2)
0000
15:0
—
—
—
SPI6EIP<2:0>(2)
SPI6EIS<1:0>(2)
—
—
—
I2C5MIP<2:0>
I2C5MIS<1:0>
0000
31:16
—
—
—
—
—
—
U6TXIP<2:0>
U6TXIS<1:0>
0000
15:0
—
—
—
U6RXIS<1:0>
—
—
—
U6EIP<2:0>
U6EIS<1:0>
0000
31:16
—
—
—
—
—
—
—
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
—
27/11
—
26/10
—
U6RXIP<2:0>
—
—
—
25/9
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
15:0
31:16
—
18/2
VOFF<15:1>
15:0
31:16
—
—
15:0
31:16
—
19/3
VOFF<15:1>
15:0
31:16
—
—
15:0
31:16
—
20/4
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 128
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0568
OFF010
056C
0570
0574
0578
057C
0580
0584
0588
058C
0590
0594
0598
059C
05A0
OFF011
OFF012
OFF013
OFF014
OFF015
OFF016
OFF017
OFF018
OFF019
OFF020
OFF021
OFF022
OFF023
OFF024
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001191F-page 129
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
05A4
OFF025
05A8
05AC
05B0
05B4
05B8
05BC
05C0
05C4
05C8
05CC
05D0
 2013-2016 Microchip Technology Inc.
05D4
05D8
05DC
OFF026
OFF027
OFF028
OFF029
OFF030
OFF031
OFF032
OFF033
OFF034
OFF035
OFF036
OFF037
OFF038
OFF039
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 130
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
05E0
OFF040
05E4
05E8
05EC
05F0
05F8
05FC
0600
0604
0608
060C
0610
0614
0618
061C
OFF041
OFF042
OFF043
OFF044
OFF046
OFF047
OFF048
OFF049
OFF050
OFF051
OFF052
OFF053
OFF054
OFF055
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001191F-page 131
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0620
OFF056
0624
062C
0630
0634
0638
063C
0640
0644
0648
064C
0650
 2013-2016 Microchip Technology Inc.
0654
0658
065C
OFF057
OFF059
OFF060
OFF061
OFF062
OFF063
OFF064
OFF065
OFF066
OFF067
OFF068
OFF069
OFF070
OFF071
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 132
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0660
OFF072
OFF073
0668
OFF074
066C
OFF075
0670
OFF076
0674
OFF077(2)
0678
OFF078
(2)
OFF079
(2)
0684
OFF081(2)
0688
OFF082(2)
068C
OFF083
(2)
OFF084
(2)
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
31:16
31:16
—
—
—
—
—
—
31:16
0698
(2)
31:16
—
—
—
—
—
—
DS60001191F-page 133
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
18/2
—
—
15:0
31:16
19/3
VOFF<15:1>
15:0
31:16
20/4
—
—
15:0
31:16
21/5
VOFF<15:1>
15:0
31:16
22/6
—
—
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
VOFF<15:1>
15:0
OFF085(2)
Note
28/12
15:0
0694
Legend:
29/13
15:0
OFF080(2)
OFF086
30/14
15:0
0680
0690
31:16
31/15
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
0664
067C
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
069C
OFF087(2)
OFF088(2)
06A4
OFF089
(2)
OFF090
(2)
06B0
(2)
OFF093(2)
06B8 OFF094
(2,4)
06BC OFF095
(2,4)
06C4 OFF097
06C8 OFF098
(2,4)
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
31:16
31:16
—
—
—
—
—
—
31:16
31:16
—
—
—
—
—
—
31:16
 2013-2016 Microchip Technology Inc.
(2,4)
—
—
—
—
—
—
06D4 OFF101(2,4)
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
18/2
—
—
15:0
31:16
19/3
VOFF<15:1>
15:0
31:16
20/4
—
—
15:0
31:16
21/5
VOFF<15:1>
15:0
31:16
22/6
—
—
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
VOFF<15:1>
15:0
06CC OFF099(2,4)
Note
27/11
15:0
(2,4)
Legend:
28/12
15:0
06C0 OFF096(2,4)
06D0 OFF100
29/13
15:0
OFF091(2)
06B4
30/14
15:0
06AC
OFF092
31:16
31/15
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
06A0
06A8
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 134
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
06D8
OFF102
OFF103
06E0
OFF104
06E4
OFF105
06E8
OFF106
OFF107(7)
06F4
06F8
06FC
0700
0704
0708
070C
0710
0714
OFF109
OFF110
OFF111
OFF112
OFF113
OFF114
OFF115
OFF116
OFF117
DS60001191F-page 135
Legend:
Note
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
06DC
06EC
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0718
OFF118(2)
0720
0724
0728
072C
0730
OFF119
OFF120
OFF121
OFF122
OFF123
OFF124
0734 OFF125
(2,4)
0738 OFF126
(2,4)
0744
 2013-2016 Microchip Technology Inc.
0748
074C
0750
OFF128
OFF129
OFF130
OFF131
OFF132
Legend:
31:16
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
31/15
15:0
073C OFF127(2,4,8)
0740
Bit Range
Bits
071C
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 136
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0754
OFF133
0758
075C
0760
0764
0768
076C
0770
0774
0778
077C
0780
0784
0788
078C
OFF134
OFF135
OFF136
OFF137
OFF138
OFF139
OFF140
OFF141
OFF142
OFF143
OFF144
OFF145
OFF146
OFF147
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001191F-page 137
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
Legend:
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0790
OFF148(2)
OFF149(2)
0798
OFF150
(2)
OFF151
(3)
07A0
07A8
07AC
07B0
07B4
07B8
07BC
 2013-2016 Microchip Technology Inc.
07C0
07C4
07C8
OFF153
OFF154
OFF155
OFF156
OFF157
OFF158
OFF159
OFF160
OFF161
OFF162
Legend:
Note
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
18/2
—
—
15:0
31:16
19/3
VOFF<15:1>
15:0
31:16
20/4
—
—
15:0
31:16
21/5
VOFF<15:1>
15:0
31:16
22/6
—
—
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
VOFF<15:1>
15:0
OFF152(3)
07A4
31:16
31/15
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
0794
079C
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 138
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
07CC
OFF163
OFF164
07D4
OFF165
07D8
OFF166
07DC
OFF167
07E0
OFF168
07E4
OFF169
07E8
OFF170
07EC
OFF171
07F0
OFF172
07F4
OFF173
07F8
OFF174
07FC
OFF175
0800
OFF176(2)
0804
(2)
OFF177
DS60001191F-page 139
Legend:
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Bits
07D0
Note
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF81_#)
Register
Name(1)
0808
OFF178(2)
OFF179
0810
OFF180
0814
OFF181
0818
OFF182
081C
OFF183
0820
0828
082C
OFF184
OFF185
(2)
OFF186
(2)
0834
 2013-2016 Microchip Technology Inc.
0838
OFF188
OFF189
OFF190
Legend:
31:16
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
15:0
31:16
—
—
—
15:0
31:16
—
VOFF<15:1>
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF<15:1>
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF<15:1>
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF<15:1>
15:0
31:16
23/7
VOFF<15:1>
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
—
—
VOFF<15:1>
—
—
—
—
—
—
17/1
16/0
All Resets
31/15
15:0
OFF187(2)
0830
Note
Bit Range
Bits
080C
0824
INTERRUPT REGISTER MAP (CONTINUED)
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
VOFF<17:16>
0000
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 140
TABLE 7-3:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
INTCON: INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
MVEC
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TPC<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode
bit 11
Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
 2013-2016 Microchip Technology Inc.
DS60001191F-page 141
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-2:
Bit
Range
PRISS: PRIORITY SHADOW SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
PRI7SS<3:0>(1)
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI1SS<3:0>(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI4SS<3:0>(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI2SS<3:0>(1)
PRI3SS<3:0>
7:0
Bit
25/17/9/1
PRI6SS<3:0>(1)
PRI5SS<3:0>(1)
15:8
Bit
26/18/10/2
R/W-0
U-0
U-0
U-0
R/W-0
—
—
—
SS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)
0111 = Interrupt with a priority level of 7 uses Shadow Set 7
0110 = Interrupt with a priority level of 7 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 7 uses Shadow Set 1
0000 = Interrupt with a priority level of 7 uses Shadow Set 0
bit 27-24 PRI6SS<3:0>: Interrupt with Priority Level 6 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0)
0111 = Interrupt with a priority level of 6 uses Shadow Set 7
0110 = Interrupt with a priority level of 6 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 6 uses Shadow Set 1
0000 = Interrupt with a priority level of 6 uses Shadow Set 0
bit 23-20 PRI5SS<3:0>: Interrupt with Priority Level 5 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0)
0111 = Interrupt with a priority level of 5 uses Shadow Set 7
0110 = Interrupt with a priority level of 5 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 5 uses Shadow Set 1
0000 = Interrupt with a priority level of 5 uses Shadow Set 0
bit 19-16 PRI4SS<3:0>: Interrupt with Priority Level 4 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0)
0111 = Interrupt with a priority level of 4 uses Shadow Set 7
0110 = Interrupt with a priority level of 4 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 4 uses Shadow Set 1
0000 = Interrupt with a priority level of 4 uses Shadow Set 0
Note 1:
These bits are ignored if the MVEC bit (INTCON<12>) = 0.
DS60001191F-page 142
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-2:
PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0)
0111 = Interrupt with a priority level of 3 uses Shadow Set 7
0110 = Interrupt with a priority level of 3 uses Shadow Set 6
•
•
•
bit 11-8
0001 = Interrupt with a priority level of 3 uses Shadow Set 1
0000 = Interrupt with a priority level of 3 uses Shadow Set 0
PRI2SS<3:0>: Interrupt with Priority Level 2 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0)
0111 = Interrupt with a priority level of 2 uses Shadow Set 7
0110 = Interrupt with a priority level of 2 uses Shadow Set 6
•
•
•
bit 7-4
0001 = Interrupt with a priority level of 2 uses Shadow Set 1
0000 = Interrupt with a priority level of 2 uses Shadow Set 0
PRI1SS<3:0>: Interrupt with Priority Level 1 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0)
0111 = Interrupt with a priority level of 1 uses Shadow Set 7
0110 = Interrupt with a priority level of 1 uses Shadow Set 6
•
•
•
bit 3-1
bit 0
0001 = Interrupt with a priority level of 1 uses Shadow Set 1
0000 = Interrupt with a priority level of 1 uses Shadow Set 0
Unimplemented: Read as ‘0’
SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
Note 1:
These bits are ignored if the MVEC bit (INTCON<12>) = 0.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 143
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
INTSTAT: INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
SRIPL<2:0>
R-0
R-0
R-0
SIRQ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8
bit 7-6
bit 7-0
SRIPL<2:0>: Requested Priority Level bits for Single Vector Mode bits
111-000 = The priority level of the latest interrupt presented to the CPU
Unimplemented: Read as ‘0’
SIRQ<7:0>: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
IPTMR<31:0>: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.
DS60001191F-page 144
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-5:
Bit
Range
31:24
23:16
15:8
7:0
IFSx: INTERRUPT FLAG STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS31
IFS30
IFS29
R/W-0
R/W-0
R/W-0
IFS28
IFS27
IFS26
IFS25
IFS24
R/W-0
R/W-0
R/W-0
R/W-0
IFS23
IFS22
IFS21
R/W-0
IFS20
IFS19
IFS18
IFS17
IFS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS15
IFS14
IFS13
IFS12
IFS11
IFS10
IFS9
IFS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS7
IFS6
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
IFS31-IFS0: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit
definitions.
REGISTER 7-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
Bit
31/23/15/7
IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC31
IEC30
IEC29
IEC28
IEC27
IEC26
IEC25
IEC24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC23
IEC22
IEC21
IEC20
IEC19
IEC18
IEC17
IEC16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC15
IEC14
IEC13
IEC12
IEC11
IEC10
IEC9
IEC8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC7
IEC6
IEC5
IEC4
IEC3
IEC2
IEC1
IEC0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
Bit
24/16/8/0
x = Bit is unknown
IEC31-IEC0: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit
definitions.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 145
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-7:
Bit
Range
IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
IP3<2:0>
R/W-0
R/W-0
IS3<1:0>
R/W-0
IP2<2:0>
R/W-0
R/W-0
R/W-0
IP0<2:0>
R/W-0
IS2<1:0>
R/W-0
IP1<2:0>
R/W-0
R/W-0
R/W-0
R/W-0
IS1<1:0>
R/W-0
R/W-0
R/W-0
IS0<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS3<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS2<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note:
This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.
DS60001191F-page 146
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-7:
IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
bit 12-10 IP1<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 9-8
bit 7-5
bit 4-2
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS1<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
Unimplemented: Read as ‘0’
IP0<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 1-0
Note:
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS0<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 147
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 7-8:
Bit
Range
31:24
23:16
15:8
7:0
OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VOFF<17:16>
R/W-0
R/W-0
R/W-0
U-0
VOFF<15:8>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
R/W-0
VOFF<7:1>
W = Writable bit
‘1’ = Bit is set
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 17-1 VOFF<17:1>: Interrupt Vector ‘x’ Address Offset bits
bit 0
Unimplemented: Read as ‘0’
DS60001191F-page 148
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
8.0
Note:
OSCILLATOR
CONFIGURATION
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 42.
“Oscillators with Enhanced PLL”
(DS60001250), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The PIC32MZ EC oscillator system has the following
modules and features:
• A total of five external and internal oscillator options
as clock sources
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating frequency on select internal and external oscillator
sources
• On-Chip user-selectable divisor postscaler on select
oscillator sources
• Software-controllable switching between 
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or shutdown with dedicated Back-up FRC (BFRC)
• Dedicated On-Chip PLL for USB peripheral
• Flexible reference clock output
• Multiple clock branches for peripherals for better
performance flexibility
A block diagram of the oscillator system is provided in
Figure 8-1. Table 8-1 shows the clock distribution.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 149
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 8-1:
PIC32MZ EC FAMILY OSCILLATOR DIAGRAM
(12 or 24 MHz only)
From POSC
USB Clock (USBCLK)
USB PLL
Reference Clock(5)
UPLLEN
REFOxCON
UPLLFSEL
REFCLKIx
N
FVco(6)
FIN(6)
PLL x M
PLLODIV<2:0>
(N)
PLLIDIV<2:0>
PLLRANGE<2:0>
(N)
PLLMULT<6:0>
PLLICLK
(M)
N
FPLL(6)
OE
ROTRIM<8:0> (M)
POSC
FRC
LPRC
SOSC
PBCLK1
SYSCLK
BFRC
System PLL
REFOxTRIM
M
 2   N + --------512
REFCLKOx
FREF(6)
RODIV<14:0> (N)
To SPI,
ADC,
SQI
‘x’ = 1-4
SPLL
ROSEL<3:0>
(To USB PLL)
VDD
Primary Oscillator (POSC)
OSC1
C1(3)
XTAL 1 M
10 k
SPLL
To
SYSCLK
Mux
POSC (HS, EC)
RF(2)
Enable
C2(3)
Peripheral Bus Clock(5)
Peripherals,
CPU
Postscaler
PBCLKx
PBxDIV<6:0>
(N)
‘x’ = 1-5, 7, 8
OSC2(4)
To ADC and Flash
FRC
Oscillator
8 MHz typical
Postscaler
SYSCLK
FRCDIV
Fsys(6)
FRCDIV<2:0>
(N)
TUN<5:0>
Backup FRC
Oscillator
8 MHz typical
LPRC
Oscillator
N
BFRC
LPRC
32.768 kHz
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSC
SOSCEN
Clock Control Logic
SOSCI
Fail-Safe
Clock
Monitor
FSCM INT
FSCM Event
NOSC<2:0>
COSC<2:0>
OSWEN
FCKSM<1:0>
WDT, RTCC
Timer1, RTCC
Notes:
1.
2.
3.
4.
5.
6.
A series resistor, RS, may be required for AT strip cut crystals, or to eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, RP.
The internal feedback resistor, RF, is typically in the range of 2 to 10 M
Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for help in determining the best oscillator components.
PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
Shaded regions indicate multiple instantiations of a peripheral or feature.
Refer to Table 37-19 in Section 37.0 “Electrical Characteristics” for frequency limitations.
DS60001191F-page 150
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 8-1:
SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION
CPU
X
WDT
X
X(2)
Deadman Timer
X(2)
X
(2)
(2)
(2)
Flash
X
X
X
ADC
X
X
X(3)
Comparator
X
Crypto
X
RNG
X
USB
X
X(3)
CAN
X
Ethernet
X(3)
PMP
X
2
I C
X
UART
X
RTCC
X
X
X(2)
EBI
X
SQI
X(3)
X
SPI
X
X
Timers
X(4)
X
Output Compare
X
Input Capture
X
Ports
X
DMA
X
Interrupts
X
Prefetch
X
OSC2 Pin
X(5)
Note 1: PBCLK1 is used by system modules and cannot be turned off.
2: SYSCLK/PBCLK1 is used to fetch data from/to the Flash Controller, while the FRC clock is used for
programming.
3: Special Function Register (SFR) access only.
4: Timer1 only.
5: PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
8.1
REFCLKO3
REFCLKO2
REFCLKO1
PBCLK8
PBCLK7
PBCLK5
PBCLK4
PBCLK3
PBCLK2
PBCLK1(1)
USBCLK
SYSCLK
SOSC
LPRC
Peripheral
FRC
Clock Source
X
Fail-Safe Clock Monitor (FSCM)
The PIC32MZ EC oscillator system includes a Fail-safe
Clock Monitor (FSCM). The FSCM monitors the
SYSCLK for continuous operation. If it detects that the
SYSCLK has failed, it switches the SYSCLK over to the
BFRC oscillator and triggers a NMI. The BFRC is an
untuned 8 MHz oscillator that will drive the SYSCLK
during FSCM event. When the NMI is executed, software can attempt to restart the main oscillator or shut
down the system.
In Sleep mode both the SYSCLK and the FSCM halt,
which prevents FSCM detection.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 151
Oscillator Control Registers
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
 2013-2016 Microchip Technology Inc.
31:16
—
—
—
—
—
FRCDIV<2:0>
DRMEN SOSCRDY
15:0
—
COSC<2:0>
—
NOSC<2:0>
CLKLOCK
ULOCK
31:16
—
—
—
—
—
—
—
—
—
—
1210 OSCTUN
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
PLLODIV<2:0>
—
1220 SPLLCON
15:0
—
—
—
—
—
PLLIDIV<2:0>
PLLICLK
—
31:16
—
RODIV<14:0>
1280 REFO1CON
15:0
ON
—
SIDL
OE
RSLP
—
DIVSWEN ACTIVE
—
—
31:16
ROTRIM<8:0>
—
1290 REFO1TRIM
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
RODIV<14:0>
12A0 REFO2CON
15:0
ON
—
SIDL
OE
RSLP
—
DIVSWEN ACTIVE
—
—
31:16
ROTRIM<8:0>
—
12B0 REFO2TRIM
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
RODIV<14:0>
12C0 REFO3CON
15:0
ON
—
SIDL
OE
RSLP
—
DIVSWEN ACTIVE
—
—
31:16
ROTRIM<8:0>
—
12D0 REFO3TRIM
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
RODIV<14:0>
12E0 REFO4CON
15:0
ON
—
SIDL
OE
RSLP
—
DIVSWEN ACTIVE
—
—
31:16
ROTRIM<8:0>
—
12F0 REFO4TRIM
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1300
PB1DIV
15:0
—
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1310
PB2DIV
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1320
PB3DIV
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1330
PB4DIV
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1340
PB5DIV
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1360
PB7DIV
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
1370
PB8DIV
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
1200
OSCCON
21/5
20/4
—
SLOCK
—
—
SLPEN
—
19/3
18/2
17/1
16/0
—
—
—
—
—
CF
—
SOSCEN OSWEN
—
—
—
—
TUN<5:0>
PLLMULT<6:0>
—
—
PLLRANGE<2:0>
—
—
—
—
—
—
—
—
ROSEL<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ROSEL<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ROSEL<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ROSEL<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PBDIV<6:0>
—
PBDIV<6:0>
—
PBDIV<6:0>
—
PBDIV<6:0>
—
PBDIV<6:0>
—
PBDIV<6:0>
—
PBDIV<6:0>
All Resets(1)
OSCILLATOR CONFIGURATION REGISTER MAP
Bits
Register
Name
Virtual Address
(BF80_#)
TABLE 8-2:
0000
xx0x
0000
0000
01xx
0x0x
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
8801
0000
8801
0000
8801
0000
8801
0000
8801
0000
8800
0000
8801
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 152
8.2
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-1:
Bit
Range
31:24
23:16
15:8
7:0
OSCCON: OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R-0
U-0
U-0
U-0
DRMEN
SOSCRDY
—
—
—
—
—
—
U-0
R-0
R-0
R-0
U-0
R/W-y
R/W-y
R/W-y
—
Bit
Bit
28/20/12/4 27/19/11/3
COSC<2:0>
Bit
26/18/10/2
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRCDIV<2:0>
U-0
—
U-0
U-0
NOSC<2:0>
R/W-0
R-0
R-0
R/W-0
R/W-0, HS
U-0
R/W-y
R/W-y
CLKLOCK
ULOCK
SLOCK
SLPEN
CF
—
SOSCEN
OSWEN(1)
Legend:
R = Readable bit
y = Value set from Configuration bits on POR
HS = Hardware Set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default setting)
bit 23
DRMEN: Dream Mode Enable bit
1 = Dream mode is enabled
0 = Dream mode is disabled
SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary Oscillator is still warming up or is turned off
bit 21-15 Unimplemented: Read as ‘0’
bit 22
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
110 = Back-up Fast RC (BFRC) Oscillator
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
bit 11
Unimplemented: Read as ‘0’
Note 1:
Note:
The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 153
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-1:
bit 10-8
bit 7
OSCCON: OSCILLATOR CONTROL REGISTER
NOSC<2:0>: New Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
110 = Reserved
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (DEVCFG1<2:0>).
CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
bit 6
ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or
USB PLL is disabled
bit 5
SLOCK: System PLL Lock Status bit
1 = System PLL module is in lock or module start-up timer is satisfied
0 = System PLL module is out of lock, start-up timer is running or system PLL is disabled
SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 4
bit 3
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2
bit 1
Unimplemented: Read as ‘0’
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0
OSWEN: Oscillator Switch Enable bit(1)
1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1:
The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001191F-page 154
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-2:
Bit
Range
31:24
23:16
15:8
7:0
OSCTUN: FRC TUNING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R/W-0
(1)
TUN<5:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
Unimplemented: Read as ‘0’
bit 5-0
TUN<5:0>: FRC Oscillator Tuning bits(1)
100000 = Center frequency -12.5%
100001 =
•
•
•
111111 =
000000 = Center frequency; Oscillator runs at minimal frequency (8 MHz)
000001 =
•
•
•
011110 =
011111 = Center frequency +12.5%
x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 155
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-3:
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
U-0
R/W-y
—
—
—
—
—
U-0
R/W-y
R/W-y
R/W-y
—
U-0
15:8
7:0
SPLLCON: SYSTEM PLL CONTROL REGISTER
R/W-y
Bit
25/17/9/1
Bit
24/16/8/0
R/W-y
R/W-y
PLLODIV<2:0>
R/W-y
R/W-y
R/W-y
R/W-y
R/W-y
PLLMULT<6:0>
U-0
U-0
U-0
U-0
R/W-y
—
PLLIDIV<2:0>
R/W-y
U-0
U-0
U-0
U-0
PLLICLK
—
—
—
—
R/W-y
R/W-y
R/W-y
PLLRANGE<2:0>
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits
111 = Reserved
110 = Reserved
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = Reserved
The default setting is specified by the FPLLODIV<2:0> Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 “Special Features” for information.
bit 23
Unimplemented: Read as ‘0’
bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
The default setting is specified by the FPLLMULT<6:0> Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 “Special Features” for information.
bit 15-11 Unimplemented: Read as ‘0’
Note 1:
2:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0> = 001).
DS60001191F-page 156
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-3:
bit 10-8
SPLLCON: SYSTEM PLL CONTROL REGISTER
PLLIDIV<2:0>: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV<2:0> Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information. If the PLLICLK bit is set for FRC, this
setting is ignored by the PLL and the divider is set for Divide-by-1.
bit 7
PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the System PLL
0 = POSC is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
PLLRANGE<2:0>: System PLL Frequency Range Selection bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
The default setting is specified by the FPLLRNG<2:0> Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
Note 1:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0> = 001).
2:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 157
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-4:
Bit
Range
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (x = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
R/W-0
R/W-0
R/W-0
31:24
—
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV<14:8>
R/W-0
23:16
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
RODIV<7:0>
15:8
7:0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
ON(1)
—
SIDL
OE
RSLP(2)
—
DIVSWEN
ACTIVE(1)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
ROSEL<3:0>(3)
HC = Hardware Clearable HS = Hardware Settable
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-16 RODIV<14:0> Reference Clock Divider bits
The value selects the reference clock divider bits (see Figure 8-1 for details). A value of ‘0’ selects no divider.
bit 15
ON: Output Enable bit(1)
1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin
bit 11
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep
bit 10
Unimplemented: Read as ‘0’
bit 9
DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8
ACTIVE: Reference Clock Request Status bit(1)
1 = Reference clock request is active
0 = Reference clock request is not active
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
ROSEL<3:0>: Reference Clock Source Select bits(3)
1111 = Reserved
•
•
•
1001 =
1000 =
0111 =
0110 =
0101 =
0100 =
0011 =
0010 =
0001 =
0000 =
Note 1:
2:
3:
BFRC
REFCLKIx
System PLL output
Reserved
SOSC
LPRC
FRC
POSC
PBCLK1
SYSCLK
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
The ROSEL<3:0> bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
DS60001191F-page 158
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-5:
Bit
Range
31:24
23:16
15:8
7:0
REFOxTRIM: REFERENCE OSCILLATOR TRIM REGISTER (x = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ROTRIM<0>
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ROTRIM<8:1>
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits
111111111 = 511/512 divisor added to RODIV value
111111110 = 510/512 divisor added to RODIV value
•
•
•
100000000 = 256/512 divisor added to RODIV value
•
•
•
000000010 = 2/512 divisor added to RODIV value
000000001 = 1/512 divisor added to RODIV value
000000000 = 0 divisor added to RODIV value
bit 22-0
Unimplemented: Read as ‘0’
Note 1:
While the ON bit (REFOxCON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
Do not write to this register when the ON bit (REFOxCON<15>) is not equal to the ACTIVE bit
(REFOxCON<8>).
Specified values in this register do not take effect if RODIV<14:0> (REFOxCON<30:16>) = 0.
2:
3:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 159
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 8-6:
Bit
Range
31:24
23:16
15:8
7:0
PBxDIV: PERIPHERAL BUS ‘x’ CLOCK DIVISOR CONTROL REGISTER (‘x’ = 1-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
(1)
U-0
U-0
U-0
R-1
U-0
U-0
U-0
—
—
—
PBDIVRDY
—
—
—
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ON
—
PBDIV<6:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Peripheral Bus ‘x’ Output Clock Enable bit(1)
1 = Output clock is enabled
0 = Output clock is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
PBDIVRDY: Peripheral Bus ‘x’ Clock Divisor Ready bit
1 = Clock divisor logic is not switching divisors and the PBxDIV<6:0> bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV<6:0> bits cannot be written
bit 10-7
Unimplemented: Read as ‘0’
bit 6-0
PBDIV<6:0>: Peripheral Bus ‘x’ Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x  7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)
Note 1: The clock for peripheral bus 1 cannot be turned off. Therefore, the ON bit in the PB1DIV register cannot
be written as a ‘0’.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001191F-page 160
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
9.0
PREFETCH MODULE
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 41. “Prefetch
Module for Devices with L1 CPU
Cache” (DS60001183), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The Prefetch module is a performance enhancing
module that is included in PIC32MZ EC family devices.
When running at high-clock rates, Wait states must be
inserted into Program Flash Memory (PFM) read
transactions to meet the access time of the PFM. Wait
states can be hidden to the core by prefetching and
storing instructions in a temporary holding area that the
CPU can access quickly. Although the data path to the
CPU is 32 bits wide, the data path to the PFM is 128
bits wide. This wide data path provides the same
bandwidth to the CPU as a 32-bit path running at four
times the frequency.
FIGURE 9-1:
The Prefetch module holds a subset of PFM in
temporary holding spaces known as lines. Each line
contains a tag and data field. Normally, the lines hold a
copy of what is currently in memory to make
instructions or data available to the CPU without Flash
Wait states.
9.1
•
•
•
•
•
•
•
Features
4x16 byte fully-associative lines
One line for CPU instructions
One line for CPU data
Two lines for peripheral data
16-byte parallel memory fetch
Configurable predictive prefetch
Error detection and correction
A simplified block diagram of the Prefetch module is
shown in Figure 9-1.
PREFETCH MODULE BLOCK DIAGRAM
SYSCLK
CPU
Prefetch Buffer
Data
CPU
Tag
Bus Control
Line Control
Program Flash Memory (PFM)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 161
Prefetch Control Registers
Virtual Address
(BF8E_#)
Register
Name(1)
TABLE 9-1:
0000
PRECON
0010
PREFETCH REGISTER MAP
PRESTAT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
PFMSECEN
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
PFMDED
PFMSEC
—
—
—
—
15:0
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
PREFEN<1:0>
—
—
—
—
PFMSECCNT<7:0>
17/1
16/0
—
—
PFMWS<2:0>
—
—
All Resets
Bit Range
Bits
0000
0007
—
0000
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 162
9.2
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 9-1:
Bit Range
PRECON: PREFETCH MODULE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
U-0
U-0
—
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
U-0
U-0
—
—
PFMSECEN
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
—
Bit
Bit
28/20/12/4 27/19/11/3
PREFEN<1:0>
—
PFMWS<2:0>(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27
Unimplemented: Read as ‘0’
bit 26
PFMSECEN: Flash SEC Interrupt Enable bit
1 = Generate an interrupt when the PFMSEC bit (PRESTAT<26>) is set
0 = Do not generate an interrupt when the PFMSEC bit is set
bit 25-6
Unimplemented: Read as ‘0’
bit 5-4
PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for any address
10 = Enable predictive prefetch for CPU instructions and CPU data
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PFMWS<2:0>: PFM Access Time Defined in Terms of SYSCLK Wait States bits(1)
111 = Seven Wait states
•
•
•
010 = Two Wait states
001 = One Wait state
000 = Zero Wait states
Note 1:
For the Wait states to SYSCLK relationship, refer to Table 37-13 in Section37.0 “Electrical
Characteristics”.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 163
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 9-2:
Bit
Range
31:24
23:16
15:8
7:0
PRESTAT: PREFETCH MODULE STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
U-0
U-0
—
—
—
—
PFMDED
PFMSEC
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PFMSECCNT<7:0>
Legend:
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27
PFMDED: Flash Double-bit Error Detected (DED) Status bit
This bit is set in hardware and can only be cleared (i.e., set to ‘0’) in software.
1 = A DED error has occurred
0 = A DED error has not occurred
bit 26
PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit
1 = A SEC error occurred when PFMSECCNT<7:0> was equal to ‘0’
0 = A SEC error has not occurred
bit 25-8
Unimplemented: Read as ‘0’
bit 7-0
PFMSECCNT<7:0>: Flash SEC Count bits
11111111 - 00000000 = SEC count
This field decrements by one each time an SEC error occurs. It will hold at zero on the two-hundred and
fifty-sixth error. When an SEC error occurs, when PFMSECCNT = 0, the PFMSEC status bit is set. If
PFMSECEN is also set, an interrupt is generated.
Note:
DS60001191F-page 164
These bits count all SEC errors and are not limited to SEC errors on unique addresses.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
10.0
Note:
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS60001117), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Direct Memory Access (DMA) Controller is a bus
master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the device such
as SPI, UART, PMP, etc., or memory itself.
Note:
To avoid cache coherency problems on
devices with L1 cache, DMA buffers must
only be allocated or accessed from the
KSEG1 segment.
Following are some of the key features of the DMA
Controller module:
• Eight identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory to memory and memory to
peripheral transfers
FIGURE 10-1:
INT Controller
Peripheral Bus
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of the
peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any
of the peripheral interrupt sources
- Up to 2-byte Pattern (data) match transfer
termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent error address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
DMA BLOCK DIAGRAM
System IRQ
SE
Address Decoder
Channel 0 Control
I0
Channel 1 Control
I1
DMA
SYSCLK
L
Y
Bus
Interface
System Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel n Control
In
L
SE
Channel Priority
Arbitration
 2013-2016 Microchip Technology Inc.
DS60001191F-page 165
DMA Control Registers
Virtual Address
(BF81_#)
Register
Name(1)
TABLE 10-1:
1000
DMACON
1010
DMASTAT
DMA GLOBAL REGISTER MAP
1020 DMAADDR
—
—
ON
RDWR
—
—
—
—
15:0
31:16
—
—
—
All Resets
—
15:0
31:16
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
SUSPEND DMABUSY
—
—
—
—
DMACH<2:0>
0000
0000
0000
DMA CRC REGISTER MAP
Bits
Register
Name(1)
Virtual Address
(BF81_#)
31:16
28/12
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
1030 DCRCCON
1040 DCRCDATA
 2013-2016 Microchip Technology Inc.
1050 DCRCXOR
Note 1:
29/13
DMAADDR<31:0>
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 10-2:
Legend:
30/14
31/15
30/14
31:16
—
—
15:0
31:16
—
—
15:0
31:16
29/13
28/12
BYTO<1:0>
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN<4:0>
23/7
—
CRCEN
DCRCDATA<31:0>
DCRCXOR<31:0>
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
CRCAPP CRCTYP
17/1
16/0
—
—
CRCCH<2:0>
All Resets
Note 1:
31/15
Bit Range
Legend:
Bit Range
Bits
0000
0000
0000
0000
0000
0000
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 166
10.1
Virtual Address
(BF81_#)
1070 DCH0ECON
DCH0INT
31/15
30/14
29/13
15:0 CHBUSY
—
CHPIGNEN
31:16
—
—
31:16
15:0
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
—
—
CHCHNS
—
CHEN
—
CHAED
—
CHCHN
—
CHAEN
—
—
—
CHEDET
—
—
CHSIRQ<7:0>
—
—
—
PATEN
CHAIRQ<7:0>
SIRQEN AIRQEN
—
—
—
—
CHPIGN<7:0>
—
15:0
31:16
28/12
—
—
—
—
—
—
—
CHPATLEN
—
—
CFORCE CABORT
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDDIE
CHDDIF
CHDHIE
CHDHIF
CHBCIE
CHBCIF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
1060 DCH0CON
1080
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP
—
—
CHPRI<1:0>
0000
0000
—
—
00FF
FF00
CHCCIE
CHCCIF
CHTAIE
CHTAIF
—
CHERIE 0000
CHERIF 0000
1090 DCH0SSA
31:16
15:0
CHSSA<31:0>
0000
0000
10A0 DCH0DSA
31:16
15:0
CHDSA<31:0>
0000
0000
10B0 DCH0SSIZ
10C0 DCH0DSIZ
10D0 DCH0SPTR
10E0 DCH0DPTR
10F0 DCH0CSIZ
1100 DCH0CPTR
1110
DCH0DAT
1120 DCH1CON
1130 DCH1ECON
1140
DCH1INT
DS60001191F-page 167
1150 DCH1SSA
1160 DCH1DSA
Legend:
Note 1:
31:16
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHSPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHPDAT<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
0000
CHPIGNEN
—
—
—
—
—
CHCHNS
—
CHPRI<1:0>
—
—
—
0000
00FF
31:16
—
—
—
CHSIRQ<7:0>
—
—
—
—
—
15:0
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
CHPIGN<7:0>
15:0 CHBUSY
31:16
15:0
31:16
15:0
31:16
—
—
CHPATLEN
—
—
—
—
—
CHEN
CHAED
CHCHN
CHAEN
—
CHAIRQ<7:0>
CHEDET
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSSA<31:0>
CHDSA<31:0>
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CHSHIF
CHDDIF
0000
0000
0000
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF81_#)
1180 DCH1DSIZ
1190 DCH1SPTR
11A0 DCH1DPTR
11B0 DCH1CSIZ
11C0 DCH1CPTR
11D0 DCH1DAT
11E0 DCH2CON
11F0 DCH2ECON
DCH2INT
1210 DCH2SSA
1220 DCH2DSA
 2013-2016 Microchip Technology Inc.
1230 DCH2SSIZ
1240 DCH2DSIZ
1250 DCH2SPTR
1260 DCH2DPTR
1270 DCH2CSIZ
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
15:0
—
—
—
15:0
—
—
CHPATLEN
—
—
—
—
—
CHCHNS
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHEN
CHAED
CHCHN
—
—
—
—
—
0000
CHPRI<1:0>
0000
00FF
CHAEN
—
CHAIRQ<7:0>
CHEDET
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSHIF
CHDDIF
0000
0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCSIZ<15:0>
0000
0000
—
—
—
—
—
—
—
CHDPTR<15:0>
—
0000
0000
CHSPTR<15:0>
—
0000
0000
CHDSIZ<15:0>
—
0000
0000
CHSSIZ<15:0>
—
0000
0000
CHDSA<31:0>
15:0
31:16
0000
0000
CHSSA<31:0>
15:0
31:16
0000
0000
CHPDAT<15:0>
CHPIGN<7:0>
0000
0000
CHCPTR<15:0>
CHPIGNEN
—
15:0
—
20/4
CHCSIZ<15:0>
—
—
15:0
31:16
—
21/5
CHDPTR<15:0>
15:0 CHBUSY
15:0
31:16
—
—
CHSSIZ<15:0>
22/6
CHSPTR<15:0>
31:16
15:0
31:16
23/7
CHDSIZ<15:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
1170 DCH1SSIZ
1200
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
0000
—
—
—
—
—
—
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 168
TABLE 10-3:
Virtual Address
(BF81_#)
1290 DCH2DAT
12A0 DCH3CON
12B0 DCH3ECON
DCH3INT
12D0 DCH3SSA
12E0 DCH3DSA
12F0 DCH3SSIZ
1300 DCH3DSIZ
1310 DCH3SPTR
1320 DCH3DPTR
1330 DCH3CSIZ
1340 DCH3CPTR
1350 DCH3DAT
DS60001191F-page 169
1360 DCH4CON
1370 DCH4ECON
1380
DCH4INT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
CHPIGNEN
—
31:16
—
—
—
15:0
—
—
—
15:0
—
—
—
—
—
—
CHPATLEN
—
15:0
31:16
15:0
31:16
15:0
31:16
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
CHCHNS
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHEN
CHAED
CHCHN
—
—
—
—
—
0000
CHPRI<1:0>
0000
00FF
CHAEN
—
CHAIRQ<7:0>
CHEDET
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSHIF
CHDDIF
0000
0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPIGN<7:0>
15:0 CHBUSY
—
—
—
CHPIGNEN
—
31:16
—
—
—
15:0
—
—
—
15:0
—
—
CHPATLEN
—
—
—
—
—
CHCHNS
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
CHPDAT<15:0>
31:16
0000
0000
CHCPTR<15:0>
—
0000
0000
CHCSIZ<15:0>
—
0000
0000
CHDPTR<15:0>
—
0000
0000
CHSPTR<15:0>
—
0000
0000
CHDSIZ<15:0>
—
0000
0000
CHDSA<31:0>
—
0000
0000
CHSSA<31:0>
15:0
31:16
19/3
—
—
15:0
31:16
15:0
31:16
20/4
—
—
31:16
15:0
31:16
21/5
CHPIGN<7:0>
15:0 CHBUSY
15:0
31:16
22/6
CHPDAT<15:0>
31:16
15:0
31:16
23/7
CHCPTR<15:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
1280 DCH2CPTR
12C0
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
0000
—
—
—
CHEN
CHAED
CHCHN
—
—
—
—
—
0000
CHPRI<1:0>
0000
00FF
CHAEN
—
CHAIRQ<7:0>
CHEDET
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
CHSHIF
CHDDIF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF81_#)
13A0 DCH4DSA
13B0 DCH4SSIZ
13C0 DCH4DSIZ
13D0 DCH4SPTR
13E0 DCH4DPTR
13F0 DCH4CSIZ
1400 DCH4CPTR
1410 DCH4DAT
1420 DCH5CON
1430 DCH5ECON
DCH5INT
 2013-2016 Microchip Technology Inc.
1450 DCH5SSA
1460 DCH5DSA
1470 DCH5SSIZ
1480 DCH5DSIZ
1490 DCH5SPTR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0000
0000
CHSSA<31:0>
31:16
0000
CHDSA<31:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
1390 DCH4SSA
1440
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHSPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHPDAT<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
0000
CHPIGNEN
—
—
—
—
—
CHCHNS
—
CHPRI<1:0>
—
—
—
0000
00FF
31:16
—
—
—
CHSIRQ<7:0>
—
—
—
—
—
15:0
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
CHPIGN<7:0>
15:0 CHBUSY
31:16
15:0
—
—
CHPATLEN
—
—
31:16
—
CHCHN
CHAEN
—
CHAIRQ<7:0>
CHEDET
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSHIF
CHDDIF
0000
0000
CHDSA<31:0>
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
—
CHAED
CHSSA<31:0>
15:0
31:16
15:0
31:16
—
CHEN
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
—
—
0000
CHDSIZ<15:0>
—
—
—
—
—
—
—
—
—
CHSPTR<15:0>
0000
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 170
TABLE 10-3:
Virtual Address
(BF81_#)
14B0 DCH5CSIZ
14C0 DCH5CPTR
14D0 DCH5DAT
14E0 DCH6CON
14F0 DCH6ECON
DCH6INT
1510 DCH6SSA
1520 DCH6DSA
1530 DCH6SSIZ
1540 DCH6DSIZ
1550 DCH6SPTR
1560 DCH6DPTR
1570 DCH6CSIZ
1580 DCH6CPTR
DS60001191F-page 171
1590 DCH6DAT
15A0 DCH7CON
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPIGNEN
—
31:16
—
—
—
15:0
—
—
—
31:16
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
CHDPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
CHCSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
CHCPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
CHPDAT<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
0000
—
—
—
—
CHCHNS
—
CHPRI<1:0>
0000
00FF
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
CHPIGN<7:0>
15:0 CHBUSY
31:16
15:0
—
—
CHPATLEN
—
—
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
15:0
31:16
—
—
—
CHEN
CHAED
CHCHN
CHAEN
—
CHAIRQ<7:0>
CHEDET
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSHIF
CHDDIF
0000
0000
CHDSA<31:0>
15:0
31:16
15:0
31:16
23/7
CHSSA<31:0>
15:0
31:16
15:0
31:16
24/8
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0 CHBUSY
—
—
—
—
CHPIGN<7:0>
0000
0000
—
—
—
—
—
—
—
CHPDAT<15:0>
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
CHCPTR<15:0>
15:0
0000
0000
CHCSIZ<15:0>
—
0000
0000
CHDPTR<15:0>
—
0000
0000
CHSPTR<15:0>
—
0000
0000
CHDSIZ<15:0>
—
All Resets
Bit Range
Register
Name(1)
Bits
14A0 DCH5DPTR
1500
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
0000
—
—
—
—
—
—
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
—
—
0000
CHPRI<1:0>
0000
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF81_#)
DCH7INT
31:16
31/15
30/14
29/13
—
—
—
15:0
31:16
15:0
—
—
—
—
—
—
28/12
27/11
26/10
25/9
24/8
—
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
23/7
22/6
CFORCE CABORT
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
21/5
PATEN
CHDDIE
CHDDIF
20/4
19/3
CHAIRQ<7:0>
SIRQEN AIRQEN
CHDHIE
CHDHIF
CHBCIE
CHBCIF
18/2
17/1
16/0
—
—
—
CHCCIE
CHCCIF
CHTAIE
CHTAIF
All Resets
Bit Range
Register
Name(1)
Bits
15B0 DCH7ECON
15C0
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
00FF
FF00
CHERIE 0000
CHERIF 0000
15D0 DCH7SSA
31:16
15:0
CHSSA<31:0>
0000
0000
15E0 DCH7DSA
31:16
15:0
CHDSA<31:0>
0000
0000
15F0 DCH7SSIZ
1600 DCH7DSIZ
1610 DCH7SPTR
1620 DCH7DPTR
1630 DCH7CSIZ
1640 DCH7CPTR
1650 DCH7DAT
Legend:
Note 1:
31:16
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHSPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCSIZ<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHPDAT<15:0>
—
—
—
—
—
—
—
0000
0000
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 172
TABLE 10-3:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
U-0
DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
U-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
ON
—
—
SUSPEND
DMABUSY
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit
1 = DMA module is active and is transferring data
0 = DMA module is disabled and not actively transferring data
bit 10-0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 173
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-2:
Bit
Range
31:24
23:16
15:8
7:0
DMASTAT: DMA STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RDWR
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
DMACH<2:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
RDWR: Read/Write Status bit
1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
bit 30-3 Unimplemented: Read as ‘0’
bit 2-0
DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel when an error was detected.
REGISTER 10-3:
Bit
Range
31:24
23:16
15:8
7:0
DMAADDR: DMA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR<31:24>
R-0
R-0
DMAADDR<23:16>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR<15:8>
R-0
R-0
DMAADDR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DMAADDR<31:0>: DMA Module Address bits
These bits contain the address of the most recent DMA access when an error was detected.
DS60001191F-page 174
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-4:
Bit
Range
31:24
23:16
15:8
7:0
DCRCCON: DMA CRC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
BYTO<1:0>
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
(1)
—
—
WBO
—
—
BITO
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
PLEN<4:0>(1)
R/W-0
R/W-0
R/W-0
U-0
U-0
CRCEN
CRCAPP(1)
CRCTYP
—
—
R/W-0
CRCCH<2:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
PLEN<4:0>: Polynomial Length bits(1)
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 175
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-4:
DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
CRCCH<2:0>: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
DS60001191F-page 176
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-5:
Bit
Range
31:24
23:16
15:8
7:0
DCRCDATA: DMA CRC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA<31:24>
R/W-0
R/W-0
DCRCDATA<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 10-6:
Bit
Range
31:24
23:16
15:8
7:0
DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR<15:8>
R/W-0
R/W-0
DCRCXOR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
 2013-2016 Microchip Technology Inc.
DS60001191F-page 177
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-7:
Bit
Range
31:24
23:16
15:8
7:0
DCHxCON: DMA CHANNEL x CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
CHBUSY
—
CHIPGNEN
—
CHPATLEN
—
—
CHCHNS(1)
R/W-0
R/W-0
CHPIGN<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
CHEN(2)
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI<1:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 CHPIGN<7:0>: Channel Register Data bits
Pattern Terminate mode:
Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match
logic will treat it as a “don’t care” when the pattern matching logic is enabled and the CHPIGEN bit is set.
bit 23-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CHPIGNEN: Enable Pattern Ignore Byte bit
1 = Treat any byte that matches the CHPIGN<7:0> bits as a “don’t care” when pattern matching is enabled
0 = Disable this feature
bit 12
Unimplemented: Read as ‘0’
bit 11
CHPATLEN: Pattern Length bit
1 = 2 byte length
0 = 1 byte length
bit 10-9
Unimplemented: Read as ‘0’
bit 8
CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7
CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit 5
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
DS60001191F-page 178
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-7:
DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED)
bit 4
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3
Unimplemented: Read as ‘0’
bit 2
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0
CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 179
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-8:
Bit
Range
31:24
23:16
DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ<7:0>
15:8
R/W-1
CHSIRQ<7:0>(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
bit 15-8
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
bit 2-0
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1:
See Table 7-2: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
bit 7
bit 6
bit 5
bit 4
bit 3
DS60001191F-page 180
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-9:
Bit
Range
31:24
23:16
15:8
7:0
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21
CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16
CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
 2013-2016 Microchip Technology Inc.
DS60001191F-page 181
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-9:
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5
CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0
CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected 
Either the source or the destination address is invalid.
0 = No interrupt is pending
DS60001191F-page 182
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA<31:24>
23:16
R/W-0
R/W-0
CHSSA<23:16>
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA<15:8>
7:0
R/W-0
CHSSA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHSSA<31:0> Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 10-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA<23:16>
R/W-0
R/W-0
CHDSA<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 183
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ<15:8>
7:0
R/W-0
CHSSIZ<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSSIZ<15:0>: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 10-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ<15:8>
7:0
R/W-0
CHDSIZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHDSIZ<15:0>: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
DS60001191F-page 184
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR<15:8>
7:0
R-0
R-0
CHSPTR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR<15:8>
7:0
R-0
R-0
CHDPTR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHDPTR<15:0>: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
 2013-2016 Microchip Technology Inc.
DS60001191F-page 185
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ<15:8>
7:0
R/W-0
CHCSIZ<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
REGISTER 10-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR<15:8>
7:0
R-0
R-0
CHCPTR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHCPTR<15:0>: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
DS60001191F-page 186
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 10-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT<15:8>
R/W-0
R/W-0
CHPDAT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHPDAT<15:0>: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 187
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 188
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
11.0 HI-SPEED USB WITH ON-THEGO (OTG)
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 51. “HiSpeed USB with On-The-Go (OTG)”
(DS60001232), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
embedded host, device, or OTG implementation with a
minimum of external components.
The module supports Hi-Speed, Full-Speed, or LowSpeed in any of the operating modes. This module in
Host mode is intended for use as an embedded host
and therefore does not implement a UHCI or OHCI
controller.
The USB module consists of the RAM controller,
packet encode/decode, UTM synchronization, endpoint control, a dedicated USB DMA controller, pull-up
and pull-down resistors, and the register interface. A
block diagram of the PIC32 USB OTG module is
presented in Figure 11-1.
Note:
To avoid cache coherency problems on
devices with L1 cache, USB buffers must
only be allocated or accessed from the
KSEG1 segment.
 2013-2016 Microchip Technology Inc.
The USB module includes the following features:
• USB Hi-Speed, Full-Speed, and Low-Speed
support for host and device
• USB OTG support with one or more Hi-Speed,
Full-Speed, or Low-Speed device
• Integrated signaling resistors
• Integrated analog comparators for VBUS
monitoring
• Integrated USB transceiver
• Transaction handshaking performed by hardware
• Integrated 8-channel DMA to access system RAM
and Flash
• Seven transmit endpoints and seven receive
endpoints, in addition to Endpoint 0
• Session Request Protocol (SRP) and Host
Negotiation Protocol (HNP) support
• Suspend and resume signaling support
• Dynamic FIFO sizing
• Integrated RAM for the FIFOs, eliminating the
need for system RAM for the FIFOs
• Link power management support
Note 1: The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not
limited to, USB Implementers Forum, Inc.
(also referred to as USB-IF). The user is
fully responsible for investigating and
satisfying any applicable licensing
obligations.
2: If the USB module is used, the Primary
Oscillator (POSC) is limited to either
12 MHz or 24 MHz.
DS60001191F-page 189
PIC32MZ EC FAMILY USB INTERFACE DIAGRAM
USBCLK
POSC
(12 MHz or 24 MHz only)
USB PLL
UPLLEN
UPLLFSEL
Endpoint Control
EP0
Control
Host
EPO
Control
Function
DMA
Requests
Transmit
EP1 - EP7
Control
Combine Endpoints
Receive
Host
Transaction
Scheduler
Interrupt
Control
Interrupts
EP Reg
Decoder
Common
Regs
D+
UTM
Synchronization
Packet
Encode/Decode
D-
Data Sync
Packet Encode
HS Negotiation
Packet Decode
HNP/SRP
CRC Gen/Check
USBID
VUSB3V3
 2013-2016 Microchip Technology Inc.
VBUS
USB 2.0
HS PHY
RAM Controller
RX
Buff
RX
Buff
FIFO
Decoder
TX
Buff
TX
Buff
Cycle Control
Timers
Cycle
Control
Link Power
Management
RAM
System Bus
Slave mode
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 190
FIGURE 11-1:
USB OTG Control Registers
USB REGISTER MAP
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
EP7TXIF
EP6TXIF
EP5TXIF
EP4TXIF
EP3TXIF
EP2TXIF
EP1TXIF
EP0IF
ISOUPD(1)
SOFT
CONN(1)
—(2)
—(2)
—(2)
—(2)
—(2)
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
VBUSIE
SOFIE
15:0
—
31:16
3000 USBCSR0
3004 USBCSR1
3008 USBCSR2
300C USBCSR3
15:0
31/15
31:16 FORCEHST
15:0
—
HSEN
HSMODE
SESSRQIE DISCONIE CONNIE
—
—
FIFOACC
—
FORCEFS FORCEHS
—
—
—
RESET
—
—
—
15:0
—
—
—
31:16
USB
3018
IE0CSR2(3) 15:0
—
—
—
—
—
—
—
31:16
USB
301C
IE0CSR3(3) 15:0
MPRXEN
MPTXEN
BIGEND
HBRXEN
—
—
—
—
31:16 AUTOSET
USB
3010
IENCSR0(4)
MODE
—
15:0
—
—
—
EP7TXIE
EP6TXIE
EP5TXIE
EP4TXIE
EP3TXIE
EP2TXIE
EP1TXIE
EP0IE
00FF
—
—
—
EP7RXIF
EP6RXIF
EP5RXIF
EP4RXIF
EP3RXIF
EP2RXIF
EP1RXIF
—
0000
RESETIE
RESUMEIE
SUSPIE
VBUSIF
SESSREQIF
DISCONIF
CONNIF
SOFIF
RESETIF
EP3RXIE
EP2RXIE
—
2000
—(2)
—(2)
—
—
—
EP7RXIE
EP6RXIE
EP5RXIE
EP4RXIE
TESTJ
NAK
—
—
—
—
—
—
—(1)
—(1)
DATA
TGGL(2)
—
FLSHFIFO
—
—
—
—
—
FRC
DATTG
31:16 AUTOCLR
USB
3014
IENCSR1(4)
AUTORQ
15:0
(2)
DMA
REQEN
—
—
DMA
REQMD
SEND
STALL(1)
SETUP
END(1)
DATAEND(1)
SENT
STALL(1)
NAK
TMOUT(2)
STATPKT(2)
REQPKT(2)
ERROR(2)
SETUP
PKT(2)
RXSTALL(2)
—
—
—
—
—
SPEED<1:0>(2)
—
—
—
0000
RXPKT
RDY
—
—
—
0000
—
—
—
0000
0000
0000
—
—
—
—
—
—
—
—
xx00
—
—
—
—
—
—
—
0000
SENT
STALL(1)
SEND
STALL(1)
FIFONE
RXSTALL(2)
SETUPPKT(2)
TXPKT
RDY
—
—
—(1)
—(1)
INCOMP
TX(1)
DATA
TGGL(2)
NAK
TMOUT(2)
CLRDT
FLUSH
UNDER
RUN(1)
ERROR(2)
(2)
PIDERR
DMA
REQMD
—(1)
—(1)
DATA
TWEN(2)
DATA
TGGL(2)
INCOM
PRX
0000
SENTSTALL(1) SENDSTALL(1)
CLRDT
RXSTALL
(2)
REQPKT
(2)
DATAERR(1) OVERRUN(1)
FLUSH
DERRNAKT(1)
(2)
ERROR
FIFOFULL
0000
RXPKT
RDY 0000
RXMAXP<10:0>
TXINTERV<7:0>(2)
SPEED<1:0>(2)
—
0000
PROTOCOL<1:0>
TEP<3:0>
0000
RXCNT<13:0>
RXFIFOSZ<3:0>
TXFIFOSZ<3:0>
DS60001191F-page 191
RXINTERV<7:0>
—
—
SPEED<1:0>
0000
0000
TXMAXP<10:0>
DISNYET(1)
0000
TXPKT
RDY
RXCNT<6:0>
—
DTWREN(2)
00FE
0000
SVCRPR(1)
MULT<4:0>
—
EP1RXIE
ENDPOINT<3:0>
SVC
SETEND(1)
—
HBTXEN DYNFIFOS SOFTCONE UTMIDWID
—
RESUMEIF SUSPIF 0600
RFRMNUM<10:0>
NAKLIM<4:0>(2)
DMA
REQEN
—(2)
TESTK
—
—
—(2)
—
MULT<4:0>
ISO(1)
31:16
USB
301C
IENCSR3(1,3) 15:0
SUSPEN
DISPING(2) DTWREN(2)
ISO(1)
31:16
USB
3018
IENCSR2(4) 15:0
SUSP
MODE
RESUME
—
31:16
USB
3010
IE0CSR0(3)
0000
FUNC<6:0>(1)
PACKET
—(1)
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF8E_#)
TABLE 11-1:
0000
—
—
PROTOCOL<1:0>
—
—
TEP<3:0>
—
—
0000
0000
3020
USB
FIFO0
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
3024
USB
FIFO1
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
Legend:
Note
1:
2:
3:
4:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
11.1
USB REGISTER MAP (CONTINUED)
Register
Name
Bit Range
3028
USB
FIFO2
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
302C
USB
FIFO3
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
3030
USB
FIFO4
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
3034
USB
FIFO5
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
3038
USB
FIFO6
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
0000
303C
USB
FIFO7
31:16
DATA<31:16>
0000
15:0
DATA<15:0>
3060 USBOTG
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
RXDPB
15:0
—
—
—
—
26/10
25/9
24/8
23/7
RXFIFOSZ<3:0>
—
—
TXEDMA
RXEDMA
22/6
21/5
—
—
BDEV
FSDEV
LSDEV
USB
FIFOA
31:16
—
—
—
RXFIFOAD<12:0>
15:0
—
—
—
TXFIFOAD<12:0>
306C
USB
HWVER
31:16
—
—
—
15:0
RC
3078
USB
INFO
31:16
31:16
—
—
—
—
VERMAJOR<4:0>
—
—
—
15:0
RAMBITS<3:0>
—
 2013-2016 Microchip Technology Inc.
3080
—
15:0
—
—
—
NRSTX
3084
USB
E0RXA
31:16
—
15:0
—
3088
USB
E1TXA
31:16
—
15:0
—
308C
USB
E1RXA
31:16
—
15:0
—
3090
USB
E2TXA
31:16
—
15:0
—
3094
USB
E2RXA
31:16
—
15:0
—
3098
USB
E3TXA
31:16
—
15:0
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
TXHUBPRT<6:0>
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
TXHUBPRT<6:0>
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
TXHUBPRT<6:0>
—
—
—
16/0
TXDPB
TXFIFOSZ<3:0>
VBUS<1:0>
0000
HOSTMODE HOSTREQ SESSION 0080
0000
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
—
0000
0800
WTCON<3:0>
WTID<3:0>
3C5C
RXENDPTS<3:0>
TXENDPTS<3:0>
8C77
NRST
TXHUBPRT<6:0>
—
17/1
0000
FSEOF<7:0>
31:16
18/2
VERMINOR<9:0>
DMACHANS<3:0>
USB
E0TXA
Legend:
Note
1:
2:
3:
4:
—
VPLEN<7:0>
15:0
USB
307C
EOFRST
—
19/3
0000
—
3064
—
20/4
All Resets
Virtual Address
(BF8E_#)
Bits
LSEOF<7:0>
0072
HSEOF<7:0>
7780
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
—
—
—
—
—
0000
—
—
—
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 192
TABLE 11-1:
USB REGISTER MAP (CONTINUED)
Bit Range
309C
USB
E3RXA
31:16
—
15:0
—
30A0
US
BE4TXA
31:16
—
15:0
—
30A4
USB
E4RXA
31:16
—
15:0
—
30A8
USB
E5TXA
31:16
—
15:0
—
30AC
USB
E5RXA
31:16
—
15:0
—
30B0
USB
E6TXA
31:16
—
15:0
—
30B4
USB
E6RXA
31:16
—
15:0
—
30B8
USB
E7TXA
31:16
—
15:0
—
30BC
USB
E7RXA
31:16
—
15:0
—
3100
USB
E0CSR0
31:16
3108
USB
E0CSR2
31:16
USB
310C
E0CSR3
31:16
3110
USB
E1CSR0
31:16
3114
USB
E1CSR1
31:16
3118
USB
E1CSR2
31:16
311C
USB
E1CSR3
31:16
3120
USB
E2CSR0
31:16
3124
USB
E2CSR1
31:16
Legend:
Note
1:
2:
3:
4:
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
31/15
30/14
29/13
28/12
—
—
—
27/11
26/10
25/9
24/8
—
—
—
RXHUBPRT<6:0>
—
TXHUBPRT<6:0>
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
TXHUBPRT<6:0>
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
TXHUBPRT<6:0>
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
TXHUBPRT<6:0>
—
—
—
—
—
—
—
RXHUBPRT<6:0>
—
—
—
—
—
—
—
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name
DS60001191F-page 193
Virtual Address
(BF8E_#)
Bits
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
MULTTRAN
TXHUBADD<6:0>
0000
—
TXFADDR<6:0>
0000
MULTTRAN
RXHUBADD<6:0>
0000
—
RXFADDR<6:0>
0000
Indexed by the same bits in USBIE0CSR0
0000
0000
Indexed by the same bits in USBIE0CSR2
Indexed by the same bits in USBIE0CSR3
0000
0000
0000
0000
Indexed by the same bits in USBIE1CSR0
0000
0000
Indexed by the same bits in USBIE1CSR1
Indexed by the same bits in USBIE1CSR2
0000
0000
0000
0000
Indexed by the same bits in USBIE1CSR3
0000
0000
Indexed by the same bits in USBIE2CSR0
Indexed by the same bits in USBIE2CSR1
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
0000
0000
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 11-1:
USB REGISTER MAP (CONTINUED)
Bit Range
3128
USB
E2CSR2
31:16
USB
312C
E2CSR3
31:16
3130
USB
E3CSR0
31:16
3134
USB
E3CSR1
31:16
3138
USB
E3CSR2
31:16
USB
313C
E3CSR3
31:16
3140
USB
E4CSR0
31:16
3144
USB
E4CSR1
31:16
3148
USB
E4CSR2
31:16
USB
314C
E4CSR3
31:16
3150
USB
E5CSR0
31:16
3154
USB
E5CSR1
31:16
3158
USB
E5CSR2
31:16
USB
315C
E5CSR3
31:16
3160
USB
E6CSR0
31:16
3164
USB
E6CSR1
31:16
3168
USB
E6CSR2
31:16
USB
316C
E6CSR3
31:16
Legend:
Note
1:
2:
3:
4:
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
Indexed by the same bits in USBIE2CSR2
Indexed by the same bits in USBIE2CSR3
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name
 2013-2016 Microchip Technology Inc.
Virtual Address
(BF8E_#)
Bits
0000
0000
0000
0000
Indexed by the same bits in USBIE3CSR0
0000
0000
Indexed by the same bits in USBIE3CSR1
Indexed by the same bits in USBIE3CSR2
0000
0000
0000
0000
Indexed by the same bits in USBIE3CSR3
0000
0000
Indexed by the same bits in USBIE4CSR0
Indexed by the same bits in USBIE4CSR1
0000
0000
0000
0000
Indexed by the same bits in USBIE4CSR2
0000
0000
Indexed by the same bits in USBIE4CSR3
0000
0000
Indexed by the same bits in USBIE5CSR0
Indexed by the same bits in USBIE5CSR1
0000
0000
0000
0000
Indexed by the same bits in USBIE5CSR2
0000
0000
Indexed by the same bits in USBIE5CSR3
Indexed by the same bits in USBIE6CSR0
0000
0000
0000
0000
Indexed by the same bits in USBIE6CSR1
0000
0000
Indexed by the same bits in USBIE6CSR2
Indexed by the same bits in USBIE6CSR3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
0000
0000
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 194
TABLE 11-1:
USB REGISTER MAP (CONTINUED)
Bit Range
3170
USB
E7CSR0
31:16
3174
USB
E7CSR1
31:16
3178
USB
E7CSR2
31:16
USB
317C
E7CSR3
31:16
3200
USB
DMAINT
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
DMA8IF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
3204
USB
DMA1C
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
3208
USB
DMA1A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
320C
USB
DMA1N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3214
USB
DMA2C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3218
USB
DMA2A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
321C
USB
DMA2N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3224
USB
DMA3C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3228
USB
DMA3A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
322C
USB
DMA3N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3234
USB
DMA4C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3238
USB
DMA4A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
323C
USB
DMA4N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3244
USB
DMA5C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
Legend:
Note
1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0000
Indexed by the same bits in USBIE7CSR0
15:0
0000
0000
Indexed by the same bits in USBIE7CSR1
15:0
All Resets
Register
Name
DS60001191F-page 195
Virtual Address
(BF8E_#)
Bits
0000
0000
Indexed by the same bits in USBIE7CSR2
15:0
0000
0000
Indexed by the same bits in USBIE7CSR3
15:0
DMABRSTM<1:0>
—
—
DMABRSTM<1:0>
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
—
—
—
DMADIR
—
0000
DMAEN 0000
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
0000
—
—
—
DMAEP<3:0>
—
—
DMAMODE
0000
—
DMAERR
DMAERR
—
DMAEP<3:0>
—
—
—
DMAEP<3:0>
—
—
DMAIE
0000
DMA1IF 0000
0000
—
DMAERR
—
DMABRSTM<1:0>
DMAEP<3:0>
DMAERR
—
DMABRSTM<1:0>
—
—
—
DMABRSTM<1:0>
—
DMAERR
0000
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
0000
—
—
DMAEP<3:0>
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 11-1:
USB REGISTER MAP (CONTINUED)
Bit Range
3248
USB
DMA5A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
324C
USB
DMA5N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3254
USB
DMA6C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3258
USB
DMA6A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
325C
USB
DMA6N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3264
USB
DMA7C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3268
USB
DMA7A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
326C
USB
DMA7N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3274
USB
DMA8C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3278
USB
DMA8A
31:16
DMAADDR<31:16>
0000
15:0
DMAADDR<15:0>
0000
327C
USB
DMA8N
31:16
DMACOUNT<31:16>
0000
15:0
DMACOUNT<15:0>
3304
USB
E1RPC
31:16
3308
USB
E2RPC
31:16
330C
USB
E3RPC
31:16
3310
USB
E4RPC
31:16
3314
USB
E5RPC
31:16
3318
USB
E6RPC
31:16
331C
USB
E7RPC
31:16
Legend:
Note
1:
2:
3:
4:
31/15
—
30/14
—
29/13
—
28/12
—
27/11
—
26/10
—
25/9
—
DMABRSTM<1:0>
—
23/7
—
22/6
—
15:0
—
—
—
—
—
DMAEP<3:0>
—
18/2
17/1
16/0
—
—
—
DMAIE
DMAMODE
DMADIR
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
—
—
—
—
—
—
—
15:0
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
—
—
—
—
—
—
—
15:0
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
—
—
—
—
—
—
—
—
—
RQPKTCNT<15:0>
0000
0000
0000
0000
RQPKTCNT<15:0>
—
0000
0000
RQPKTCNT<15:0>
—
0000
0000
RQPKTCNT<15:0>
—
0000
0000
RQPKTCNT<15:0>
—
0000
DMAEN 0000
RQPKTCNT<15:0>
—
0000
DMAEN 0000
RQPKTCNT<15:0>
—
0000
DMAEN 0000
0000
—
DMAERR
—
—
DMAEP<3:0>
—
19/3
0000
—
DMAERR
—
20/4
DMAEP<3:0>
—
—
21/5
0000
—
DMAERR
—
DMABRSTM<1:0>
—
—
—
DMABRSTM<1:0>
—
24/8
All Resets
Register
Name
 2013-2016 Microchip Technology Inc.
Virtual Address
(BF8E_#)
Bits
0000
0000
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 196
TABLE 11-1:
USB REGISTER MAP (CONTINUED)
Register
Name
Bit Range
3340
USB
DPBFD
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
—
—
—
EP7TXD
EP6TXD
EP5TXD
EP4TXD
EP3TXD
15:0
—
—
—
—
—
—
—
—
EP7RXD
EP6RXD
EP5RXD
EP4RXD
EP3RXD
31:16
USB
3344
TMCON1 15:0
31:16
USB
3348
TMCON2 15:0
3360
USB
LPMR1
31:16
3364
USB
LMPR2
Legend:
Note
1:
2:
3:
4:
15:0
22/6
21/5
20/4
19/3
18/2
17/1
16/0
EP2TXD
EP1TXD
—
0000
EP2RXD
EP1RXD
—
0000
THHSRTN<15:0>
05E6
TUCH<15:0>
4074
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LPM
ERRIE
LPM
RESIE
—
15:0
31:16
23/7
ENDPOINT<3:0>
—
—
—
—
—
LPMACKIE LPMNYIE
LPMSTIE
LPMTOIE
—
—
—
RMTWAK
—
—
—
—
LPMFADDR<6:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
—
—
—
—
—
—
—
—
LPMERR(1)
—(2)
—
—
THSBT<3:0>
LPMNAK(1)
—(2)
—
LPMEN<1:0>
—(2)
HIRD<3:0>
—
All Resets
Virtual Address
(BF8E_#)
Bits
—(2)
0000
0000
LPMRES LPMXMT
LNKSTATE<3:0>
0000
0000
0000
—
—
—
—
—
LPMRES
LPMNC
LPMACK
LPMNY
LPMST
0000
0000
0000
DS60001191F-page 197
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 11-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-1:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR0: USB CONTROL STATUS REGISTER 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
EP7TXIF
EP6TXIF
EP5TXIF
EP4TXIF
EP3TXIF
EP2TXIF
EP1TXIF
EP0IF
R/W-0
R/W-0
R/W-1
R-0, HS
R-0
R/W-0
R-0, HC
R/W-0
ISOUPD
SOFTCONN
HSEN
HSMODE
RESET
RESUME
SUSPMODE
SUSPEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
U-0
R/W-0
—
FUNC<6:0>
—
—
—
—
Legend:
HS = Hardware Settable HC = Hardware Clearable
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-17 EP7TXIF:EP1TXIF: Endpoint ‘n’ TX Interrupt Flag bit
1 = Endpoint has a transmit interrupt to be serviced
0 = No interrupt event
bit 16
EP0IF: Endpoint 0 Interrupt bit
1 = Endpoint 0 has an interrupt to be serviced
0 = No interrupt event
All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently
from the remaining bits in this register to avoid accidental clearing.
bit 15
ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode)
1 = USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet
0 = No change in behavior
This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is
unimplemented in Host mode.
bit 14
SOFTCONN: Soft Connect/Disconnect Feature Selection bit
1 = The USB D+/D- lines are enabled and active
0 = The USB D+/D- lines are disabled and are tri-stated
This bit is only available in Device mode.
bit 13
HSEN: Hi-Speed Enable bit
1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub
0 = Module only operates in Full-Speed mode
bit 12
HSMODE: Hi-Speed Mode Status bit
1 = Hi-Speed mode successfully negotiated during USB reset
0 = Module is not in Hi-Speed mode
In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when
the RESET bit is cleared.
bit 11
RESET: Module Reset Status bit
1 = Reset signaling is present on the bus
0 = Normal module operation
In Device mode, this bit is read-only. In Host mode, this bit is read/write.
DS60001191F-page 198
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-1:
bit 10
USBCSR0: USB CONTROL STATUS REGISTER 0 (CONTINUED)
RESUME: Resume from Suspend control bit
1 = Generate Resume signaling when the device is in Suspend mode
0 = Stop Resume signaling
In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, the software should clear this bit after 20 ms.
bit 9
SUSPMODE: Suspend Mode status bit
1 = The USB module is in Suspend mode
0 = The USB module is in Normal operations
This bit is read-only in Device mode. In Host mode, it can be set by software, and is cleared by hardware.
bit 8
SUSPEN: Suspend Mode Enable bit
1 = Suspend mode is enabled
0 = Suspend mode is not enabled
bit 7
Unimplemented: Read as ‘0’
bit 6-0
FUNC<6:0>: Device Function Address bits
These bits are only available in Device mode. This field is written with the address received through a
SET_ADDRESS command, which will then be used for decoding the function address in subsequent token
packets.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 199
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-2:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR1: USB CONTROL STATUS REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
EP7TXIE
EP6TXIE
EP5TXIE
EP4TXIE
EP3TXIE
EP2TXIE
EP1TXIE
EP0IE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
U-0
EP7RXIF
EP6RXIF
EP5RXIF
EP4RXIF
EP3RXIF
EP2RXIF
EP1RXIF
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-17 EP7TXIE:EP1TXIE: Endpoint ‘n’ Transmit Interrupt Enable bits
1 = Endpoint Transmit interrupt events are enabled
0 = Endpoint Transmit interrupt events are not enabled
bit 16
EP0IE: Endpoint 0 Interrupt Enable bit
1 = Endpoint 0 interrupt events are enabled
0 = Endpoint 0 interrupt events are not enabled
bit 15-8 Unimplemented: Read as ‘0’
bit 7-1
bit 0
EP7RXIF:EP1RXIF: Endpoint ‘n’ RX Interrupt bit
1 = Endpoint has a receive event to be serviced
0 = No interrupt event
Unimplemented: Read as ‘0’
DS60001191F-page 200
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-3:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR2: USB CONTROL STATUS REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
VBUSERRIE SESSRQIE DISCONIE
R-0, HS
R-0, HS
Bit
28/20/12/4
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
CONNIE
SOFIE
RESETIE
RESUMEIE
SUSPIE
R-0, HS
VBUSERRIF SESSRQIF DISCONIF
Bit
27/19/11/3
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
CONNIF
SOFIF
RESETIF
RESUMEIF
SUSPIF
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
EP7RXIE
EP6RXIE
EP5RXIE
EP4RXIE
EP3RXIE
EP2RXIE
EP1RXIE
—
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
VBUSERRIE: VBUS Error Interrupt Enable bit
1 = VBUS error interrupt is enabled
0 = VBUS error interrupt is disabled
bit 30
SESSRQIE: Session Request Interrupt Enable bit
1 = Session request interrupt is enabled
0 = Session request interrupt is disabled
bit 29
DISCONIE: Device Disconnect Interrupt Enable bit
1 = Device disconnect interrupt is enabled
0 = Device disconnect interrupt is disabled
bit 28
CONNIE: Device Connection Interrupt Enable bit
1 = Device connection interrupt is enabled
0 = Device connection interrupt is disabled
bit 27
SOFIE: Start of Frame Interrupt Enable bit
1 = Start of Frame event interrupt is enabled
0 = Start of Frame event interrupt is disabled
bit 26
RESETIE: Reset/Babble Interrupt Enable bit
1 = Interrupt when reset (Device mode) or Babble (Host mode) is enabled
0 = Reset/Babble interrupt is disabled
bit 25
RESUMEIE: Resume Interrupt Enable bit
1 = Resume signaling interrupt is enabled
0 = Resume signaling interrupt is disabled
bit 24
SUSPIE: Suspend Interrupt Enable bit
1 = Suspend signaling interrupt is enabled
0 = Suspend signaling interrupt is disabled
bit 23
VBUSERRIF: VBUS Error Interrupt bit
1 = VBUS has dropped below the VBUS valid threshold during a session
0 = No interrupt
bit 22
SESSRQIF: Session Request Interrupt bit
1 = Session request signaling has been detected
0 = No session request detected
bit 21
DISCONIF: Device Disconnect Interrupt bit
1 = In Host mode, indicates when a device disconnect is detected. In Device mode, indicates when a
session ends.
0 = No device disconnect detected
bit 20
CONNIF: Device Connection Interrupt bit
1 = In Host mode, indicates when a device connection is detected
0 = No device connection detected
 2013-2016 Microchip Technology Inc.
DS60001191F-page 201
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-3:
USBCSR2: USB CONTROL STATUS REGISTER 2 (CONTINUED)
bit 19
SOFIF: Start of Frame Interrupt bit
1 = A new frame has started
0 = No start of frame detected
bit 18
RESETIF: Reset/Babble Interrupt bit
1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on the
bus.
0 = No reset/babble detected
bit 17
RESUMEIF: Resume Interrupt bit
1 = Resume signaling is detected on the bus while USB module is in Suspend mode
0 = No Resume signaling detected
bit 16
SUSPIF: Suspend Interrupt bit
1 = Suspend signaling is detected on the bus (Device mode)
0 = No suspend signaling detected
bit 15-8
Unimplemented: Read as ‘0’
bit 7-1
EP7RXIE:EP1RXIE: Endpoint ‘n’ Receive Interrupt Enable bit
1 = Receive interrupt is enabled for this endpoint
0 = Receive interrupt is not enabled
bit 0
Unimplemented: Read as ‘0’
DS60001191F-page 202
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-4:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR3: USB CONTROL STATUS REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FORCEHST
FIFOACC
FORCEFS
FORCEHS
PACKET
TESTK
TESTJ
NAK
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
ENDPOINT<3:0>
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RFRMUM<10:8>
R-0
R-0
R-0
RFRMNUM<7:0>
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FORCEHST: Test Mode Force Host Select bit
1 = Forces USB module into Host mode, regardless of whether it is connected to any peripheral
0 = Normal operation
bit 30
FIFOACC: Test Mode Endpoint 0 FIFO Transfer Force bit
1 = Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO
0 = No transfer
bit 29
FORCEFS: Test mode Force Full-Speed Mode Select bit
This bit is only active if FORCEHST = 1.
1 = Forces USB module into Full-Speed mode. Undefined behavior if FORCEHS = 1.
0 = If FORCEHS = 0, places USB module into Low-Speed mode.
bit 28
FORCEHS: Test mode Force Hi-Speed Mode Select bit
This bit is only active if FORCEHST = 1.
1 = Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1.
0 = If FORCEFS = 0, places USB module into Low-Speed mode.
bit 27
PACKET: Test_Packet Test Mode Select bit
This bit is only active if module is in Hi-Speed mode.
1 = The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded
into the Endpoint 0 FIFO before the test mode is entered.
0 = Normal operation
bit 26
TESTK: Test_K Test Mode Select bit
1 = Enters Test_K test mode. The USB module transmits a continuous K on the bus.
0 = Normal operation
This bit is only active if the USB module is in Hi-Speed mode.
bit 25
TESTJ: Test_J Test Mode Select bit
1 = Enters Test_J test mode. The USB module transmits a continuous J on the bus.
0 = Normal operation
This bit is only active if the USB module is in Hi-Speed mode.
bit 24
NAK: Test_SE0_NAK Test Mode Select bit
1 = Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid
IN token with a NAK
0 = Normal operation
This mode is only active if module is in Hi-Speed mode.
bit 23-20 Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 203
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-4:
USBCSR3: USB CONTROL STATUS REGISTER 3 (CONTINUED)
bit 19-16 ENDPOINT<3:0>: Endpoint Registers Select bits
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Endpoint 7
•
•
•
0000 = Endpoint 0
These bits select which endpoint registers are accessed through addresses 3010-301F.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
RFRMNUM<10:0>: Last Received Frame Number bits
DS60001191F-page 204
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-5:
Bit
Range
31:24
23:16
15:8
7:0
USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 0)
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0, HC
R/W-0
R/W-0, HC
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/C-0, HS
SVCSETEND SVCRPR SENDSTALL SETUPEND
—
—
—
DISPING
DTWREN
DATATGGL
R/W-0, HS
R-0, HS
R-0
DATAEND
SENTSTALL
NAKTMOUT
STATPKT
REQPKT
ERROR
SETUPPKT
RXSTALL
U-0
U-0
U-0
U-0
U-0
U-0
FLSHFIFO
R-0
TXPKTRDY RXPKTRDY
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27
DISPING: Disable Ping tokens control bit (Host mode)
1 = USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer
0 = Ping tokens are issued
bit 26
DTWREN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared.
0 = Disable data toggle write
bit 25
DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the Endpoint 0 data toggle.
If DTWREN = 1, this bit is writable with the desired setting.
If DTWREN = 0, this bit is read-only.
bit 24
FLSHFIFO: Flush FIFO Control bit
1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and
the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should
only be used when TXPKTRDY/RXPKTRDY = 1.
0 = No Flush operation
bit 23
SVCSETEND: Clear SETUPEND Control bit (Device mode)
1 = Clear the SETUPEND bit in this register. This bit is automatically cleared.
0 = Do not clear
NAKTMOUT: NAK Time-out Control bit (Host mode)
1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the
NAKLIM<4:0> bits (USBICSR<28:24>)
0 = Allow the endpoint to continue
bit 22
SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode)
1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared.
0 = Do not clear
STATPKT: Status Stage Transaction Control bit (Host mode)
1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction
0 = Do not perform a status stage transaction
 2013-2016 Microchip Technology Inc.
DS60001191F-page 205
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-5:
bit 21
USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 0) (CONTINUED)
SENDSTALL: Send Stall Control bit (Device mode)
1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared.
0 = Do not send STALL handshake.
REQPKT: IN transaction Request Control bit (Host mode)
1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set.
0 = Do not request an IN transaction
bit 20
SETUPEND: Early Control Transaction End Status bit (Device mode)
1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and
the FIFO flushed at this time.
0 = Normal operation
This bit is cleared by writing a ‘1’ to the SVCSETEND bit in this register.
ERROR: No Response Error Status bit (Host mode)
1 = Three attempts have been made to perform a transaction with no response from the peripheral. An interrupt is generated.
0 = Clear this flag. Software must write a ‘0’ to this bit to clear it.
bit 19
DATAEND: End of Data Control bit (Device mode)
The software sets this bit when:
• Setting TXPKTRDY for the last data packet
• Clearing RXPKTRDY after unloading the last data packet
• Setting TXPKTRDY for a zero length data packet
Hardware clears this bit.
SETUPPKT: Send a SETUP token Control bit (Host mode)
1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an
OUT token for the transaction
0 = Normal OUT token operation
Setting this bit also clears the Data Toggle.
bit 18
SENTSTALL: STALL sent status bit (Device mode)
1 = STALL handshake has been transmitted
0 = Software clear of bit
RXSTALL: STALL handshake received Status bit (Host mode)
1 = STALL handshake was received
0 = Software clear of bit
bit 17
TXPKTRDY: TX Packet Ready Control bit
1 = Data packet has been loaded into the FIFO. It is cleared automatically.
0 = No data packet is ready for transmit
bit 16
RXPKTRDY: RX Packet Ready Status bit
1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set.
0 = No data packet has been received
This bit is cleared by setting the SVCRPR bit.
bit 15-0
Unimplemented: Read as ‘0’
DS60001191F-page 206
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-6:
Bit
Range
31:24
23:16
15:8
7:0
USBIE0CSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2
(ENDPOINT 0)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
SPEED<1:0>
U-0
U-0
NAKLIM<4:0>
—
—
—
—
—
—
—
—
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
Legend:
R = Readable bit
-n = Value at POR
RXCNT<6:0>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 NAKLIM<4:0>: Endpoint 0 NAK Limit bits
The number of frames/microframes (Hi-Speed transfers) after which Endpoint 0 should time-out on receiving
a stream of NAK responses.
bit 23-22 SPEED<1:0>: Operating Speed Control bits
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 21-7 Unimplemented: Read as ‘0’
bit 6-0
RXCNT<6:0>: Receive Count bits
The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of
the FIFO change and is only valid while RXPKTRDY is set.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 207
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-7:
Bit
Range
31:24
23:16
15:8
7:0
USBIE0CSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3
(ENDPOINT 0)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-0
R-x
R-x
R-x
R-1
R-0
MPRXEN
MPTXEN
BIGEND
HBRXEN
HBTXEN
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
DYNFIFOS SOFTCONE UTMIDWID
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
MPRXEN: Automatic Amalgamation Option bit
1 = Automatic amalgamation of bulk packets is done
0 = No automatic amalgamation
bit 30
MPTXEN: Automatic Splitting Option bit
1 = Automatic splitting of bulk packets is done
0 = No automatic splitting
bit 29
BIGEND: Byte Ordering Option bit
1 = Big Endian ordering
0 = Little Endian ordering
bit 28
HBRXEN: High-bandwidth RX ISO Option bit
1 = High-bandwidth RX ISO endpoint support is selected
0 = No High-bandwidth RX ISO support
bit 27
HBTXEN: High-bandwidth TX ISO Option bit
1 = High-bandwidth TX ISO endpoint support is selected
0 = No High-bandwidth TX ISO support
bit 26
DYNFIFOS: Dynamic FIFO Sizing Option bit
1 = Dynamic FIFO sizing is supported
0 = No Dynamic FIFO sizing
bit 25
SOFTCONE: Soft Connect/Disconnect Option bit
1 = Soft Connect/Disconnect is supported
0 = Soft Connect/Disconnect is not supported
bit 24
UTMIDWID: UTMI+ Data Width Option bit
Always ‘0’, indicating 8-bit UTMI+ data width
bit 23-0 Unimplemented: Read as ‘0’
DS60001191F-page 208
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-8:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUTOSET
ISO
—
MODE
R/W-0, HS
R/W-0, HC
R/W-0, HS
INCOMPTX
NAKTMOUT
CLRDT
R/W-0
R/W-0
bit 30
bit 29
bit 28
bit 27
bit 26
bit 25
bit 24
—
DMAREQEN FRCDATTG DMAREQMD
DATAWEN
R/W-0
SENTSTALL SENDSTALL
RXSTALL SETUPPKT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DATATGGL
R/W-0
R/W-0, HS
R/W-0
R/W-0, HC
FLUSH
UNDERRUN
ERROR
FIFONE
TXPKTRDY
R/W-0
R/W-0
R/W-0
R/W-0
MULT<4:0>
TXMAXP<10:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXMAXP<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31
USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 1-7)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
AUTOSET: Auto Set Control bit
1 = TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded
into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have
to be set manually.
0 = TXPKTRDY must be set manually for all packet sizes
ISO: Isochronous TX Endpoint Enable bit (Device mode)
1 = Enables the endpoint for Isochronous transfers
0 = Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers.
This bit only has an effect in Device mode. In Host mode, it always returns ‘0’.
MODE: Endpoint Direction Control bit
1 = Endpoint is TX
0 = Endpoint is RX
This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions.
DMAREQEN: Endpoint DMA Request Enable bit
1 = DMA requests are enabled for this endpoint
0 = DMA requests are disabled for this endpoint
FRCDATTG: Force Endpoint Data Toggle Control bit
1 = Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received.
0 = No forced behavior
DMAREQMD: Endpoint DMA Request Mode Control bit
1 = DMA Request Mode 1
0 = DMA Request Mode 0
This bit must not be cleared either before or in the same cycle as the above DMAREQEN bit is cleared.
DATAWEN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the TX Endpoint data toggle (DATATGGL) to be written
0 = Disables writing the DATATGGL bit
DATATGGL: Data Toggle Control bit (Host mode)
When read, this bit indicates the current state of the TX Endpoint data toggle. If DATAWEN = 1, this bit may
be written with the required setting of the data toggle. If DATAWEN = 0, any value written to this bit is ignored.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 209
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-8:
bit 23
USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 1-7) (CONTINUED)
INCOMPTX: Incomplete TX Status bit (Device mode)
1 = For high-bandwidth Isochronous endpoint, a large packet has been split into two or three packets for
transmission but insufficient IN tokens have been received to send all the parts
0 = Normal operation
In anything other than isochronous transfers, this bit will always return ‘0’.
bit 22
bit 21
bit 20
NAKTMOUT: NAK Time-out status bit (Host mode)
1 = TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting
0 = Written by software to clear this bit
CLRDT: Clear Data Toggle Control bit
1 = Resets the endpoint data toggle to ‘0’
0 = Do not clear the data toggle
SENTSTALL: STALL handshake transmission status bit (Device mode)
1 = STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit is cleared.
0 = Written by software to clear this bit
RXSTALL: STALL receipt bit (Host mode)
1 = STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed
and the TXPKTRDY bit is cleared.
0 = Written by software to clear this bit
SENDSTALL: STALL handshake transmission control bit (Device mode)
1 = Issue a STALL handshake to an IN token
0 = Terminate stall condition
This bit has no effect when the endpoint is being used for Isochronous transfers.
SETUPPKT: Definition bit (Host mode)
1 = When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token
for the transaction. This also clears the Data Toggle.
bit 19
bit 18
bit 17
bit 16
0 = Normal OUT token for the transaction
FLUSH: FIFO Flush control bit
1 = Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, TXPKTRDY is cleared and
an interrupt is generated.
0 = Do not flush the FIFO
UNDERRUN: Underrun status bit (Device mode)
1 = An IN token has been received when TXPKTRDY is not set.
0 = Written by software to clear this bit.
ERROR: Handshake failure status bit (Host mode)
1 = Three attempts have been made to send a packet and no handshake packet has been received
0 = Written by software to clear this bit.
FIFONE: FIFO Not Empty status bit
1 = There is at least 1 packet in the TX FIFO
0 = TX FIFO is empty
TXPKTRDY: TX Packet Ready Control bit
The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data
packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO.
DS60001191F-page 210
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-8:
USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 1-7) (CONTINUED)
bit 15-11 MULT<4:0>: Multiplier Control bits
For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1
for the payload size.
For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload
into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required
to be an exact multiple of the payload specified by TXMAXP.
For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies
the maximum number of such transactions that can take place in a single microframe.
bit 10-0 TXMAXP<10:0>: Maximum TX Payload per transaction Control bits
This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the
constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in
Full-Speed and Hi-Speed operations.
TXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 211
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-9:
USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7)
Bit
Bit
Range 31/23/15/7
R/W-0
31:24
15:8
7:0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0, HC
R-0
R/W-0
—
—
ISO
AUTOCLR
AUTORQ
R/W-0, HC
23:16
Bit
30/22/14/6
R/W-0, HS
DMAREQEN
R/W-0
SENTSTALL SENDSTALL
CLRDT
RXSTALL
REQPKT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DISNYET
PIDERR
DMAREQMD
R/W-0, HC
DATATWEN DATATGGL
R-0, HS
R/W-0, HS
DATAERR
OVERRUN
ERROR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MULT<4:0>
R/W-0
R-0, HSC
DERRNAKT
FLUSH
INCOMPRX
R/W-0, HS
FIFOFULL RXPKTRDY
R/W-0
R/W-0
RXMAXP<10:8>
R/W-0
R/W-0
RXMAXP<7:0>
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
AUTOCLR: RXPKTRDY Automatic Clear Control bit
1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the
RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be
cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte
chunks regardless of the RXMAXP.
0 = No automatic clearing of RXPKTRDY
This bit should not be set for high-bandwidth Isochronous endpoints.
bit 30
ISO: Isochronous Endpoint Control bit (Device mode)
1 = Enable the RX endpoint for Isochronous transfers
0 = Enable the RX endpoint for Bulk/Interrupt transfers
AUTORQ: Automatic Packet Request Control bit (Host mode)
1 = REQPKT will be automatically set when RXPKTRDY bit is cleared.
0 = No automatic packet request
This bit is automatically cleared when a short packet is received.
bit 29
DMAREQEN: DMA Request Enable Control bit
1 = Enable DMA requests for the RX endpoint.
0 = Disable DMA requests for the RX endpoint.
bit 28
DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode)
1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX
packets are ACKed including at the point at which the FIFO becomes full.
0 = Normal operation.
In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for
all Interrupt endpoints.
PIDERR: PID Error Status bit (Host mode)
1 = In ISO transactions, this indicates a PID error in the received packet.
0 = No error
bit 27
DMAREQMD: DMA Request Mode Selection bit
1 = DMA Request Mode 1
0 = DMA Request Mode 0
DS60001191F-page 212
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-9:
USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7) (CONTINUED)
bit 26
DATATWEN: Data Toggle Write Enable Control bit (Host mode)
1 = DATATGGL can be written
0 = DATATGGL is not writable
bit 25
DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the endpoint data toggle.
If DATATWEN = 1, this bit may be written with the required setting of the data toggle.
If DATATWEN = 0, any value written to this bit is ignored.
bit 24
INCOMPRX: Incomplete Packet Status bit
1 = The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because
parts of the data were not received
0 = Written by then software to clear this bit
In anything other than Isochronous transfer, this bit will always return ‘0’.
bit 23
CLRDT: Clear Data Toggle Control bit
1 = Reset the endpoint data toggle to ‘0’
0 = Leave endpoint data toggle alone
bit 22
SENTSTALL: STALL Handshake Status bit (Device mode)
1 = STALL handshake is transmitted
0 = Written by the software to clear this bit
RXSTALL: STALL Handshake Receive Status bit (Host mode)
1 = A STALL handshake has been received. An interrupt is generated.
0 = Written by the software to clear this bit
bit 21
SENDSTALL: STALL Handshake Control bit (Device mode)
1 = Issue a STALL handshake
0 = Terminate stall condition
REQPKT: IN Transaction Request Control bit (Host mode)
1 = Request an IN transaction.
0 = No request
This bit is cleared when RXPKTRDY is set.
bit 20
FLUSH: Flush FIFO Control bit
1 = Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the
RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is doublebuffered, FLUSH may need to be set twice to completely clear the FIFO.
0 = Normal FIFO operation
This bit is automatically cleared.
bit 19
DATAERR: Data Packet Error Status bit (Device mode)
1 = The data packet has a CRC or bit-stuff error.
0 = No data error
This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns ‘0’.
DERRNAKT: Data Error/NAK Time-out Status bit (Host mode)
1 = The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt
of NAK responses for longer than the time set as the NAK limit.
0 = No data or NAK time-out error
 2013-2016 Microchip Technology Inc.
DS60001191F-page 213
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-9:
bit 18
USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7) (CONTINUED)
OVERRUN: Data Overrun Status bit (Device mode)
1 = An OUT packet cannot be loaded into the RX FIFO.
0 = Written by software to clear this bit
This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
ERROR: No Data Packet Received Status bit (Host mode)
1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt
is generated.
0 = Written by the software to clear this bit.
This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always
returns zero.
bit 17
FIFOFULL: FIFO Full Status bit
1 = No more packets can be loaded into the RX FIFO
0 = The RX FIFO has at least one free space
bit 16
RXPKTRDY: Data Packet Reception Status bit
1 = A data packet has been received. An interrupt is generated.
0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO.
bit 15-11 MULT<4:0>: Multiplier Control bits
For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1
for the payload size.
For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload
into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required
to be an exact multiple of the payload specified by TXMAXP.
For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies
the maximum number of such transactions that can take place in a single microframe.
bit 10-0
RXMAXP<10:0>: Maximum RX Payload Per Transaction Control bits
This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the
constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in
Full-Speed and Hi-Speed operations.
RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.
DS60001191F-page 214
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-10: USBIENCSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2
(ENDPOINT 1-7)
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXINTERV<7:0>
SPEED<1:0>
U-0
U-0
—
—
R-0
R-0
R/W-0
PROTOCOL<1:0>
TEP<3:0>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXCNT<13:8>
R-0
RXCNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable HS = Hardware Settable
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 TXINTERV<7:0>: Endpoint TX Polling Interval/NAK Limit bits (Host mode)
For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving
a stream of NAK responses.
The following table describes the valid values and interpretation for these bits:
Transfer Type
Speed
Valid Values (m)
Low/Full
0x01 to 0xFF
Polling interval is ‘m’ frames.
High
0x01 to 0x10
Polling interval is 2(m-1) frames.
Isochronous
Full or High
0x01 to 0x10
Polling interval is 2(m-1) frames/microframes.
Bulk
Full or High
0x02 to 0x10
NAK limit is 2(m-1) frames/microframes. A
value of ‘0’ or ‘1’ disables the NAK time-out
function.
Interrupt
Interpretation
bit 23-22 SPEED<1:0>: TX Endpoint Operating Speed Control bits (Host mode)
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 21-20 PROTOCOL<1:0>: TX Endpoint Protocol Control bits
11 = Interrupt
10 = Bulk
01 = Isochronous
00 = Control
bit 19-16 TEP<3:0>: TX Target Endpoint Number bits
This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during
device enumeration.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 RXCNT<13:0>: Receive Count bits
The number of received data bytes in the endpoint RX FIFO. The value returned changes as the contents of
the FIFO change and is only valid while RXPKTRDY is set.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 215
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3
(ENDPOINT 1-7)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXFIFOSZ<3:0>
TXFIFOSZ<3:0>
U-0
RXINTERV<7:0>
SPEED<1:0>
Legend:
R = Readable bit
-n = Value at POR
R/W-0
PROTOCOL<1:0>
W = Writable bit
‘1’ = Bit is set
TEP<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 RXFIFOSZ<3:0>: Receive FIFO Size bits
1111 = Reserved
1110 = Reserved
1101 = 8192 bytes
1100 = 4096 bytes
•
•
•
0011 = 8 bytes
0010 = Reserved
0001 = Reserved
0000 = Reserved or endpoint has not been configured
This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic
FIFO sizing is used.
bit 27-24 TXFIFOSZ<3:0>: Transmit FIFO Size bits
1111 = Reserved
1110 = Reserved
1101 = 8192 bytes
1100 = 4096 bytes
•
•
•
0011 = 8 bytes
0010 = Reserved
0001 = Reserved
0000 = Reserved or endpoint has not been configured
This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic
FIFO sizing is used.
bit 23-16 Unimplemented: Read as ‘0’
DS60001191F-page 216
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3
(ENDPOINT 1-7) (CONTINUED)
bit 15-8
RXINTERV<7:0>: Endpoint RX Polling Interval/NAK Limit bits
For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving
a stream of NAK responses.
The following table describes the valid values and meaning for this field:
Transfer Type
Speed
Valid Values (m)
Low/Full
0x01 to 0xFF
Polling interval is ‘m’ frames.
High
0x01 to 0x10
Polling interval is 2(m-1) frames.
Isochronous
Full or High
0x01 to 0x10
Polling interval is 2(m-1) frames/microframes.
Bulk
Full or High
0x02 to 0x10
NAK limit is 2(m-1) frames/microframes. A
value of ‘0’ or ‘1’ disables the NAK time-out
function.
Interrupt
bit 7-6
SPEED<1:0>: RX Endpoint Operating Speed Control bits
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 5-4
PROTOCOL<1:0>: RX Endpoint Protocol Control bits
11 = Interrupt
10 = Bulk
01 = Isochronous
00 = Control
bit 3-0
TEP<3:0>: RX Target Endpoint Number bits
Interpretation
This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during
device enumeration.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 217
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-12: USBFIFOx: USB FIFO DATA REGISTER ‘x’ (‘x’ = 0-7)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA<15:8>
R/W-0
DATA<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R/W-0
DATA<23:16>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DATA<31:0>: USB Transmit/Receive FIFO Data bits
Writes to this register loads data into the TxFIFO for the corresponding endpoint. Reading from this register
unloads data from the RxFIFO for the corresponding endpoint.
Transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the
data accessed is contiguous. However, all transfers associated with one packet must be of the same width
so that data is consistently byte-, word- or double-word aligned. The last transfer may contain fewer bytes
than the previous transfers in order to complete an odd-byte or odd-word transfer.
DS60001191F-page 218
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
RXDPB
U-0
U-0
U-0
R/W-0
—
—
—
TXDPB
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
TXEDMA
RXEDMA
R-1
R-0
R-0
R-0
R-0
R-0
R/W-0, HC
R/W-0
BDEV
FSDEV
LSDEV
RXFIFOSZ<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
TXFIFOSZ<3:0>
VBUS<1:0>
HOSTMODE HOSTREQ
SESSION
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28
RXDPB: RX Endpoint Double-packet Buffering Control bit
1 = Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.
0 = Double-packet buffer is not supported
bit 27-24 RXFIFOSZ<3:0>: RX Endpoint FIFO Packet Size bits
The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth
packets prior to transmission)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes
bit 23-21 Unimplemented: Read as ‘0’
bit 20
TXDPB: TX Endpoint Double-packet Buffering Control bit
1 = Double-packet buffer is supported. This doubles the size set in TXFIFOSZ.
0 = Double-packet buffer is not supported
 2013-2016 Microchip Technology Inc.
DS60001191F-page 219
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)
bit 19-16 TXFIFOSZ<3:0>: TX Endpoint FIFO packet size bits
The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth
packets prior to transmission)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes
bit 15-10 Unimplemented: Read as ‘0’
bit 9
TXEDMA: TX Endpoint DMA Assertion Control bit
1 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an
endpoint. This is Early mode.
0 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an
endpoint. This is Late mode.
bit 8
RXEDMA: RX Endpoint DMA Assertion Control bit
1 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to
an endpoint. This is Early mode.
0 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an
endpoint. This is Late mode.
bit 7
BDEV: USB Device Type bit
1 = USB is operating as a ‘B’ device
0 = USB is operating as an ‘A’ device
bit 6
FSDEV: Full-Speed/Hi-Speed device detection bit (Host mode)
1 = A Full-Speed or Hi-Speed device has been detected being connected to the port
0 = No Full-Speed or Hi-Speed device detected
bit 5
LSDEV: Low-Speed Device Detection bit (Host mode)
1 = A Low-Speed device has been detected being connected to the port
0 = No Low-Speed device detected
bit 4-3
VBUS<1:0>: VBUS Level Detection bits
11 = Above VBUS Valid
10 = Above AValid, below VBUS Valid
01 = Above Session End, below AValid
00 = Below Session End
bit 2
HOSTMODE: Host Mode bit
1 = USB module is acting as a Host
0 = USB module is not acting as a Host
bit 1
HOSTREQ: Host Request Control bit
‘B’ device only:
1 = USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when
Host Negotiation is completed.
0 = Host Negotiation is not taking place
DS60001191F-page 220
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)
bit 0
SESSION: Active Session Control/Status bit
‘A’ device:
1 = Start a session
0 = End a session
‘B’ device:
1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol
0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect
Clearing this bit when the USB module is not suspended will result in undefined behavior.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 221
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-14: USBFIFOA: USB FIFO ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
RXFIFOAD<12:8>
RXFIFOAD<7:0>
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXFIFOAD<12:8>
R/W-0
TXFIFOAD<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-16 RXFIFOAD<12:0>: Receive Endpoint FIFO Address bits
Start address of the endpoint FIFO in units of 8 bytes as follows:
1111111111111 = 0xFFF8
•
•
•
0000000000010 = 0x0010
0000000000001 = 0x0008
0000000000000 = 0x0000
bit 15-13 Unimplemented: Read as ‘0’
bit 12-0 TXFIFOAD<12:0>: Transmit Endpoint FIFO Address bits
Start address of the endpoint FIFO in units of 8 bytes as follows:
1111111111111 = 0xFFF8
•
•
•
0000000000010 = 0x0010
0000000000001 = 0x0008
0000000000000 = 0x0000
DS60001191F-page 222
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-15: USBHWVER: USB HARDWARE VERSION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RC
R-0
VERMAJOR<4:0>
R-0
VERMINOR<9:8>
R-0
R-0
VERMINOR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
RC: Release Candidate bit
1 = USB module was created using a release candidate
0 = USB module was created using a full release
bit 14-10 VERMAJOR<4:0>: USB Module Major Version number bits
This read-only number is the Major version number for the USB module.
bit 9-0
VERMINOR<9:0>: USB Module Minor Version number bits
This read-only number is the Minor version number for the USB module.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 223
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-16: USBINFO: USB INFORMATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
VPLEN<7:0>
R/W-1
WTCON<3:0>
R-1
R-0
R-0
WTID<3:0>
R-0
R-1
R-1
R-1
R-0
R-1
DMACHANS<3:0>
R-0
R-1
R-1
RXENDPTS<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R-0
R-0
RAMBITS<3:0>
R-1
R-1
TXENDPTS<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 VPLEN<7:0>: VBUS pulsing charge length bits
Sets the duration of the VBUS pulsing charge in units of 546.1 µs. (The default setting corresponds to 32.77
ms.)
bit 23-20 WTCON<3:0>: Connect/Disconnect filter control bits
Sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. The default setting
corresponds to 2.667 µs.
bit 19-6
WTID<3:0>: ID delay valid control bits
Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of
4.369ms. The default setting corresponds to 52.43ms.
bit 15-12 DMACHANS<3:0>: DMA Channels bits
These read-only bits provide the number of DMA channels in the USB module. For the PIC32MZ EC family,
this number is 8.
bit 11-8 RAMBITS<3:0>: RAM address bus width bits
These read-only bits provide the width of the RAM address bus. For the PIC32MZ EC family, this number is
12.
bit 7-4
RXENDPTS<3:0>: Included RX Endpoints bits
This read-only register gives the number of RX endpoints in the design. For the PIC32MZ EC family, this
number is 7.
bit 3-0
TXENDPTS<3:0>: Included TX Endpoints bits
These read-only bits provide the number of TX endpoints in the design. For the PIC32MZ EC family, this
number is 7.
DS60001191F-page 224
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-17: USBEOFRST: USB END-OF-FRAME/SOFT RESET CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
NRSTX
NRST
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R.W-0
R/W-1
R/W-0
R.W-1
R/W-1
R/W-1
R.W-0
R/W-0
R/W-0
LSEOF<7:0>
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
FSEOF<7:0>
Legend:
R = Readable bit
-n = Value at POR
R/W-0
HSEOF<7:0>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
NRSTX: Reset of XCLK Domain bit
1 = Reset the XCLK domain, which is clock recovered from the received data by the PHY
0 = Normal operation
bit 24
NRST: Reset of CLK Domain bit
1 = Reset the CLK domain, which is clock recovered from the peripheral bus
0 = Normal operation
bit 23-16 LSEOF<7:0>: Low-Speed EOF bits
These bits set the Low-Speed transaction in units of 1.067 µs (default setting is 121.6 µs) prior to the EOF
to stop new transactions from beginning.
bit 15-8 FSEOF<7:0>: Full-Speed EOF bits
These bits set the Full-Speed transaction in units of 533.3 µs (default setting is 63.46 µs) prior to the EOF
to stop new transactions from beginning.
bit 7-0
HSEOF<7:0>: Hi-Speed EOF bits
These bits set the Hi-Speed transaction in units of 133.3 µs (default setting is 17.07 µs) prior to the EOF to
stop new transactions from beginning.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 225
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-18: USBExTXA: USB ENDPOINT ‘x’ TRANSMIT ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
—
R/W-0
TXHUBPRT<6:0>
MULTTRAN
U-0
R/W-0
TXHUBADD<6:0>
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
Legend:
R = Readable bit
-n = Value at POR
TXFADDR<6:0>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-24 TXHUBPRT<6:0>: TX Hub Port bits (Host mode)
When a low- or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field
records the port number of that USB 2.0 hub.
bit 23
MULTTRAN: TX Hub Multiple Translators bit (Host mode)
1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator
bit 22-16 TXHUBADD<6:0>: TX Hub Address bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these
bits record the address of the USB 2.0 hub.
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
TXFADDR<6:0>: TX Functional Address bits (Host mode)
Specifies the address for the target function that is be accessed through the associated endpoint. It needs
to be defined for each TX endpoint that is used.
DS60001191F-page 226
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-19: USBExRXA: USB ENDPOINT ‘x’ RECEIVE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
—
R/W-0
RXHUBPRT<6:0>
MULTTRAN
U-0
R/W-0
RXHUBADD<6:0>
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
Legend:
R = Readable bit
-n = Value at POR
RXFADDR<6:0>
HC = Hardware Clearable HS = Hardware Settable
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-24 RXHUBPRT<6:0>: RX Hub Port bits (Host mode)
When a low- or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field records
the port number of that USB 2.0 hub.
bit 23
MULTTRAN: RX Hub Multiple Translators bit (Host mode)
1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator
bit 22-16 TXHUBADD<6:0>: RX Hub Address bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these
bits record the address of the USB 2.0 hub.
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
RXFADDR<6:0>: RX Functional Address bits (Host mode)
Specifies the address for the target function that is be accessed through the associated endpoint. It needs to
be defined for each RX endpoint that is used.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 227
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-20: USBDMAINT: USB DMA INTERRUPT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
DMA8IF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
DMAxIF: DMA Channel ‘x’ Interrupt bit
1 = The DMA channel has an interrupt event
0 = No interrupt event
All bits are cleared on a read of the register.
DS60001191F-page 228
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-21: USBDMAxC: USB DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 1-8)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
DMABRSTM<1:0>
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAIE
DMAMODE
DMADIR
DMAEN
DMAEP<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
DMAERR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-9 DMABRSTM<1:0>: DMA Burst Mode Selection bit
11 = Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length
10 = Burst Mode 2: INCR8, INCR4 or unspecified length
01 = Burst Mode 1: INCR4 or unspecified length
00 = Burst Mode 0: Bursts of unspecified length
bit 8
DMAERR: Bus Error bit
1 = A bus error has been observed on the input
0 = The software writes this to clear the error
bit 7-4
DMAEP<3:0>: DMA Endpoint Assignment bits
These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7.
bit 3
DMAIE: DMA Interrupt Enable bit
1 = Interrupt is enabled for this channel
0 = Interrupt is disabled for this channel
bit 2
DMAMODE: DMA Transfer Mode bit
1 = DMA Mode1 Transfers
0 = DMA Mode0 Transfers
bit 1
DMADIR: DMA Transfer Direction bit
1 = DMA Read (TX endpoint)
0 = DMA Write (RX endpoint)
bit 0
DMAEN: DMA Enable bit
1 = Enable the DMA transfer and start the transfer
0 = Disable the DMA transfer
 2013-2016 Microchip Technology Inc.
DS60001191F-page 229
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-22: USBDMAxA: USB DMA CHANNEL ‘x’ MEMORY ADDRESS REGISTER (‘x’ = 1-8)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
DMAADDR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAADDR<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAADDR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAADDR<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DMAADDR<31:0>: DMA Memory Address bits
This register identifies the current memory address of the corresponding DMA channel. The initial memory
address written to this register during initialization must have a value such that its modulo 4 value is equal
to ‘0’. The lower two bits of this register are read only and cannot be set by software. As the DMA transfer
progresses, the memory address will increment as bytes are transferred.
REGISTER 11-23: USBDMAxN: USB DMA CHANNEL ‘x’ COUNT REGISTER (‘X’ = 1-8)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMACOUNT<31:24>
R/W-0
DMACOUNT<23:16>
R/W-0
R/W-0
DMACOUNT<15:8>
R/W-0
R/W-0
DMACOUNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DMACOUNT<31:0>: DMA Transfer Count bits
This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer
which identifies the entire transfer length. As the count progresses this count is decremented as bytes are
transferred.
DS60001191F-page 230
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-24: USBExRPC: USB ENDPOINT ‘x’ REQUEST PACKET COUNT REGISTER (HOST
MODE ONLY) (‘x’ = 1-7)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RQPKTCNT<15:8>
R/W-0
R/W-0
RQPKTCNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 RQPKTCNT<15:0>: Request Packet Count bits
Sets the number of packets of size MAXP that are to be transferred in a block transfer. This register is only
available in Host mode when AUTOREQ is set.
REGISTER 11-25: USBDPBFD: USB DOUBLE PACKET BUFFER DISABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
EP7TXD
EP6TXD
EP5TXD
EP4TXD
EP3TXD
EP2TXD
EP1TXD
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
EP7RXD
EP6RXD
EP5RXD
EP4RXD
EP3RXD
EP2RXD
EP1RXD
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-17 EP7TXD:EP1TXD: TX Endpoint ‘x’ Double Packet Buffer Disable bits
1 = TX double packet buffering is disabled for endpoint ‘x’
0 = TX double packet buffering is enabled for endpoint ‘x’
bit 16
Unimplemented: Read as ‘0’
bit 15-1 EP7RXD:EP1RXD: RX Endpoint ‘x’ Double Packet Buffer Disable bits
1 = RX double packet buffering is disabled for endpoint ‘x’
0 = RX double packet buffering is enabled for endpoint ‘x’
bit 0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 231
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-26: USBTMCON1: USB TIMING CONTROL REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
THHSRTN<15:8>
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
THHSRTN<7:0>
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
TUCH<15:8>
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
TUCH<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 THHSRTN:<15:0>: Hi-Speed Resume Signaling Delay bits
These bits set the delay from the end of Hi-Speed resume signaling (acting as a Host) to enable the UTM
normal operating mode.
bit 15-0 TUCH<15:0>: Chirp Time-out bits
These bits set the chirp time-out. This number, when multiplied by 4, represents the number of USB module
clock cycles before the time-out occurs.
Note:
Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum
specified in the USB 2.0 specification, making the USB module non-compliant.
REGISTER 11-27: USBTMCON2: USB TIMING CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
THBST<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3-0 THBST<3:0>: High Speed Time-out Adder bits
These bits represent the value to be added to the minimum high speed time-out period of 736 bit times. The
time-out period can be increased in increments of 64 Hi-Speed bit times (133 ns).
Note:
Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum
specified in the USB 2.0 specification, making the USB module non-compliant.
DS60001191F-page 232
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL 
REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
—
—
U-0
U-0
U-0
R/W-0
—
—
—
LPMNAK
R-0
R-0
R-0
R-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
LPMERRIE LPMRESIE LPMACKIE
ENDPOINT<3:0>
R-0
R-0
R-0
R-0
HIRD<3:0>
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
LPMNYIE
LPMSTIE
LPMTOIE
R/W-0
LPMEN<1:0>
R/W-0, HC
R/W-0, HC
LPMRES
LPMXMT
U-0
U-0
U-0
R-0
—
—
—
RMTWAK
R-0
R-0
R-0
R-0
LNKSTATE<3:0>
HC = Hardware Clearable
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29
LPMERRIE: LPM Error Interrupt Enable bit
1 = LPMERR interrupt is enabled
0 = LPMERR interrupt is disabled
bit 28
LPMRESIE: LPM Resume Interrupt Enable bit
1 = LPMRES interrupt is enabled
0 = LPMRES interrupt is disabled
bit 27
LPMACKIE: LPM Acknowledge Interrupt Enable bit
1 = Enable the LPMACK Interrupt
0 = Disable the LPMACK Interrupt
bit 26
LPMNYIE: LPM NYET Interrupt Enable bit
1 = Enable the LPMNYET Interrupt
0 = Disable the LPMNYET Interrupt
bit 25
LPMSTIE: LPM STALL Interrupt Enable bit
1 = Enable the LPMST Interrupt
0 = Disable the LPMST Interrupt
bit 24
LPMTOIE: LPM Time-out Interrupt Enable bit
1 = Enable the LPMTO Interrupt
0 = Disable the LPMTO Interrupt
bit 23-21 Unimplemented: Read as ‘0’
bit 20
LPMNAK: LPM-only Transaction Setting bit
1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK
0 = Normal transaction operation
Setting this bit to ‘1’ will only take effect after the USB module as been LPM suspended.
bit 19-18 LPMEN<1:0>: LPM Enable bits (Device mode)
11 = LPM and Extended transactions are supported
10 = LPM is supported and Extended transactions are not supported
01 = LPM is not supported but Extended transactions are supported
00 = LPM and Extended transactions are not supported
bit 17
LPMRES: LPM Resume bit
1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 µs.
0 = No resume operation
This bit is self-clearing.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 233
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL 
REGISTER 1 (CONTINUED)
bit 16
LPMXMT: LPM Transition to the L1 State bit
When in Device mode:
1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must
be set to ‘0b11. Both LPMXMT and LPMEN must be set in the same cycle.
0 = Maintain current state
When LPMXMT and LPMEN are set, the USB module can respond in the following ways:
• If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will
self clear and a software interrupt will be generated.
• If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In
this case, the bit will not self clear however a software interrupt will be generated.
When in Host mode:
1 = USB module will transmit an LPM transaction. This bit is self clearing, and will be immediately cleared
upon receipt of any Token or three time-outs have occurred.
0 = Maintain current state
bit 15-12 ENDPOINT<3:0>: LPM Token Packet Endpoint bits
This is the endpoint in the token packet of the LPM transaction.
bit 11-9 Unimplemented: Read as ‘0’
bit 8
RMTWAK: Remote Wake-up Enable bit
This bit is applied on a temporary basis only and is only applied to the current suspend state.
1 = Remote wake-up is enabled
0 = Remote wake-up is disabled
bit 7-4
HIRD<3:0>: Host Initiated Resume Duration bits
The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual
resume time of:
Resume Time = 50 µs + HIRD * 75 µs. The resulting range is 50 µs to 1200 µs.
bit 3-0
LNKSTATE<3:0>: Link State bits
This value is provided by the host to the peripheral to indicate what state the peripheral must transition to
after the receipt and acceptance of a LPM transaction. The only valid value for this register is ‘1’ for Sleep
State (L1). All other values are reserved.
DS60001191F-page 234
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R-0
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
—
—
LPMNCIF
LPMACKIF
LPMNYIF
LPMSTIF
—
LPMFADDR<6:0>
Legend:
R = Readable bit
-n = Value at POR
LPMERRIF LPMRESIF
HS = Hardware Settable
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14-8 LPMFADDR<6:0>: LPM Payload Function Address bits
These bits contain the address of the LPM payload function.
bit 7-6
Unimplemented: Read as ‘0’
bit 5
LPMERRIF: LPM Error Interrupt Flag bit (Device mode)
1 = An LPM transaction was received that had a LINKSTATE field that is not supported. The response will
be a STALL.
0 = No error condition
bit 4
LPMRESIF: LPM Resume Interrupt Flag bit
1 = The USB module has resumed (for any reason)
0 = No Resume condition
bit 3
LPMNCIF: LPM NC Interrupt Flag bit
When in Device mode:
1 = The USB module received a LPM transaction and responded with a NYET due to data pending in the
RX FIFOs.
0 = No NC interrupt condition
When in Host mode:
1 = A LPM transaction is transmitted and the device responded with an ACK
0 = No NC interrupt condition
bit 2
LPMACKIF: LPM ACK Interrupt Flag bit
When in Device mode:
1 = A LPM transaction was received and the USB Module responded with an ACK
0 = No ACK interrupt condition
When in Host mode:
1 = The LPM transaction is transmitted and the device responds with an ACK
0 = No ACK interrupt condition
bit 1
LPMNYIF: LPM NYET Interrupt Flag bit
When in Device mode:
1 = A LPM transaction is received and the USB Module responded with a NYET
0 = No NYET interrupt flag
When in Host mode:
1 = A LPM transaction is transmitted and the device responded with an NYET
0 = No NYET interrupt flag
 2013-2016 Microchip Technology Inc.
DS60001191F-page 235
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2
(CONTINUED)
bit 0
LPMSTIF: LPM STALL Interrupt Flag bit
When in Device mode:
1 = A LPM transaction was received and the USB Module responded with a STALL
0 = No Stall condition
When in Host mode:
1 = A LPM transaction was transmitted and the device responded with a STALL
0 = No Stall condition
DS60001191F-page 236
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
12.0
I/O PORTS
Note:
Key features of the I/O ports include:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
General purpose I/O pins are the simplest of
peripherals. They allow the PIC32MZ EC family device
to monitor and control other devices. To add flexibility
and functionality, some pins are multiplexed with
alternate function(s). These functions depend on which
peripheral features are on the device. In general, when
a peripheral is functioning, that pin may not be used as
a general purpose I/O pin.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Port Control
PIO Module
RD ODC
PBCLK4
Data Bus
D
PBCLK4
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
I/O Cell
0
1
D
Q
1
TRIS
CK
EN Q
0
WR TRIS
Output Multiplexers
D
Q
I/O Pin
LAT
CK
EN Q
WR LAT
WR PORT
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
PBCLK4
Synchronization
R
Peripheral Input
Peripheral Input Buffer
Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than shown here.
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DS60001191F-page 237
PIC32MZ Embedded Connectivity (EC) Family
12.1
Parallel I/O (PIO) Ports
All port pins have ten registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an
output. If the data direction bit is a ‘1’, then the pin is an
input. All port pins are defined as inputs after a Reset.
Reads from the latch (LATx) read the latch. Writes to
the latch write the latch. Reads from the port (PORTx)
read the port pins, while writes to the port pins write the
latch.
12.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx, and TRISx registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of outputs
higher than VDD (e.g., 5V) on any desired 5V-tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the maximum VIH specification.
Refer to the pin name tables (Table 2 through Table 5)
for the available pins and their functionality.
12.1.2
CONFIGURING ANALOG AND
DIGITAL PORT PINS
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSEL
and TRIS bits set. In order to use port pins for I/O
functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
Comparator module.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
DS60001191F-page 238
12.1.3
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP.
12.1.4
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
allows the PIC32MZ EC devices to generate interrupt
requests to the processor in response to a change-ofstate on selected input pins. This feature can detect
input change-of-states even in Sleep mode, when the
clocks are disabled. Every I/O port pin can be selected
(enabled) for generating an interrupt request on a
change-of-state.
Five control registers are associated with the CN functionality of each I/O port. The CNENx registers contain
the CN interrupt enable control bits for each of the input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
The CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a
current source or sink source connected to the pin,
and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
the control bits for each of the pins. Setting any of
the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
Note:
Pull-ups and pull-downs on change
notification pins should always be
disabled when the port pin is configured as
a digital output.
An additional control register (CNCONx) is shown in
Register 12-3.
12.2
CLR, SET, and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
12.3
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
PPS configuration provides an alternative to these
choices by enabling peripheral set selection and their
placement on a wide range of I/O pins. By increasing
the pinout options available on a particular device,
users can better tailor the device to their entire
application, rather than trimming the application to fit
the device.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software and
generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the peripheral mapping once it has been established.
12.3.1
AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable port number.
12.3.2
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digitalonly peripherals. These include general serial
communications (UART, SPI, and CAN), general purpose timer clock inputs, timer-related peripherals (input
capture and output compare), interrupt-on-change
inputs, and reference clocks (input and output).
In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
the peripheral’s function requires special I/O circuitry
on a specific port and cannot be easily connected to
multiple pins. These modules include I2C among others. A similar requirement excludes all modules with
analog inputs, such as the Analog-to-Digital Converter
(ADC).
A key difference between remappable and non-remappable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
 2013-2016 Microchip Technology Inc.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
12.3.3
CONTROLLING PPS
PPS features are controlled through two sets of SFRs:
one to map peripheral inputs, and one to map outputs.
Because they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on
whether an input or output is being mapped.
12.3.4
INPUT MAPPING
The inputs of the PPS options are mapped on the basis
of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The [pin name]R registers, where [pin name] refers to the
peripheral pins listed in Table 12-1, are used to configure peripheral input mapping (see Register 12-1). Each
register contains sets of 4 bit fields. Programming these
bit fields with an appropriate value maps the RPn pin
with the corresponding value to that peripheral. For any
given device, the valid range of values for any bit field is
shown in Table 12-1.
For example, Figure 12-2 illustrates the remappable
pin selection for the U1RX input.
FIGURE 12-2:
REMAPPABLE INPUT
EXAMPLE FOR U1RX
U1RXR<3:0>
0
RPD2
1
RPG8
2
RPF4
U1RX input
to peripheral
n
RPn
Note:
For input only, PPS functionality does not
have priority over TRISx settings. Therefore,
when configuring RPn pin for input, the
corresponding bit in the TRISx register must
also be configured for input (set to ‘1’).
DS60001191F-page 239
PIC32MZ Embedded Connectivity (EC) Family
TABLE 12-1:
INPUT PIN SELECTION
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT3
INT3R
INT3R<3:0>
T2CK
T2CKR
T2CKR<3:0>
T6CK
T6CKR
T6CKR<3:0>
IC3
IC3R
IC3R<3:0>
Note 1:
2:
3:
IC7
IC7R
IC7R<3:0>
U1RX
U1RXR
U1RXR<3:0>
U2CTS
U2CTSR
U2CTSR<3:0>
[pin name]R Value to
RPn Pin Selection
U5RX
U5RXR
U5RXR<3:0>
U6CTS
U6CTSR
U6CTSR<3:0>
SDI1
SDI1R
SDI1R<3:0>
SDI3
SDI3R
SDI3R<3:0>
SDI5(1)
SDI5R(1)
SDI5R<3:0>(1)
SS6(1)
SS6R(1)
SS6R<3:0>(1)
REFCLKI1
REFCLKI1R
REFCLKI1R<3:0>
INT4
INT4R
INT4R<3:0>
T5CK
T5CKR
T5CKR<3:0>
T7CK
T7CKR
T7CKR<3:0>
IC4
IC4R
IC4R<3:0>
IC8
IC8R
IC8R<3:0>
U3RX
U3RXR
U3RXR<3:0>
U4CTS
U4CTSR
U4CTSR<3:0>
SDI2
SDI2R
SDI2R<3:0>
SDI4
SDI4R
SDI4R<3:0>
C1RX(3)
C1RXR(3)
C1RXR<3:0>(3)
REFCLKI4
REFCLKI4R
REFCLKI4R<3:0>
INT2
INT2R
INT2R<3:0>
T3CK
T3CKR
T3CKR<3:0>
T8CK
T8CKR
T8CKR<3:0>
IC2
IC2R
IC2R<3:0>
IC5
IC5R
IC5R<3:0>
IC9
IC9R
IC9R<3:0>
U1CTS
U1CTSR
U1CTSR<3:0>
U2RX
U2RXR
U2RXR<3:0>
U5CTS
U5CTSR
U5CTSR<3:0>
SS1
SS1R
SS1R<3:0>
SS3
SS3R
SS3R<3:0>
SS4
SS4R
SS4R<3:0>
SS5(1)
SS5R(1)
SS5R<3:0>(1)
C2RX(3)
C2RXR(3)
C2RXR<3:0>(3)
0000 = RPD2
0001 = RPG8
0010 = RPF4
0011 = RPD10
0100 = RPF1
0101 = RPB9
0110 = RPB10
0111 = RPC14
1000 = RPB5
1001 = Reserved
1010 = RPC1(1)
1011 = RPD14(1)
1100 = RPG1(1)
1101 = RPA14(1)
1110 = RPD6(2)
1111 = Reserved
0000 = RPD3
0001 = RPG7
0010 = RPF5
0011 = RPD11
0100 = RPF0
0101 = RPB1
0110 = RPE5
0111 = RPC13
1000 = RPB3
1001 = Reserved
1010 = RPC4(1)
1011 = RPD15(1)
1100 = RPG0(1)
1101 = RPA15(1)
1110 = RPD7(2)
1111 = Reserved
0000 = RPD9
0001 = RPG6
0010 = RPB8
0011 = RPB15
0100 = RPD4
0101 = RPB0
0110 = RPE3
0111 = RPB7
1000 = Reserved
1001 = RPF12(1)
1010 = RPD12(1)
1011 = RPF8(1)
1100 = RPC3(1)
1101 = RPE9(1)
1110 = Reserved
1111 = Reserved
This selection is not available on 64-pin devices.
This selection is not available on 64-pin or 100-pin devices.
This selection is not available on devices without a CAN module.
DS60001191F-page 240
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 12-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
Note 1:
2:
3:
[pin name]R SFR
[pin name]R bits
INT1
INT1R
INT1R<3:0>
T4CK
T4CKR
T4CKR<3:0>
T9CK
T9CKR
T9CKR<3:0>
IC1
IC1R
IC1R<3:0>
IC6
IC6R
IC6R<3:0>
U3CTS
U3CTSR
U3CTSR<3:0>
U4RX
U4RXR
U4RXR<3:0>
U6RX
U6RXR
U6RXR<3:0>
SS2
SS2R
SS2R<3:0>
SDI6(1)
SDI6R(1)
SDI6R<3:0>(1)
OCFA
OCFAR
OCFAR<3:0>
REFCLKI3
REFCLKI3R
REFCLKI3R<3:0>
[pin name]R Value to
RPn Pin Selection
0000 = RPD1
0001 = RPG9
0010 = RPB14
0011 = RPD0
0100 = Reserved
0101 = RPB6
0110 = RPD5
0111 = RPB2
1000 = RPF3
1001 = RPF13(1)
1010 = No Connect
1011 = RPF2(1)
1100 = RPC2(1)
1101 = RPE8(1)
1110 = Reserved
1111 = Reserved
This selection is not available on 64-pin devices.
This selection is not available on 64-pin or 100-pin devices.
This selection is not available on devices without a CAN module.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 241
PIC32MZ Embedded Connectivity (EC) Family
12.3.5
OUTPUT MAPPING
12.3.6.1
In contrast to inputs, the outputs of the PPS options
are mapped on the basis of the pin. In this case, a
control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPnR registers (Register 12-2) are used to control
output mapping. Like the [pin name]R registers, each
register contains sets of 4 bit fields. The value of the
bit field corresponds to one of the peripherals, and
that peripheral’s output is mapped to the pin (see
Table 12-2 and Figure 12-3).
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK Configuration bit (CFGCON<13>). Setting IOLOCK prevents
writes to the control registers; clearing IOLOCK
allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
12.3.6.2
FIGURE 12-3:
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPF0
RPF0R<3:0>
Default
U1TX Output
U2RTS Output
0
1
2
RPF0
Output Data
Control Register Lock
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The IOL1WAY
Configuration bit (DEVCFG3<29>) blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure
does not execute, and the PPS control registers cannot
be written to. The only way to clear the bit and reenable peripheral remapping is to perform a device
Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
14
REFCLKO1
12.3.6
15
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32MZ EC devices include two features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Configuration bit select lock
DS60001191F-page 242
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 12-2:
OUTPUT PIN SELECTION
RPn Port Pin
RPnR SFR
RPnR bits
RPD2
RPD2R
RPD2R<3:0>
RPG8
RPG8R
RPG8R<3:0>
RPF4
RPF4R
RPF4R<3:0>
RPD10
RPD10R
RPD10R<3:0>
RPF1
RPF1R
RPF1R<3:0>
RPB9
RPB9R
RPB9R<3:0>
RPB10
RPB10R
RPB10R<3:0>
RPC14
RPC14R
RPC14R<3:0>
RPB5
RPB5R
RPB5R<3:0>
RPC1R(1)
RPC1R<3:0>(1)
RPD14(1)
RPD14R(1)
RPD14R<3:0>(1)
RPG1(1)
RPG1R(1)
RPG1R<3:0>(1)
RPA14(1)
RPA14R(1)
RPA14R<3:0>(1)
RPD6(2)
RPD6R(2)
RPD6R<3:0>(2)
RPD3
RPD3R
RPD3R<3:0>
RPG7
RPG7R
RPG7R<3:0>
RPF5
RPF5R
RPF5R<3:0>
RPD11
RPD11R
RPD11R<3:0>
RPF0
RPF0R
RPF0R<3:0>
RPB1
RPB1R
RPB1R<3:0>
RPE5
RPE5R
RPE5R<3:0>
RPC13
RPC13R
RPC13R<3:0>
RPB3
RPB3R
RPB3R<3:0>
RPC4(1)
RPC4R(1)
RPC4R<3:0>(1)
RPD15(1)
RPD15R(1)
RPD15R<3:0>(1)
RPG0(1)
RPG0R(1)
RPG0R<3:0>(1)
RPA15(1)
RPA15R(1)
RPA15R<3:0>(1)
RPD7(2)
RPD7R(2)
RPD7R<3:0>(2)
RPD9
RPD9R
RPD9R<3:0>
RPG6
RPG6R
RPG6R<3:0>
RPB8
RPB8R
RPB8R<3:0>
RPB15
RPB15R
RPB15R<3:0>
RPD4
RPD4R
RPD4R<3:0>
RPB0
RPB0R
RPB0R<3:0>
RPE3
RPE3R
RPE3R<3:0>
RPC1
(1)
RPB7
RPB7R
RPB7R<3:0>
RPF12(1)
RPF12R(1)
RPF12R<3:0>(1)
RPD12(1)
RPD12R(1)
RPD12R<3:0>(1)
RPF8(1)
RPF8R(1)
RPF8R<3:0>(1)
RPC3(1)
RPC3R(1)
RPC3R<3:0>(1)
RPE9(1)
RPE9R(1)
RPE9R<3:0>(1)
Note 1:
2:
3:
RPnR Value to Peripheral
Selection
0000 = No Connect
0001 = U3TX
0010 = U4RTS
0011 = Reserved
0100 = Reserved
0101 = SDO1
0110 = SDO2
0111 = SDO3
1000 = Reserved
1001 = SDO5(1)
1010 = SS6(1)
1011 = OC3
1100 = OC6
1101 = REFCLKO4
1110 = C2OUT
1111 = C1TX(3)
0000 = No Connect
0001 = U1TX
0010 = U2RTS
0011 = U5TX
0100 = U6RTS
0101 = SDO1
0110 = SDO2
0111 = SDO3
1000 = SDO4
1001 = SDO5(1)
1010 = Reserved
1011 = OC4
1100 = OC7
1101 = Reserved
1110 = Reserved
1111 = REFCLKO1
0000 = No Connect
0001 = U3RTS
0010 = U4TX
0011 = Reserved
0100 = U6TX
0101 = SS1
0110 = Reserved
0111 = SS3
1000 = SS4
1001 = SS5(1)
1010 = SDO6(1)
1011 = OC5
1100 = OC8
1101 = Reserved
1110 = C1OUT
1111 = REFCLKO3
This selection is not available on 64-pin devices.
This selection is not available on 64-pin or 100-pin devices.
This selection is not available on devices without a CAN module.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 243
PIC32MZ Embedded Connectivity (EC) Family
TABLE 12-2:
OUTPUT PIN SELECTION (CONTINUED)
RPn Port Pin
RPnR SFR
RPnR bits
RPD1
RPD1R
RPD1R<3:0>
RPG9
RPG9R
RPG9R<3:0>
RPB14
RPB14R
RPB14R<3:0>
RPD0
RPD0R
RPD0R<3:0>
RPB6
RPB6R
RPB6R<3:0>
RPD5
RPD5R
RPD5R<3:0>
RPB2
RPB2R
RPB2R<3:0>
RPF3
RPF3R
RPF3R<3:0>
(1)
RPF13R
RPF13R<3:0>(1)
RPC2(1)
RPC2R(1)
RPC2R<3:0>(1)
RPE8(1)
RPE8R(1)
RPE8R<3:0>(1)
RPF2(1)
RPF2R(1)
RPF2R<3:0>(1)
RPF13
Note 1:
2:
3:
(1)
RPnR Value to Peripheral
Selection
0000 = No Connect
0001 = U1RTS
0010 = U2TX
0011 = U5RTS
0100 = U6TX
0101 = Reserved
0110 = SS2
0111 = Reserved
1000 = SDO4
1001 = Reserved
1010 = SDO6(1)
1011 = OC2
1100 = OC1
1101 = OC9
1110 = Reserved
1111 = C2TX(3)
This selection is not available on 64-pin devices.
This selection is not available on 64-pin or 100-pin devices.
This selection is not available on devices without a CAN module.
DS60001191F-page 244
 2013-2016 Microchip Technology Inc.
I/O Ports Control Registers
ANSELA
0010
0020
0030
0040
TRISA
PORTA
LATA
ODCA
0050
CNPUA
0060
CNPDA
0070 CNCONA
0080
CNENA
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
Legend:
Note 1:
TRISA15 TRISA14
26/10
25/9
24/8
23/7
22/6
—
—
—
—
ANSA10
ANSA9
—
—
—
—
—
—
TRISA10
TRISA9
16/0
—
—
0000
ANSA1
ANSA0
0623
—
—
0000
TRISA2
TRISA1
TRISA0
C6FF
21/5
20/4
19/3
18/2
—
—
—
—
—
—
ANSA5
—
—
—
—
—
—
—
—
—
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
17/1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RA15
RA14
—
—
—
RA10
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATA15
LATA14
—
—
—
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
ODCA10
ODCA9
—
ODCA7
ODCA6
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUA15 CNPUA14
—
—
—
31:16
—
—
—
—
—
—
15:0
31:16
ODCA15 ODCA14
—
—
—
—
15:0 CNPDA15 CNPDA14
CNPUA10 CNPUA9
—
—
CNPDA10 CNPDA9
—
—
—
CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
—
—
—
—
—
—
—
—
0000
CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
CNIEA10
CNIEA9
—
CNIEA7
CNIEA6
CNIEA5
CNIEA4
CNIEA3
CNIEA2
CNIEA1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATA10
CN
STATA9
—
CN
STATA7
CN
STATA6
CN
STATA5
CN
STATA4
CN
STATA3
CN
STATA2
CN
STATA1
15:0
31:16
0090 CNSTATA
Bits
All
Resets
Register
Name(1)
0000
PORTA REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY
Bit Range
Virtual Address
(BF86_#)
TABLE 12-3:
15:0
CNIEA15 CNIEA14
—
—
CN
CN
STATA15 STATA14
—
—
CNIEA0 0000
—
0000
CN
0000
STATA0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
DS60001191F-page 245
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
12.4
TRISB
0120 PORTB
0130
LATB
0140
ODCB
0150 CNPUB
0160 CNPDB
0170 CNCONB
0180 CNENB
0190 CNSTATB
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0100 ANSELB
0110
PORTB REGISTER MAP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
ANSB15
—
ANSB14
—
ANSB13
—
ANSB12
—
ANSB11
—
ANSB10
—
ANSB9
—
ANSB8
—
ANSB7
—
ANSB6
—
ANSB5
—
ANSB41
—
ANSB3
—
ANSB2
—
ANSB1
—
ANSB0
—
FFFF
0000
15:0 TRISB15
31:16
—
TRISB14
—
TRISB13
—
TRISB12
—
TRISB11
—
TRISB10
—
TRISB9
—
TRISB8
—
TRISB7
—
TRISB6
—
TRISB5
—
TRISB4
—
TRISB3
—
TRISB2
—
TRISB1
—
TRISB0
—
FFFF
0000
15:0
31:16
RB15
—
RB14
—
RB13
—
RB12
—
RB11
—
RB10
—
RB9
—
RB8
—
RB7
—
RB6
—
RB5
—
RB4
—
RB3
—
RB2
—
RB1
—
RB0
—
xxxx
0000
15:0
31:16
LATB15
—
LATB14
—
LATB13
—
LATB12
—
LATB11
—
LATB10
—
LATB9
—
LATB8
—
LATB7
—
LATB6
—
LATB5
—
LATB4
—
LATB3
—
LATB2
—
LATB1
—
LATB0
—
xxxx
0000
15:0 ODCB15
31:16
—
ODCB14
—
ODCB13
—
ODCB12
—
ODCB11
—
ODCB10
—
ODCB9
—
ODCB8
—
ODCB7
—
ODCB6
—
ODCB5
—
ODCB4
—
ODCB3
—
ODCB2
—
ODCB1
—
ODCB0
—
0000
0000
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5
31:16
—
—
—
—
—
—
—
—
—
—
—
CNPUB4
—
CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
—
—
—
—
0000
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5
31:16
—
—
—
—
—
—
—
—
—
—
—
CNPDB4
—
CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
—
—
—
—
0000
15:0
31:16
ON
—
15:0 CNIEB15
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEB14
—
CNIEB13
—
CNIEB12
—
CNIEB11
—
CNIEB10
—
CNIEB9
—
CNIEB8
—
CNIEB7
—
CNIEB6
—
CNIEB5
—
CNIEB4
—
CNIEB3
—
CNIEB2
—
CNIEB1
—
—
—
0000
0000
CNIEB0 0000
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
0000
STATB15 STATB14 STATB13 STATB12 STATB11 STATB10 STATB9 STATB8 STATB7 STATB6 STATB5 STATB4 STATB3 STATB2 STATB1 STATB0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
15:0
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 246
TABLE 12-4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
PORTC REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY
0200 ANSELC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSC4
—
ANSC3
—
ANSC2
—
ANSC1
—
—
0000
001E
0210
TRISC
31:16
15:0
—
TRISC15
—
TRISC14
—
TRISC13
—
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4
—
TRISC3
—
TRISC2
—
TRISC1
—
—
0000
F01E
0220 PORTC
31:16
15:0
—
RC15
—
RC14
—
RC13
—
RC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC4
—
RC3
—
RC2
—
RC1
—
—
0000
xxxx
0230
LATC
31:16
15:0
—
LATC15
—
LATC14
—
LATC13
—
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATC4
—
LATC3
—
LATC2
—
LATC1
—
—
0000
xxxx
0240
ODCC
31:16
15:0
—
ODCC15
—
ODCC14
—
ODCC13
—
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCC4
—
ODCC3
—
ODCC2
—
ODCC1
—
—
0000
0000
0250 CNPUC
31:16
15:0
—
CNPUC15
—
CNPUC14
—
CNPUC13
—
CNPUC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUC4
—
CNPUC3
—
CNPUC2
—
CNPUC1
—
—
0000
0000
0260 CNPDC
31:16
15:0
—
CNPDC15
—
CNPDC14
—
CNPDC13
—
CNPDC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDC4
—
CNPDC3
—
CNPDC2
—
CNPDC1
—
—
0000
0000
0270 CNCONC
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0280 CNENC
31:16
15:0
—
CNIEC15
—
CNIEC14
CNIEC13
—
CNIEC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEC4
—
CNIEC3
—
CNIEC2
—
CNIEC1
—
—
0000
0000
0290 CNSTATC
31:16
—
—
—
—
15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
Legend:
Note 1:
—
—
—
—
CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
DS60001191F-page 247
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-5:
Virtual Address
(BF86_#)
Register
Name(1)
Bit Range
PORTC REGISTER MAP FOR 64-PIN DEVICES ONLY
0210
TRISC
31:16
15:0
—
TRISC15
—
TRISC14
—
TRISC13
—
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
F000
0220 PORTC
31:16
15:0
—
RC15
—
RC14
—
RC13
—
RC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
0230
LATC
31:16
15:0
—
LATC15
—
LATC14
—
LATC13
—
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
0240
ODCC
31:16
15:0
—
ODCC15
—
ODCC14
—
ODCC13
—
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
0250 CNPUC
31:16
15:0
—
CNPUC15
—
CNPUC14
—
CNPUC13
—
CNPUC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0260 CNPDC
31:16
15:0
—
CNPDC15
—
CNPDC14
—
CNPDC13
—
CNPDC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0270 CNCONC
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0280 CNENC
31:16
15:0
—
CNIEC15
—
CNIEC14
CNIEC13
—
CNIEC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0290 CNSTATC
31:16
—
—
—
—
15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bits
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 248
TABLE 12-6:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
PORTD REGISTER MAP FOR 124-PIN AND 144-PIN DEVICES ONLY
—
—
0000
C000
0300 ANSELD
31:16
15:0
—
ANSD14
—
ANSD13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0310
31:16
—
15:0 TRISD15
—
TRISD14
—
TRISD13
—
TRISD12
—
TRISD11
—
TRISD10
—
TRISD9
—
—
—
TRISD7
—
TRISD6
—
TRISD5
—
TRISD4
—
TRISD3
—
TRISD2
—
TRISD1
TRISD
—
0000
TRISD0 FEFF
0320 PORTD
31:16
15:0
—
RD15
—
RD14
—
RD13
—
RD12
—
RD11
—
RD10
—
RD9
—
—
—
RD7
—
RD6
—
RD5
—
RD4
—
RD3
—
RD2
—
RD1
—
RD0
0000
xxxx
0330
LATD
31:16
15:0
—
LATD15
—
LATD14
—
LATD13
—
LATD12
—
LATD11
—
LATD10
—
LATD9
—
—
—
LATD7
—
LATD6
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0
0000
xxxx
0340
ODCD
31:16
—
15:0 ODCD15
—
ODCD14
—
ODCD13
—
ODCD12
—
ODCD11
—
ODCD10
—
ODCD9
—
—
—
ODCD7
—
ODCD6
—
ODCD5
—
ODCD4
—
ODCD3
—
ODCD2
—
ODCD1
—
0000
ODCD0 0000
0350 CNPUD
31:16
—
—
—
—
—
—
—
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9
—
—
—
—
—
—
—
—
—
—
0000
CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000
0360 CNPDD
31:16
—
—
—
—
—
—
—
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9
—
—
—
—
—
—
—
—
—
—
0000
CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000
0370 CNCOND
31:16
15:0
0380 CNEND
31:16
—
15:0 CNIED15
31:16
—
—
—
CNIED14
—
SIDL
—
—
—
—
CNIED13 CNIED12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIED11
—
CNIED10
—
CNIED9
—
—
—
CNIED7
—
CNIED6
—
CNIED5
—
CNIED4
—
CNIED3
—
CNIED2
—
CNIED1
—
—
0000
0000
—
0000
CNIED0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNS
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
—
0000
TATD15
STATD14 STATD13 STATD12 STATD11 STATD10 STATD9
STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0390 CNSTATD
Legend:
Note 1:
—
ON
15:0
DS60001191F-page 249
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-7:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY
—
—
0000
C000
0300 ANSELD
31:16
15:0
—
ANSD15
—
ANSD14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0310
31:16
—
15:0 TRISD15
—
TRISD14
—
TRISD13
—
TRISD12
—
TRISD11
—
TRISD10
—
TRISD9
—
—
—
—
—
—
—
TRISD5
—
TRISD4
—
TRISD3
—
TRISD2
—
TRISD1
TRISD
—
0000
TRISD0 FE3F
0320 PORTD
31:16
15:0
—
RD15
—
RD14
—
RD13
—
RD12
—
RD11
—
RD10
—
RD9
—
—
—
—
—
—
—
RD5
—
RD4
—
RD3
—
RD2
—
RD1
—
RD0
0000
xxxx
0330
LATD
31:16
15:0
—
LATD15
—
LATD14
—
LATD13
—
LATD12
—
LATD11
—
LATD10
—
LATD9
—
—
—
—
—
—
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0
0000
xxxx
0340
ODCD
31:16
—
15:0 ODCD15
—
ODCD14
—
ODCD13
—
ODCD12
—
ODCD11
—
ODCD10
—
ODCD9
—
—
—
—
—
—
—
ODCD5
—
ODCD4
—
ODCD3
—
ODCD2
—
ODCD1
—
0000
ODCD0 0000
0350 CNPUD
31:16
—
—
—
—
—
—
—
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000
0360 CNPDD
31:16
—
—
—
—
—
—
—
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000
0370 CNCOND
31:16
15:0
0380 CNEND
31:16
—
15:0 CNIED15
31:16
—
—
—
CNIED14
—
SIDL
—
—
—
—
CNIED13 CNIED12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIED11
—
CNIED10
—
CNIED9
—
—
—
—
—
—
—
CNIED5
—
CNIED4
—
CNIED3
—
CNIED2
—
CNIED1
—
—
0000
0000
—
0000
CNIED0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNS
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
0000
TATD15
STATD14 STATD13 STATD12 STATD11 STATD10 STATD9
STATD5 STATD4 STATD3 STATD2 STATD1 STATD0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0390 CNSTATD
Legend:
Note 1:
—
ON
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 250
TABLE 12-8:
Virtual Address
(BF86_#)
Register
Name(1)
Bit Range
PORTD REGISTER MAP FOR 64-PIN DEVICES ONLY
0310
TRISD
31:16
15:0
—
—
—
—
—
—
—
—
—
TRISD11
—
TRISD10
—
TRISD9
—
—
—
—
—
—
—
TRISD5
—
TRISD4
—
TRISD3
—
TRISD2
—
TRISD1
—
TRISD0
0000
0E3F
0320 PORTD
31:16
15:0
—
—
—
—
—
—
—
—
—
RD11
—
RD10
—
RD9
—
—
—
—
—
—
—
RD5
—
RD4
—
RD3
—
RD2
—
RD1
—
RD0
0000
xxxx
0330
LATD
31:16
15:0
—
—
—
—
—
—
—
—
—
LATD11
—
LATD10
—
LATD9
—
—
—
—
—
—
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0
0000
xxxx
0340
ODCD
31:16
15:0
—
—
—
—
—
—
—
—
—
ODCD11
—
ODCD10
—
ODCD9
—
—
—
—
—
—
—
ODCD5
—
ODCD4
—
ODCD3
—
ODCD2
—
ODCD1
—
ODCD0
0000
0000
0350 CNPUD
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
CNPUD11 CNPUD10 CNPUD9
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000
0360 CNPDD
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
CNPDD11 CNPDD10 CNPDD9
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000
0370 CNCOND
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0380 CNEND
31:16
15:0
—
—
—
—
—
—
—
—
—
CNIED11
—
CNIED10
—
CNIED9
—
—
—
—
—
—
—
CNIED5
—
CNIED4
—
CNIED3
—
CNIED2
—
CNIED1
—
CNIED0
0000
0000
31:16
—
—
—
—
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
0000
STATD11 STATD10 STATD9
STATD5 STATD4 STATD3 STATD2 STATD1 STATD0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0390 CNSTATD
Legend:
Note 1:
31/15
All
Resets
Bits
DS60001191F-page 251
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-9:
Virtual Address
(BF86_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Bits
0400 ANSELE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSE9
—
ANSE8
—
ANSE7
—
ANSE6
—
ANSE5
—
ANSE4
—
—
—
—
—
—
—
—
0000
03F0
0410
TRISE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9
—
TRISE8
—
TRISE7
—
TRISE6
—
TRISE5
—
TRISE4
—
TRISE3
—
TRISE2
—
TRISE1
—
TRISE0
0000
03FF
0420
PORTE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
RE9
—
RE8
—
RE7
—
RE6
—
RE5
—
RE4
—
RE3
—
RE2
—
RE1
—
RE0
0000
xxxx
0430
LATE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
LATE9
—
LATE8
—
LATE7
—
LATE6
—
LATE5
—
LATE4
—
LATE3
—
LATE2
—
LATE1
—
LATE0
0000
xxxx
0440
ODCE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCE9
—
ODCE8
—
ODCE7
—
ODCE6
—
ODCE5
—
ODCE4
—
ODCE3
—
ODCE2
—
ODCE1
—
ODCE0
0000
0000
0450
CNPUE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUE9 CNPUE8 CNPUE7
—
CNPUE6
—
CNPUE5
—
—
—
—
—
0000
CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
0460
CNPDE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDE9 CNPDE8 CNPDE7
—
CNPDE6
—
CNPDE5
—
—
—
—
—
0000
CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000
0470 CNCONE
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0480
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEE9
—
CNIEE8
—
CNIEE7
—
CNIEE6
—
CNIEE5
—
CNIEE4
—
CNIEE3
—
CNIEE2
—
CNIEE1
31:16
—
—
—
—
—
—
CNENE
0000
0000
—
0000
CNIEE0 0000
—
—
—
—
—
—
—
—
—
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
0000
STATE9 STATE8 STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0490 CNSTATE
Legend:
Note 1:
—
—
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 252
TABLE 12-10: PORTE REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0400 ANSELE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSE7
—
ANSE6
—
ANSE5
—
ANSE4
—
—
—
—
—
—
—
—
0000
00F0
0410
TRISE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE7
—
TRISE6
—
TRISE5
—
TRISE4
—
TRISE3
—
TRISE2
—
TRISE1
—
TRISE0
0000
00FF
0420
PORTE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RE7
—
RE6
—
RE5
—
RE4
—
RE3
—
RE2
—
RE1
—
RE0
0000
xxxx
0430
LATE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATE7
—
LATE6
—
LATE5
—
LATE4
—
LATE3
—
LATE2
—
LATE1
—
LATE0
0000
xxxx
0440
ODCE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCE7
—
ODCE6
—
ODCE5
—
ODCE4
—
ODCE3
—
ODCE2
—
ODCE1
—
ODCE0
0000
0000
0450
CNPUE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUE7
—
CNPUE6
—
CNPUE5
—
—
—
—
—
0000
CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
0460
CNPDE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDE7
—
CNPDE6
—
CNPDE5
—
—
—
—
—
0000
CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000
0470 CNCONE
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0480
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEE7
—
CNIEE6
—
CNIEE5
—
CNIEE4
—
CNIEE3
—
CNIEE2
—
CNIEE1
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CNENE
0000
0000
—
0000
CNIEE0 0000
—
—
—
—
—
—
—
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
0000
STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0490 CNSTATE
Legend:
Note 1:
—
—
DS60001191F-page 253
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-11: PORTE REGISTER MAP FOR 64-PIN DEVICES ONLY
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0500 ANSELF
31:16
15:0
—
—
—
—
—
ANSF13
—
ANSF12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
3000
0510
TRISF
31:16
15:0
—
—
—
—
—
TRISF13
—
TRISF12
—
—
—
—
—
—
—
TRISF8
—
—
—
—
—
TRISF5
—
TRISF4
—
TRISF3
—
TRISF2
—
TRISF1
—
TRISF0
0000
313F
0520
PORTF
31:16
15:0
—
—
—
—
—
RF13
—
RF12
—
—
—
—
—
—
—
RF8
—
—
—
—
—
RF5
—
RF4
—
RF3
—
RF2
—
RF1
—
RF0
0000
xxxx
0530
LATF
31:16
15:0
—
—
—
—
—
LATF13
—
LATF12
—
—
—
—
—
—
—
LATF8
—
—
—
—
—
LATF5
—
LATF4
—
LATF3
—
LATF2
—
LATF1
—
LATF0
0000
xxxx
0540
ODCF
31:16
15:0
—
—
—
—
—
ODCF13
—
ODCF12
—
—
—
—
—
—
—
ODCF8
—
—
—
—
—
ODCF5
—
ODCF4
—
ODCF3
—
ODCF2
—
ODCF1
—
ODCF0
0000
0000
0550 CNPUF
31:16
15:0
—
—
—
—
—
—
CNPUF13 CNPUF12
—
—
—
—
—
—
—
CNPUF8
—
—
—
—
—
CNPUF5
—
CNPUF4
—
CNPUF3
—
CNPUF2
—
CNPUF1
—
0000
CNPUF0 0000
0560 CNPDF
31:16
15:0
—
—
—
—
—
—
CNPDF13 CNPDF12
—
—
—
—
—
—
—
CNPDF8
—
—
—
—
—
CNPDF5
—
CNPDF4
—
CNPDF3
—
CNPDF2
—
CNPDF1
—
0000
CNPDF0 0000
0570 CNCONF
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0580 CNENF
31:16
15:0
—
—
—
—
—
CNIEF13
—
CNIEF12
—
—
—
—
—
—
—
CNIEF8
—
—
—
—
—
CNIEF5
—
CNIEF4
—
CNIEF3
—
CNIEF2
—
CNIEF1
—
CNIEF0
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
0000
STATF13 STATF12
STATF8
STATF5 STATF4 STATF3 STATF2 STATF1 STATF0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0590 CNSTATF
Legend:
Note 1:
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 254
TABLE 12-12: PORTF REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY
Virtual Address
(BF86_#)
Register
Name(1)
Bit Range
0510
TRISF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5
—
TRISF4
—
TRISF3
—
—
—
TRISF1
—
TRISF0
0000
003B
0520
PORTF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RF5
—
RF4
—
RF3
—
—
—
RF1
—
RF0
0000
xxxx
0530
LATF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATF5
—
LATF4
—
LATF3
—
—
—
LATF1
—
LATF0
0000
xxxx
0540
ODCF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCF5
—
ODCF4
—
ODCF3
—
—
—
ODCF1
—
ODCF0
0000
0000
0550
CNPUF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUF5
—
CNPUF4
—
CNPUF3
—
—
—
CNPUF1
—
0000
CNPUF0 0000
0560
CNPDF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDF5
—
CNPDF4
—
CNPDF3
—
—
—
CNPDF1
—
0000
CNPDF0 0000
0570 CNCONF
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0580
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEF5
—
CNIEF4
—
CNIEF3
—
—
—
CNIEF1
—
CNIEF0
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATF3
—
CN
STATF1
—
CN
STATF0
0000
—
—
CN
STATF4
—
15:0
—
CN
STATF5
CNENF
0590 CNSTATF
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bits
—
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
DS60001191F-page 255
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-13: PORTF REGISTER MAP FOR 64-PIN DEVICES ONLY
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
ANSG15
—
—
—
—
—
—
—
—
—
—
—
ANSG9
—
ANSG8
—
ANSG7
—
ANSG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
83C0
—
—
—
—
—
TRISG9
—
TRISG8
—
TRISG7
—
TRISG6
—
—
—
—
—
—
—
—
—
TRISG1
—
TRISG0
0000
F3C3
0600 ANSELG
31:16
15:0
0610
31:16
—
15:0 TRISG15
TRISG
—
—
—
TRISG14 TRISG13 TRISG12
0620 PORTG
31:16
15:0
—
RG15
—
RG14
—
RG13
—
RG12
—
—
—
—
—
RG9
—
RG8
—
RG7
—
RG6
—
—
—
—
—
—
—
—
—
RG1
—
RG0
0000
xxxx
0630
LATG
31:16
15:0
—
LATG15
—
LATG14
—
LATG13
—
LATG12
—
—
—
—
—
LATG9
—
LATG8
—
LATG7
—
LATG6
—
—
—
—
—
—
—
—
—
LATG1
—
LATG0
0000
xxxx
0640
ODCG
31:16
15:0
—
ODCG15
—
ODCG14
—
ODCG13
—
ODCG12
—
—
—
—
—
ODCG9
—
ODCG8
—
ODCG7
—
ODCG6
—
—
—
—
—
—
—
—
—
ODCG1
—
ODCG0
0000
0000
0650 CNPUG
31:16
—
—
—
—
15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12
—
—
—
—
—
CNPUG9
—
CNPUG8
—
CNPUG7
—
CNPUG6
—
—
—
—
—
—
—
—
—
—
0000
CNPUG1 CNPUG0 0000
0660 CNPDG
31:16
—
—
—
—
15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12
—
—
—
—
—
CNPDG9
—
CNPDG8
—
CNPDG7
—
CNPDG6
—
—
—
—
—
—
—
—
—
—
0000
CNPDG1 CNPDG0 0000
0670 CNCONG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0680 CNENG
31:16
—
15:0 CNIEG15
—
—
—
—
—
CNIEG9
—
CNIEG8
—
CNIEG7
—
CNIEG6
—
—
—
—
—
—
—
—
—
CNIEG1
—
CNIEG0
0000
0000
31:16
—
—
—
SIDL
—
—
—
—
—
CNIEG14 CNIEG13 CNIEG12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
0000
STATG15 STATG14 STATG13 STATG12
STATG9
STATG8
STATG7
STATG6
STATG1 STATG0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0690 CNSTATG
Legend:
Note 1:
—
ON
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 256
TABLE 12-14: PORTG REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0600 ANSELG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSG9
—
ANSG8
—
ANSG7
—
ANSG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
03C0
0610
TRISG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9
—
TRISG8
—
TRISG7
—
TRISG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
03C0
0620 PORTG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
RG9
—
RG8
—
RG7
—
RG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
0630
LATG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
LATG9
—
LATG8
—
LATG7
—
LATG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
0640
ODCG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCG9
—
ODCG8
—
ODCG7
—
ODCG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0650 CNPUG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUG9
—
CNPUG8
—
CNPUG7
—
CNPUG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0660 CNPDG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDG9
—
CNPDG8
—
CNPDG7
—
CNPDG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0670 CNCONG
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0680 CNENG
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEG9
—
CNIEG8
—
CNIEG7
—
CNIEG6
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
CN
CN
CN
—
—
—
—
—
—
0000
STATG9
STATG8
STATG7
STATG6
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
0690 CNSTATG
Legend:
Note 1:
DS60001191F-page 257
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-15: PORTG REGISTER MAP FOR 64-PIN DEVICES ONLY
0710
TRISH
0720 PORTH
0730
LATH
0740
ODCH
0750 CNPUH
0760 CNPDH
0770 CNCONH
0780 CNENH
0790 CNSTATH
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSH6
—
15:0
31:16
—
—
—
—
TRISH13
—
TRISH12
—
—
—
TRISH10
—
TRISH9
—
TRISH8
—
—
—
TRISH6
—
15:0
31:16
—
—
—
—
RH13
—
RH12
—
—
—
RH10
—
RH9
—
RH8
—
—
—
15:0
31:16
—
—
—
—
LATH13
—
LATH12
—
—
—
LATH10
—
LATH9
—
LATH8
—
15:0
31:16
—
—
—
—
ODCH13
—
ODCH12
—
—
—
ODCH10
—
ODCH9
—
15:0
31:16
—
—
—
—
CNPUH13 CNPUH12
—
—
—
—
15:0
31:16
—
—
—
—
CNPDH13 CNPDH12
—
—
—
—
15:0
31:16
ON
—
—
—
SIDL
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
CNIEH13
—
CNIEH12
—
—
—
CNIEH10
—
21/5
17/1
16/0
All
Resets
0700 ANSELH
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
0000
20/4
19/3
18/2
—
—
—
—
—
ANSH5
—
ANSH4
—
—
—
—
—
ANSH1
—
ANSH0 0073
—
0000
TRISH5
—
TRISH4
—
—
—
—
—
TRISH1
—
TRISH0 3773
—
0000
RH6
—
RH5
—
RH4
—
—
—
—
—
RH1
—
RH0
—
xxxx
0000
—
—
LATH6
—
LATH5
—
LATH4
—
—
—
—
—
LATH1
—
LATH0
—
xxxx
0000
ODCH8
—
—
—
ODCH6
—
ODCH5
—
ODCH4
—
—
—
—
—
ODCH1
—
ODCH0 0000
—
0000
CNPUH10 CNPUH9
—
—
CNPUH8
—
—
—
CNPUH6 CNPUH5 CNPUH4
—
—
—
—
—
—
—
CNPUH1 CNPUH0 0000
—
—
0000
CNPDH10 CNPDH9
—
—
CNPDH8
—
—
—
CNPDH6 CNPDH5 CNPDH4
—
—
—
—
—
—
—
CNPDH1 CNPDH0 0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEH9
—
CNIEH8
—
—
—
CNIEH6
—
CNIEH5
—
CNIEH4
—
—
—
—
—
CNIEH1
—
—
—
0000
0000
CNIEH0 0000
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
—
—
—
—
0000
STATH13 STATH12
STATH10 STATH9 STATH8
STATH6 STATH5 STATH4
STATH1 STATH0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
15:0
—
—
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 258
TABLE 12-16: PORTH REGISTER MAP FOR 124-PIN DEVICES ONLY
0700 ANSELH
0710
TRISH
0720 PORTH
0730
LATH
0740
ODCH
0750 CNPUH
0760 CNPDH
0770 CNCONH
0780 CNENH
0790 CNSTATH
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSH6
—
TRISH14
—
TRISH13
—
TRISH12
—
TRISH11
—
TRISH10
—
TRISH9
—
TRISH8
—
TRISH7
—
TRISH6
—
15:0 TRISH15
31:16
—
22/6
21/5
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
0000
20/4
19/3
18/2
—
—
—
—
—
ANSH5
—
ANSH4
—
—
—
—
—
ANSH1
—
ANSH0 0073
—
0000
TRISH5
—
TRISH4
—
TRISH3
—
TRISH2
—
TRISH1
—
TRISH0 FFFF
—
0000
15:0
31:16
RH15
—
RH14
—
RH13
—
RH12
—
RH11
—
RH10
—
RH9
—
RH8
—
RH7
—
RH6
—
RH5
—
RH4
—
RH3
—
RH2
—
RH1
—
RH0
—
xxxx
0000
15:0
31:16
LATH15
—
LATH14
—
LATH13
—
LATH12
—
LATH11
—
LATH10
—
LATH9
—
LATH8
—
LATH7
—
LATH6
—
LATH5
—
LATH4
—
LATH3
—
LATH2
—
LATH1
—
LATH0
—
xxxx
0000
15:0 ODCH15
31:16
—
ODCH14
—
ODCH13
—
ODCH12
—
ODCH11
—
ODCH10
—
ODCH9
—
ODCH8
—
ODCH7
—
ODCH6
—
ODCH5
—
ODCH4
—
ODCH3
—
ODCH2
—
ODCH1
—
ODCH0 0000
—
0000
15:0 CNPUH15 CNPUH14 CNPUH13 CNPUH12 CNPUH11 CNPUH10 CNPUH9
31:16
—
—
—
—
—
—
—
CNPUH8
—
CNPUH7
—
CNPUH6 CNPUH5 CNPUH4 CNPUH3 CNPUH2 CNPUH1 CNPUH0 0000
—
—
—
—
—
—
—
0000
15:0 CNPDH15 CNPDH14 CNPDH13 CNPDH12 CNPDH11 CNPDH10 CNPDH9
31:16
—
—
—
—
—
—
—
CNPDH8
—
CNPDH7
—
CNPDH6 CNPDH5 CNPDH4 CNPDH3 CNPDH2 CNPDH1 CNPDH0 0000
—
—
—
—
—
—
—
0000
15:0
31:16
ON
—
15:0 CNIEH15
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEH14
—
CNIEH13
—
CNIEH12
—
CNIEH11
—
CNIEH10
—
CNIEH9
—
CNIEH8
—
CNIEH7
—
CNIEH6
—
CNIEH5
—
CNIEH4
—
CNIEH3
—
CNIEH2
—
CNIEH1
—
—
—
0000
0000
CNIEH0 0000
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
0000
STATH15 STATH14 STATH13 STATH12 STATH11 STATH10 STATH9 STATH8 STATH7 STATH6 STATH5 STATH4 STATH3 STATH2 STATH1 STATH0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
15:0
DS60001191F-page 259
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-17: PORTH REGISTER MAP FOR 144-PIN DEVICES ONLY
0800 ANSELJ
0810
TRISJ
0820 PORTJ
0830
LATJ
0840
ODCJ
0850 CNPUJ
0860 CNPDJ
0870 CNCONJ
0880 CNENJ
0890 CNSTATJ
Legend:
Note 1:
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
—
—
—
—
—
—
—
—
—
0000
ANSJ9
—
ANSJ8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0B00
0000
TRISJ9
—
TRISJ8
—
—
—
—
—
—
—
TRISJ4
—
—
—
TRISJ2
—
TRISJ1
—
—
—
RJ9
—
RJ8
—
—
—
—
—
—
—
RJ4
—
—
—
RJ2
—
RJ1
—
RJ0
—
xxxx
0000
LATJ11
—
—
—
LATJ9
—
LATJ8
—
—
—
—
—
—
—
LATJ4
—
—
—
LATJ2
—
LATJ1
—
LATJ0
—
xxxx
0000
—
—
ODCJ11
—
—
—
ODCJ9
—
ODCJ8
—
—
—
—
—
—
—
ODCJ4
—
—
—
ODCJ2
—
ODCJ1
—
ODCJ0 0000
—
0000
—
—
—
—
CNPUJ11
—
—
—
CNPUJ9
—
CNPUJ8
—
—
—
—
—
—
—
CNPUJ4
—
—
—
CNPUJ2 CNPUJ1 CNPUJ0 0000
—
—
—
0000
—
—
—
—
—
—
CNPDJ11
—
—
—
CNPDJ9
—
CNPDJ8
—
—
—
—
—
—
—
CNPDJ4
—
—
—
CNPDJ2 CNPDJ1 CNPDJ0 0000
—
—
—
0000
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEJ11
—
—
—
CNIEJ9
—
CNIEJ8
—
—
—
—
—
—
—
CNIEJ4
—
—
—
CNIEJ2
—
CNIEJ1
—
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
ANSJ11
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
TRISJ11
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
RJ11
—
15:0
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
15:0
31:16
—
—
15:0
31:16
15:0
31:16
25/9
TRISJ0 0B17
—
0000
—
—
0000
0000
CNIEJ0 0000
—
0000
CN
CN
CN
CN
CN
CN
CN
—
—
—
—
—
0000
STATJ11
STATJ9
STATJ8
STATJ4
STATJ2 STATJ1 STATJ0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
15:0
—
—
—
—
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 260
TABLE 12-18: PORTJ REGISTER MAP FOR 124-PIN DEVICES ONLY
0800 ANSELJ
0810
TRISJ
0820 PORTJ
0830
LATJ
0840
ODCJ
0850 CNPUJ
0860 CNPDJ
0870 CNCONJ
0880 CNENJ
0890 CNSTATJ
Legend:
Note 1:
31/15
30/14
29/13
28/12
31:16
—
—
—
15:0
31:16
—
—
—
—
—
—
TRISJ14
—
15:0 TRISJ15
31:16
—
27/11
26/10
—
—
—
—
—
ANSJ11
—
—
—
TRISJ13
—
TRISJ12
—
TRISJ11
—
TRISJ10
—
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
—
—
—
—
—
—
—
—
—
0000
ANSJ9
—
ANSJ8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0B00
0000
TRISJ9
—
TRISJ8
—
TRISJ7
—
TRISJ6
—
TRISJ5
—
TRISJ4
—
TRISJ3
—
TRISJ2
—
TRISJ1
—
25/9
TRISJ0 FFFF
—
0000
15:0
31:16
RJ15
—
RJ14
—
RJ13
—
RJ12
—
RJ11
—
RJ10
—
RJ9
—
RJ8
—
RJ7
—
RJ6
—
RJ5
—
RJ4
—
RJ3
—
RJ2
—
RJ1
—
RJ0
—
xxxx
0000
15:0
31:16
LATJ15
—
LATJ14
—
LATJ13
—
LATJ12
—
LATJ11
—
LATJ10
—
LATJ9
—
LATJ8
—
LATJ7
—
LATJ6
—
LATJ5
—
LATJ4
—
LATJ3
—
LATJ2
—
LATJ1
—
LATJ0
—
xxxx
0000
15:0 ODCJ15
31:16
—
ODCJ14
—
ODCJ13
—
ODCJ12
—
ODCJ11
—
ODCJ10
—
ODCJ9
—
ODCJ18
—
ODCJ7
—
ODCJ6
—
ODCJ5
—
ODCJ4
—
ODCJ3
—
ODCJ2
—
ODCJ1
—
ODCJ0 0000
—
0000
15:0 CNPUJ15 CNPUJ14 CNPUJ13 CNPUJ12 CNPUJ11 CNPUJ10
31:16
—
—
—
—
—
—
CNPUJ9
—
CNPUJ8
—
CNPUJ7
—
CNPUJ6
—
CNPUJ5 CNPUJ4 CNPUJ3 CNPUJ2 CNPUJ1 CNPUJ0 0000
—
—
—
—
—
—
0000
15:0 CNPDJ15 CNPDJ14 CNPDJ13 CNPDJ12 CNPDJ11 CNPDJ10
31:16
—
—
—
—
—
—
CNPDJ9
—
CNPDJ8
—
CNPDJ7
—
CNPDJ6
—
CNPDJ5 CNPDJ4 CNPDJ3 CNPDJ2 CNPDJ1 CNPDJ0 0000
—
—
—
—
—
—
0000
15:0
31:16
ON
—
15:0 CNIEJ15
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEJ14
—
CNIEJ13
—
CNIEJ12
—
CNIEJ11
—
CNIEJ10
—
CNIEJ9
—
CNIEJ8
—
CNIEJ7
—
CNIEJ6
—
CNIEJ5
—
CNIEJ4
—
CNIEJ3
—
CNIEJ2
—
CNIEJ1
—
—
—
0000
0000
CNIEJ0 0000
—
0000
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
0000
STATJ15 STATJ14 STATJ13 STATJ12 STATJ11 STATJ10 STATJ9
STATJ8
STATJ7
STATJ6 STATJ5 STATJ4 STATJ3 STATJ2 STATJ1 STATJ0
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
15:0
DS60001191F-page 261
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-19: PORTJ REGISTER MAP FOR 144-PIN DEVICES ONLY
Virtual Address
(BF86_#)
Register
Name(1)
0910
TRISK
0920 PORTK
0930
LATK
0940
ODCK
0950 CNPUK
0960 CNPDK
0970 CNCONK
0980 CNENK
0990 CNSTATK
Legend:
Note 1:
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
—
0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISK7
—
TRISK6
—
TRISK5
—
TRISK4
—
TRISK3
—
TRISK2
—
TRISK1
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RK7
—
RK6
—
RK5
—
RK4
—
RK3
—
RK2
—
RK1
—
RK0
—
xxxx
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATK7
—
LATK6
—
LATK5
—
LATK4
—
LATK3
—
LATK2
—
LATK1
—
LATK0
—
xxxx
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCK7
—
ODCK6
—
ODCK5
—
ODCK4
—
ODCK3
—
ODCK2
—
ODCK1
—
ODCK0 0000
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUK7
—
CNPUK6 CNPUK5 CNPUK4 CNPUK3 CNPUK2 CNPUK1 CNPUK0 0000
—
—
—
—
—
—
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDK7
—
CNPDK6 CNPDK5 CNPDK4 CNPDK3 CNPDK2 CNPDK1 CNPDK0 0000
—
—
—
—
—
—
—
0000
15:0
31:16
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEK7
—
CNIEK6
—
CNIEK5
—
CNIEK4
—
CNIEK3
—
CNIEK2
—
CNIEK1
—
CNIEK0 0000
—
0000
15:0
—
—
—
—
—
—
—
—
CN
STATK7
CN
STATK6
CN
STATK5
CN
STATK4
CN
STATK3
CN
STATK2
CN
STATK1
CN
0000
STATK0
TRISK0 00FF
—
0000
—
—
0000
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 262
TABLE 12-20: PORTK REGISTER MAP FOR 144-PIN DEVICES ONLY
INT1R
1408
INT2R
140C
INT3R
1410
INT4R
1418
T2CKR
141C
T3CKR
1420
T4CKR
1424
T5CKR
1428
T6CKR
142C
T7CKR
1430
T8CKR
1434
T9CKR
1438
IC1R
143C
IC2R
1440
IC3R
Legend:
Note 1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
INT1R<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IC3R<3:0>
0000
0000
—
IC2R<3:0>
—
0000
0000
IC1R<3:0>
—
0000
0000
T9CKR<3:0>
—
0000
0000
T8CKR<3:0>
—
0000
0000
T7CKR<3:0>
—
0000
0000
T6CKR<3:0>
—
0000
0000
T5CKR<3:0>
—
0000
0000
T4CKR<3:0>
—
0000
0000
T3CKR<3:0>
—
0000
0000
T2CKR<3:0>
—
0000
0000
INT4R<3:0>
—
0000
0000
INT3R<3:0>
—
0000
0000
INT2R<3:0>
—
All Resets
1404
Bit Range
Register
Name
DS60001191F-page 263
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP
IC4R
1448
IC5R
144C
IC6R
1450
IC7R
1454
IC8R
1458
IC9R
1460
OCFAR
1468
U1RXR
146C
U1CTSR
1470
U2RXR
1474
U2CTSR
1478
U3RXR
147C
U3CTSR
1480
U4RXR
1484
U4CTSR
Legend:
Note 1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
IC4R<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U4CTSR<3:0>
0000
0000
—
U4RXR<3:0>
—
0000
0000
U3CTSR<3:0>
—
0000
0000
U3RXR<3:0>
—
0000
0000
U2CTSR<3:0>
—
0000
0000
U2RXR<3:0>
—
0000
0000
U1CTSR<3:0>
—
0000
0000
U1RXR<3:0>
—
0000
0000
OCFAR<3:0>
—
0000
0000
IC9R<3:0>
—
0000
0000
IC8R<3:0>
—
0000
0000
IC7R<3:0>
—
0000
0000
IC6R<3:0>
—
0000
0000
IC5R<3:0>
—
All Resets
1444
Bit Range
Register
Name
 2013-2016 Microchip Technology Inc.
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 264
TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
U5RXR
148C
U5CTSR
1490
U6RXR
1494
U6CTSR
149C
SDI1R
14A0
SS1R
14A8
SDI2R
14AC
SS2R
14B4
SDI3R
14B8
SS3R
14C0
SDI4R
14C4
SS4R
14CC
SDI5R(1)
14D0
SS5R(1)
14D8
SDI6R(1)
Legend:
Note 1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
U5RXR<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI6R<3:0>
0000
0000
—
SS5R<3:0>
—
0000
0000
SDI5R<3:0>
—
0000
0000
SS4R<3:0>
—
0000
0000
SDI4R<3:0>
—
0000
0000
SS3R<3:0>
—
0000
0000
SDI3R<3:0>
—
0000
0000
SS2R<3:0>
—
0000
0000
SDI2R<3:0>
—
0000
0000
SS1R<3:0>
—
0000
0000
SDI1R<3:0>
—
0000
0000
U6CTSR<3:0>
—
0000
0000
U6RXR<3:0>
—
0000
0000
U5CTSR<3:0>
—
All Resets
1488
Bit Range
Register
Name
DS60001191F-page 265
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
SS6R(1)
14E0
C1RXR(2)
14E4
C2RXR(2)
14E8
REFCLKI1R
14F0
REFCLKI3R
14F4
REFCLKI4R
Legend:
Note 1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
SS6R<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REFCLKI4R<3:0>
0000
0000
—
REFCLKI3R<3:0>
—
0000
0000
REFCLKI1R<3:0>
—
0000
0000
C2RXR<3:0>
—
0000
0000
C1RXR<3:0>
—
All Resets
Register
Name
14DC
Bit Range
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 266
TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
DS60001191F-page 267
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
(1) 31:16
153C RPA15R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1540 RPB0R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1544 RPB1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1548 RPB2R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
154C RPB3R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1554 RPB5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1558 RPB6R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
155C RPB7R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1560 RPB8R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1564 RPB9R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1568 RPB10R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1578 RPB14R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
157C RPB15R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1584 RPC1R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1588 RPC2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
(1)
158C RPC3R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1590 RPC4R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not available on 64-pin devices.
2:
This register is not available on 64-pin and 100-pin devices.
1538
RPA14R(1)
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
RPA14R<3:0>
—
—
RPA15R<3:0>
—
—
RPB0R<3:0>
—
—
RPB1R<3:0>
—
—
RPB2R<3:0>
—
—
RPB3R<3:0>
—
—
RPB5R<3:0>
—
—
RPB6R<3:0>
—
—
RPB7R<3:0>
—
—
RPB8R<3:0>
—
—
RPB9R<3:0>
—
—
RPB10R<3:0>
—
—
RPB14R<3:0>
—
—
RPB15R<3:0>
—
—
RPC1R<3:0>
—
—
RPC2R<3:0>
—
—
RPC3R<3:0>
—
—
RPC4R<3:0>
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
 2013-2016 Microchip Technology Inc.
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15B8 RPC14R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15C0 RPD0R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15C4 RPD1R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15C8 RPD2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15CC RPD3R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15D0 RPD4R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15D4 RPD5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
(2)
15D8 RPD6R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(2)
15DC RPD7R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15E4 RPD9R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15E8 RPD10R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15EC RPD11R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
15F0 RPD12R
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
(1) 31:16
15F8 RPD14R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
15FC RPD15R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
160C RPE3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1614 RPE5R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not available on 64-pin devices.
2:
This register is not available on 64-pin and 100-pin devices.
15B4
RPC13R
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
RPC13R<3:0>
—
—
RPC14R<3:0>
—
—
RPD0R<3:0>
—
—
RPD1R<3:0>
—
—
RPD2R<3:0>
—
—
RPD3R<3:0>
—
—
RPD4R<3:0>
—
—
RPD5R<3:0>
—
—
RPD6R<3:0>
—
—
RPD7R<3:0>
—
—
RPD9R<3:0>
—
—
RPD10R<3:0>
—
—
RPD11R<3:0>
—
—
RPD12R<3:0>
—
—
RPD14R<3:0>
—
—
RPD15R<3:0>
—
—
RPE3R<3:0>
—
—
RPE5R<3:0>
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 268
TABLE 12-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
DS60001191F-page 269
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1624 RPE9R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1640 RPF0R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1644 RPF1R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1648 RPF2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
164C RPF3R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1650 RPF4R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1654 RPF5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
(1)
1660 RPF8R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1670 RPF12R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1674 RPF13R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
(1)
1680 RPG0R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
(1)
1684 RPG1R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
1698 RPG6R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
169C RPG7R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
16A0 RPG8R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
16A4 RPG9R
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not available on 64-pin devices.
2:
This register is not available on 64-pin and 100-pin devices.
1620
RPE8R(1)
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
RPE8R<3:0>
—
—
RPE9R<3:0>
—
—
RPF0R<3:0>
—
—
RPF1R<3:0>
—
—
RPF2R<3:0>
—
—
RPF3R<3:0>
—
—
RPF4R<3:0>
—
—
RPF5R<3:0>
—
—
RPF8R<3:0>
—
—
RPG12R<3:0>
—
—
RPG0R<3:0>
—
—
RPG1R<3:0>
—
—
RPG1R<3:0>
—
—
RPG6R<3:0>
—
—
RPG7R<3:0>
—
—
RPG8R<3:0>
—
—
RPG9R<3:0>
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 12-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 12-1:
Bit
Range
31:24
23:16
15:8
7:0
[pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
[pin name]R<3:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
[pin name]R<3:0>: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 12-1 for
input pin selection values.
Note:
Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
REGISTER 12-2:
Bit
Range
31:24
23:16
15:8
7:0
RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RPnR<3:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
RPnR<3:0>: Peripheral Pin Select Output bits
See Table 12-2 for output pin selection values.
Note:
x = Bit is unknown
Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
DS60001191F-page 270
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 12-3:
Bit
Range
31:24
23:16
15:8
7:0
CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – G)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = CPU Idle mode halts CN operation
0 = CPU Idle mode does not affect CN operation
bit 12-0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 271
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 272
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
13.0
Note:
TIMER1
The following modes are supported by Timer1:
•
•
•
•
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
13.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a real-time clock
• ADC event trigger
PIC32MZ EC devices feature one synchronous/asynchronous 16-bit timer that can operate as a free-running
interval timer for various timing applications and counting
external events. This timer can also be used with the
Low-Power Secondary Oscillator (SOSC) for real-time
clock applications.
FIGURE 13-1:
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
TIMER1 BLOCK DIAGRAM
PR1
Equal
Trigger to ADC
16-bit Comparator
TSYNC
1
Sync
TMR1
Reset
T1IF
Event Flag
0
0
1
Q
TGATE
D
Q
TCS
TGATE
ON
SOSCO/T1CK
x1
SOSCEN(1)
Gate
Sync
10
Prescaler
1, 8, 64, 256
SOSCI
PBCLK3
00
2
TCKPS<1:0>
Note 1:
The default state of the SOSCEN bit (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit
in Configuration Word, DEVCFG1.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 273
Timer1 Control Register
Virtual Address
(BF84_#)
TABLE 13-1:
TIMER1 REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
—
TGATE
—
—
21/5
20/4
All Resets
Bit Range
Register
Name(1)
Bits
19/3
18/2
17/1
16/0
—
—
TCKPS<1:0>
—
—
—
TSYNC
—
TCS
—
—
0000
0000
0000 T1CON
31:16
15:0
—
ON
—
—
—
SIDL
—
TWDIS
—
TWIP
—
—
—
—
—
—
0010
TMR1
31:16
15:0
—
—
—
—
—
—
—
—
—
TMR1<15:0>
—
—
—
—
—
—
—
0000
0000
0020
PR1
31:16
15:0
—
—
—
—
—
—
—
—
—
PR1<15:0>
—
—
—
—
—
—
—
0000
FFFF
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 274
13.2
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 13-1:
Bit
Range
31:24
23:16
15:8
7:0
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
U-0
U-0
ON
—
SIDL
TWDIS
TWIP
—
—
—
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
—
TSYNC
TCS
—
TCKPS<1:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
bit 12
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
TCKPS<1:0>: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 275
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 13-1:
T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer Clock Source Select bit
1 = External clock from T1CKI pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
DS60001191F-page 276
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
14.0
Note:
TIMER2/3, TIMER4/5, TIMER6/7,
AND TIMER8/9
Four 32-bit synchronous timers are available by
combining Timer2 with Timer3, Timer4 with Timer5,
Timer6 with Timer7, and Timer8 with Timer9.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The 32-bit timers can operate in one of three modes:
• Synchronous internal 32-bit timer
• Synchronous internal 32-bit gated timer
• Synchronous external 32-bit timer
14.1
Additional Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare
modules (Timer2 through Timer7 only)
• ADC event trigger (Timer3 and Timer5 only)
• Fast bit manipulation using CLR, SET, and INV
registers
This family of devices features eight synchronous
16-bit timers (default) that can operate as a freerunning interval timer for various timing applications
and counting external events.
The following modes are supported:
• Synchronous internal 16-bit timer
• Synchronous internal 16-bit gated timer
• Synchronous external 16-bit timer
FIGURE 14-1:
TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16-BIT)
Reset
Trigger to ADC (1)
Equal
Sync
TMRx
Comparator x 16
PRx
TxIF Event Flag
0
1
Q
TGATE
D
Q
TCS
TGATE
ON
TxCK
x1
Gate
Sync
PBCLK3
Note
1:
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS
The ADC event trigger is available on Timer3 and Timer5 only.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 277
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 14-2:
TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 BLOCK DIAGRAM (32-BIT)
Reset
TMRy(2)
MS Half Word
ADC Event Trigger(1)
TMRx(2)
LS Half Word
32-bit Comparator
Equal
PRy(2)
TyIF Event Flag(2)
Sync
PRx(2)
0
1
Q
D
TGATE
Q
TCS
TGATE
ON
TxCK(2)
x1
Gate
Sync
PBCLK3
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
10
00
3
TCKPS
Note
1:
2:
ADC event trigger is available only on the Timer2/3 and TImer4/5 pairs.
In this diagram, ‘x’ represents Timer2, 4, 6, or 8, and ‘y’ represents Timer3, 5, 7, or 9.
DS60001191F-page 278
 2013-2016 Microchip Technology Inc.
Timer2-Timer9 Control Registers
Virtual Address
(BF84_#)
TABLE 14-1:
TMR2
0220
PR2
0400 T3CON
0410
TMR3
0420
PR3
0600 T4CON
0610
TMR4
0620
PR4
0800 T5CON
0810
TMR5
0820
PR5
0A00 T6CON
0A10 TMR6
DS60001191F-page 279
0A20
PR6
0C00 T7CON
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
15:0
31:16
ON
—
15:0
31:16
23/7
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
—
—
TCKPS<2:0>
—
—
—
—
T32
—
—
—
—
—
—
—
—
TMR2<15:0>
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
PR2<15:0>
—
—
—
—
15:0
31:16
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
TMR3<15:0>
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
ON
—
—
—
SIDL
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
15:0
31:16
—
—
—
—
15:0
31:16
ON
—
—
—
SIDL
—
15:0
31:16
—
—
15:0
31:16
—
15:0
31:16
All Resets
Bit Range
Register
Name(1)
Bits
0200 T2CON
0210
TIMER2 THROUGH TIMER9 REGISTER MAP
17/1
16/0
—
—
—
0000
—
—
TCS
—
—
—
0000
0000
—
—
—
—
0000
0000
—
—
—
—
—
FFFF
0000
TCKPS<2:0>
—
—
—
—
—
—
TCS
—
—
—
0000
0000
—
—
—
—
—
—
—
0000
0000
PR3<15:0>
—
—
—
—
—
—
—
—
—
FFFF
0000
—
—
—
—
—
TCKPS<2:0>
—
—
T32
—
—
—
TCS
—
—
—
0000
0000
—
—
TMR4<15:0>
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
PR4<15:0>
—
—
—
—
—
—
—
—
—
FFFF
0000
—
—
—
—
—
—
—
—
—
—
—
TCKPS<2:0>
—
—
—
—
—
—
TCS
—
—
—
0000
0000
—
—
—
—
—
TMR5<15:0>
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
PR5<15:0>
—
—
—
—
—
—
—
—
—
FFFF
0000
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
TCKPS<2:0>
—
—
T32
—
—
—
TCS
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
TMR2<15:0>
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
PR2<15:0>
—
—
—
—
—
—
—
—
—
FFFF
0000
—
—
TCS
—
0000
TGATE
—
TGATE
—
TGATE
—
TGATE
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TCKPS<2:0>
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
14.2
Virtual Address
(BF84_#)
TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
0C10 TMR7
31:16
15:0
—
—
—
—
—
—
—
—
—
TMR3<15:0>
—
—
—
—
—
—
—
0000
0000
0C20
31:16
15:0
—
—
—
—
—
—
—
—
—
PR3<15:0>
—
—
—
—
—
—
—
0000
FFFF
0E00 T8CON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
TCKPS<2:0>
—
—
T32
—
—
—
TCS
—
—
0000
0000
0E10 TMR8
31:16
15:0
—
—
—
—
—
—
—
—
—
TMR4<15:0>
—
—
—
—
—
—
—
0000
0000
0E20
31:16
15:0
—
—
—
—
—
—
—
—
—
PR4<15:0>
—
—
—
—
—
—
—
0000
FFFF
1000 T9CON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
TCKPS<2:0>
—
—
—
—
—
—
TCS
—
—
0000
0000
1010
TMR9
31:16
15:0
—
—
—
—
—
—
—
—
—
TMR5<15:0>
—
—
—
—
—
—
—
0000
0000
1020
PR9
31:16
15:0
—
—
—
—
—
—
—
—
—
PR5<15:0>
—
—
—
—
—
—
—
0000
FFFF
PR7
PR8
Legend:
Note 1:
—
TGATE
—
TGATE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 280
TABLE 14-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 14-1:
Bit
Range
31:24
23:16
TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON(1)
—
SIDL(2)
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
7:0
TGATE(1)
T32(3)
—
TCS(1)
—
TCKPS<2:0>(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1)
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit(2)
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4
TCKPS<2:0>: Timer Input Clock Prescale Select bits(1)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
bit 3
T32: 32-Bit Timer Mode Select bit(3)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
Note 1:
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5,
Timer7, and Timer9). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).
2:
3:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 281
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 14-1:
TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9) (CONTINUED)
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timer Clock Source Select bit(1)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1:
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5,
Timer7, and Timer9). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).
2:
3:
DS60001191F-page 282
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
15.0
DEADMAN TIMER (DMT)
Note:
The primary function of the Deadman Timer (DMT) is
to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch
timer, which is clocked whenever an instruction fetch
occurs until a count match occurs. Instructions are not
fetched when the processor is in Sleep mode.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog, Deadman, and
Power-up Timers” (DS60001114), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The DMT consists of a 32-bit counter with a time-out
count match value as specified by the DMTCNT<3:0>
bits in the DEVCFG1 Configuration register.
A Deadman Timer is typically used in mission critical
and safety critical applications, where any single failure of the software functionality and sequencing must
be detected.
Figure 15-1 shows a block diagram of the Deadman
Timer module.
FIGURE 15-1:
DEADMAN TIMER BLOCK DIAGRAM
“improper sequence” flag
ON
Instruction Fetched Strobe
Force DMT Event
System Reset
Counter Initialization Value
PBCLK7
Clock
“Proper Clear Sequence” Flag
ON
32-bit counter
ON
32
DMT event
to NMI(3)
DMT Count Reset Load
System Reset
(COUNTER) = DMT Max Count(1)

(COUNTER)  DMT Window Interval(2)
Window Interval Open
Note
1:
2:
3:
DMT Max Count is controlled by the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.
DMT Window Interval is controlled by the DMTINTV<2:0> bits in the DEVCFG1 Configuration register.
Refer to Section 6.0 “Resets” for more information.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 283
Deadman Timer Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 15-1:
0A00
DMTCON
DEADMAN TIMER REGISTER MAP
0A10 DMTPRECLR
0A20
DMTCLR
0A30
DMTSTAT
0A40
DMTCNT
0A60
DMTPSCNT
0A70
DMTPSINTV
Legend:
All Resets
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x000
0000
15:0
31:16
—
—
—
STEP1<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STEP2<7:0>
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
BAD1
BAD2
DMTEVENT
—
—
—
15:0
31:16
15:0
31:16
COUNTER<31:0>
PSCNT<31:0>
PSINTV<31:0>
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
WINOPN 0000
0000
0000
0000
00xx
0000
000x
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 284
15.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 15-1:
Bit Range
DMTCON: DEADMAN TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
ON
7:0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Deadman Timer Module Enable bit(1)
1 = Deadman Timer module is enabled
0 = Deadman Timer module is disabled
bit 13-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
This bit only has control when FDMTEN (DEVCFG1<3>) = 0.
REGISTER 15-2:
Bit Range
DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP1<7:0>
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-8
STEP1<7:0>: Preclear Enable bits
01000000 = Enables the Deadman Timer Preclear (Step 1)
All other write patterns = Set BAD1 flag.
These bits are cleared when a DMT reset event occurs. STEP1<7:0> is also cleared if the
STEP2<7:0> bits are loaded with the correct value in the correct sequence.
bit 7-0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 285
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 15-3:
Bit Range
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
DMTCLR: DEADMAN TIMER CLEAR REGISTER
Bit
31/23/15/7
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP2<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7-0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
STEP2<7:0>: Clear Timer bits
00001000 = Clears STEP1<7:0>, STEP2<7:0> and the Deadman Timer if, and only if, preceded by correct loading of STEP1<7:0> bits in the correct sequence. The write to these bits may be
verified by reading DMTCNT and observing the counter being reset.
All other write patterns = Set BAD2 bit, the value of STEP1<7:0> will remain unchanged, and the new
value being written STEP2<7:0> will be captured. These bits are also cleared when a DMT reset event
occurs.
DS60001191F-page 286
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 15-4:
Bit Range
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
DMTSTAT: DEADMAN TIMER STATUS REGISTER
Bit
31/23/15/7
bit 6
bit 5
bit 4-1
bit 0
Bit
Bit
25/17/9/1 24/16/8/0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HC
R-0, HC
R-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R-0
BAD1
BAD2
DMTEVENT
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
WINOPN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
BAD1: Bad STEP1<7:0> Value Detect bit
1 = Incorrect STEP1<7:0> value was detected
0 = Incorrect STEP1<7:0> value was not detected
BAD2: Bad STEP2<7:0> Value Detect bit
1 = Incorrect STEP2<7:0> value was detected
0 = Incorrect STEP2<7:0> value was not detected
DMTEVENT: Deadman Timer Event bit
1 = Deadman timer event was detected (counter expired or bad STEP1<7:0> or STEP2<7:0> value was
entered prior to counter increment)
0 = Deadman timer even was not detected
Unimplemented: Read as ‘0’
WINOPN: Deadman Timer Clear Window bit
1 = Deadman timer clear window is open
0 = Deadman timer clear window is not open
 2013-2016 Microchip Technology Inc.
DS60001191F-page 287
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 15-5:
Bit Range
DMTCNT: DEADMAN TIMER COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER<15:8>
R-0
7:0
R-0
R-0
R-0
R-0
COUNTER<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
COUNTER<31:0>: Read current contents of DMT counter
REGISTER 15-6:
DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-y
R-y
R-y
PSCNT<31:24>
R-0
23:16
R-0
R-0
R-0
R-0
PSCNT<23:16>
R-0
15:8
R-0
R-0
R-0
R-0
PSCNT<15:8>
R-0
7:0
R-0
R-0
R-y
R-y
PSCNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
R-0
Bit
24/16/8/0
COUNTER<23:16>
15:8
Bit Range
R-0
Bit
25/17/9/1
COUNTER<31:24>
23:16
bit 31-8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
y = Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PSCNT<31:0>: DMT Instruction Count Value Configuration Status bits
This is always the value of the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.
DS60001191F-page 288
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 15-7:
Bit Range
DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-y
R-y
R-y
PSINTV<31:24>
R-0
23:16
R-0
R-0
R-0
R-0
PSINTV<23:16>
R-0
15:8
R-0
R-0
R-0
R-0
PSINTV<15:8>
R-0
7:0
R-0
R-0
R-0
R-0
PSINTV<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
y = Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PSINTV<31:0>: DMT Window Interval Configuration Status bits
This is always the value of the DMTINTV<2:0> bits in the DEVCFG1 Configuration register.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 289
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 290
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
16.0
WATCHDOG TIMER (WDT)
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog, Deadman, and
Power-up Timers” (DS60001114), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
FIGURE 16-1:
When enabled, the Watchdog Timer (WDT) operates
from the internal Low-Power Oscillator (LPRC) clock
source and can be used to detect system software malfunctions by resetting the device if the WDT is not
cleared periodically in software. Various WDT time-out
periods can be selected using the WDT postscaler. The
WDT can also be used to wake the device from Sleep
or Idle mode.
Some of the key features of the WDT module are:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
WATCHDOG TIMER BLOCK DIAGRAM
LPRC
ON
Clock
25-bit Counter
WDTCLR = 1
ON
Wake
25
0
WDT Counter Reset
ON
Reset Event
1
WDT Event
to NMI(1)
Power Save
Decoder
FWDTPS<4:0> (DEVCFG1<20:16>)
Note 1:
Refer to Section 6.0 “Resets” for more information.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 291
Watchdog Timer Control Registers
Register
Name
Bit Range
WATCHDOG TIMER REGISTER MAP
Virtual Address
(BF80_#)
TABLE 16-1:
0800
WDTCON(1)
31:16
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
WDTCLRKEY<15:0>
15:0
ON
—
—
—
—
—
—
—
—
SWDTPS<4:0>
WDTWINEN
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
All Resets
Bits
0000
x0xx
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 292
16.1
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 16-1:
Bit
Range
31:24
23:16
15:8
7:0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
WDTCLRKEY<15:8>
W-0
W-0
W-0
W-0
W-0
WDTCLRKEY<7:0>
R/W-y
U-0
U-0
U-0
U-0
U-0
U-0
U-0
ON(1)
—
—
—
—
—
—
—
U-0
R-y
R-y
R-y
R-y
R-y
R/W-0
U-0
WDTWINEN
—
—
SWDTPS<4:0>
Legend:
y = Values set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 WDTCLRKEY<15:0>: Watchdog Timer Clear Key bits
To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to this location
using a single 16-bit write.
bit 15
ON: Watchdog Timer Enable bit(1)
1 = The WDT is enabled
0 = The WDT is disabled
bit 14-7
Unimplemented: Read as ‘0’
bit 6-2
SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> Configuration bits in DEVCFG1.
bit 1
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
bit 0
Unimplemented: Read as ‘0’
Note 1:
This bit only has control when FWDTEN (DEVCFG1<23>) = 0.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 293
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 294
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
17.0
INPUT CAPTURE
Note:
Capture events are caused by the following:
• Capture timer value on every edge (rising and falling),
specified edge first
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
15.
“Input
Capture”
(DS60001122), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Each input capture channel can select between one of
six 16-bit timers for the time base, or two of six 16-bit
timers together to form a 32-bit timer. The selected
timer can use either an internal or external clock.
Other operational features include:
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values; Interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled
• Input capture can also be used to provide additional
sources of external interrupts
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin.
FIGURE 17-1:
INPUT CAPTURE BLOCK DIAGRAM
FEDGE
Specified/Every
Edge Mode
ICM<2:0>
110
PBCLK3
Prescaler Mode
(16th Rising Edge)
101
Prescaler Mode
(4th Rising Edge)
100
Rising Edge Mode
011
Timerx(2)
Timery(2)
C32/ICTMR
CaptureEvent
To CPU
FIFO Control
ICx(1)
ICxBUF(1)
Falling Edge Mode
010
Edge Detection
Mode
001
FIFO
ICI<1:0>
ICM<2:0>
Set Flag ICxIF(1)
(In IFSx Register)
/N
Sleep/Idle
Wake-up Mode
001
111
Note
1:
An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2:
See Table 17-1 for Timerx and Timery selections.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 295
PIC32MZ Embedded Connectivity (EC) Family
The timer source for each Input Capture module
depends on the setting of the ICACLK bit in the
CFGCON register. The available configurations are
shown in Table 17-1.
TABLE 17-1:
TIMER SOURCE
CONFIGURATIONS
Input Capture
Module
Timerx
Timery
ICACLK (CFGCON<17>) = 0
IC1
Timer2
Timer3
•
•
•
•
•
•
•
•
•
IC9
Timer 2
Timer 3
ICACLK (CFGCON<17>) = 1
IC1
Timer4
Timer5
IC2
Timer4
Timer5
IC3
Timer4
Timer5
IC4
Timer2
Timer3
IC5
Timer2
Timer3
IC6
Timer2
Timer3
IC7
Timer6
Timer7
IC8
Timer6
Timer7
IC9
Timer6
Timer7
DS60001191F-page 296
 2013-2016 Microchip Technology Inc.
Input Capture Control Registers
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP
2000 IC1CON(1)
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001191F-page 297
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2010 IC1BUF
IC1BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2200 IC2CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2210 IC2BUF
IC2BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2400 IC3CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2410 IC3BUF
IC3BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2600 IC4CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2610 IC4BUF
IC4BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2800 IC5CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2810 IC5BUF
IC5BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2A00 IC6CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2A10 IC6BUF
IC6BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2C00 IC7CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2C10 IC7BUF
IC7BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2E00 IC8CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
2E10 IC8BUF
IC8BUF<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3000 IC9CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
3010 IC9BUF
IC9BUF<31:0>
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF84_#)
TABLE 17-2:
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
17.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 17-1:
Bit Range
31:24
23:16
15:8
7:0
ICXCON: INPUT CAPTURE X CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
bit 14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ON
—
SIDL
—
—
—
FEDGE
C32
R/W-0
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
ICOV
ICBNE
ICTMR
ICI<1:0>
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-16
bit 15
Bit
25/17/9/1
ICM<2:0>
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
Unimplemented: Read as ‘0’
ON: Input Capture Module Enable bit
1 = Module enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1 = Capture rising edge first
0 = Capture falling edge first
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)(1)
0 = Timery is the counter source for capture
1 = Timerx is the counter source for capture
ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
ICM<2:0>: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
Refer to Table 17-1 for Timerx and Timery selections.
DS60001191F-page 298
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
18.0
OUTPUT COMPARE
Note:
When a match occurs, the Output Compare module
generates an event based on the selected mode of
operation.
This data sheet summarizes the
features of the PIC32MZ Embedded
Connectivity (EC) Family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
16.
“Output
Compare”
(DS60001111), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The following are some of the key features:
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
• ADC event trigger
The Output Compare module is used to generate a
single pulse or a train of pulses in response to selected
time base events.
For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the
OCxRS registers to the value in the selected timer.
FIGURE 18-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
Trigger to ADC(4)
Output
Logic
OCxR(1)
3
OCM<2:0>
Mode Select
Comparator
0
16
PBCLK3
Timerx(3)
OCTSEL
1
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or
OCFB(2)
1
16
Timery(3)
Timerx(3)
Rollover
Timery(3)
Rollover
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 9.
2: The OCFA pin controls the OC1-OC3, and OC7-OC9 channels. The OCFB pin controls the OC4-OC6 channels.
3: Refer to Table 18-1 for Timerx and Timery selections.
4: The ADC event trigger is only available on OC1,OC3, and OC5.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 299
PIC32MZ Embedded Connectivity (EC) Family
The timer source for each Output Compare module
depends on the setting of the OCACLK bit in the
CFGCON register. The available configurations are
shown in Table 18-1.
TABLE 18-1:
TIMER SOURCE
CONFIGURATIONS
Output
Compare
Module
Timerx
Timery
OCACLK (CFGCON<16>) = 0
OC1
Timer2
Timer3
•
•
•
•
•
•
•
•
•
OC9
Timer 2
Timer 3
OCACLK (CFGCON<16>) = 1
OC1
Timer4
Timer5
OC2
Timer4
Timer5
OC3
Timer4
Timer5
OC4
Timer2
Timer3
OC5
Timer2
Timer3
OC6
Timer2
Timer3
OC7
Timer6
Timer7
OC8
Timer6
Timer7
OC9
Timer6
Timer7
DS60001191F-page 300
 2013-2016 Microchip Technology Inc.
Output Compare Control Registers
Virtual Address
(BF84_#)
TABLE 18-2:
4010
OC1R
4020
OC1RS
4200 OC2CON
4210
OC2R
4220
OC2RS
4400 OC3CON
4410
OC3R
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
31:16
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
15:0
31:16
15:0
31:16
4610
OC4R
DS60001191F-page 301
4810
OC5R
4820
OC5RS
Legend:
Note 1:
18/2
—
—
—
OCFLT
OCTSEL
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
16/0
—
—
OCM<2:0>
—
—
—
OCM<2:0>
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
—
—
—
OCM<2:0>
xxxx
xxxx
OC3RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
—
—
—
OCM<2:0>
xxxx
0000
0000
xxxx
OC4R<31:0>
xxxx
xxxx
OC4RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
OC5RS<31:0>
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
0000
0000
xxxx
OC3R<31:0>
OC5R<31:0>
xxxx
0000
0000
xxxx
OC2RS<31:0>
15:0
0000
0000
xxxx
OC2R<31:0>
15:0
15:0
31:16
17/1
xxxx
xxxx
—
31:16
OC4RS
15:0
4800 OC5CON
19/3
OC1RS<31:0>
15:0
31:16
15:0
31:16
20/4
OC1R<31:0>
15:0
31:16
15:0
31:16
21/5
All Resets
31/15
31:16
OC3RS
15:0
4600 OC4CON
4620
Bit Range
Register
Name(1)
Bits
4000 OC1CON
4420
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP
—
—
OCM<2:0>
—
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
18.1
Virtual Address
(BF84_#)
4A10
OC6R
4A20
OC6RS
4C00 OC7CON
4C10
OC7R
4C20 OC7RS
4E00 OC8CON
4E10
OC8R
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
31:16
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
15:0
31:16
15:0
31:16
5010
—
—
—
OCFLT
OCTSEL
17/1
16/0
—
—
OCM<2:0>
—
—
—
—
—
—
—
—
—
—
—
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
0000
xxxx
—
—
—
OCM<2:0>
xxxx
0000
0000
xxxx
OC7R<31:0>
xxxx
xxxx
OC7RS<31:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
—
—
—
OCM<2:0>
xxxx
0000
0000
xxxx
OC8R<31:0>
15:0
0000
xxxx
xxxx
—
xxxx
xxxx
OC8RS<31:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
 2013-2016 Microchip Technology Inc.
OC9R<31:0>
15:0
31:16
5020 OC9RS
OC9RS<31:0>
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
OC9R
18/2
—
31:16
OC8RS
15:0
5000 OC9CON
19/3
OC6RS<31:0>
15:0
31:16
15:0
31:16
20/4
OC6R<31:0>
15:0
31:16
15:0
31:16
21/5
All Resets
Bit Range
Register
Name(1)
Bits
4A00 OC6CON
4E20
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP (CONTINUED)
—
—
OCM<2:0>
—
xxxx
0000
0000
xxxx
xxxx
xxxx
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 302
TABLE 18-2:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 18-1:
Bit
Range
31:24
23:16
15:8
7:0
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OC32
OCFLT(1)
OCTSEL(2)
OCM<2:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Peripheral On bit
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode
bit 12-6
Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(1)
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
bit 3
OCTSEL: Output Compare Timer Select bit(2)
1 = Timery is the clock source for this Output Compare module
0 = Timerx is the clock source for this Output Compare module
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1:
2:
This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.
Refer to Table 18-1 for Timerx and Timery selections.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 303
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 304
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
The SPI/I2S module is compatible with Motorola® SPI
and SIOP interfaces.
19.0 SERIAL PERIPHERAL
INTERFACE (SPI) AND
INTER-IC SOUND (I 2S)
Note:
The following are some of the key features of the SPI
module:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 23.
“Serial Peripheral Interface (SPI)”
(DS60001106), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
•
•
•
•
•
Master and Slave modes support
Four different clock formats
Enhanced Framed SPI protocol support
User-configurable 8-bit, 16-bit and 32-bit data width
Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit, 
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio Codec Support:
- I2S protocol
- Left-justified
- Right-justified
- PCM
The SPI/I2S module is a synchronous serial interface
that is useful for communicating with external
peripherals and other microcontroller devices, as well
as digital audio devices. These peripheral devices may
be Serial EEPROMs, Shift registers, display drivers,
Analog-to-Digital Converters (ADC), etc.
SPI/I2S MODULE BLOCK DIAGRAM
FIGURE 19-1:
Internal
Data Bus
SPIxBUF
Read
Write
FIFOs Share Address SPIxBUF
SPIxRXB FIFO
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
MCLKSEL
Edge
Select
REFCLKO1
Baud Rate
Generator
SCKx
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
 2013-2016 Microchip Technology Inc.
PBCLK2
MSTEN
DS60001191F-page 305
SPI Control Registers
SPI1 THROUGH SPI6 REGISTER MAP
1000 SPI1CON
1010 SPI1STAT
1020 SPI1BUF
1030 SPI1BRG
1040 SPI1CON2
1200 SPI2CON
1210 SPI2STAT
1220 SPI2BUF
1230 SPI2BRG
1240 SPI2CON2
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
31:16
ON
—
—
—
SIDL
—
DISSDO
MODE32 MODE16
SMP
RXBUFELM<4:0>
15:0
31:16
—
—
—
FRMERR
SPIBUSY
24/8
FRMCNT<2:0>
—
—
20/4
19/3
18/2
17/1
—
—
SPIFE
—
—
—
CKP
—
MSTEN
—
DISSDI
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
SPI
—
—
SGNEXT
31:16 FRMEN FRMSYNC FRMPOL
FRM
ERREN
MSSEN
15:0
31:16
ON
—
—
—
SIDL
—
DISSDO
MODE32 MODE16
SMP
RXBUFELM<4:0>
15:0
31:16
—
—
—
FRMERR
SPIBUSY
BRG<12:0>
—
SPI
SPI
IGNROV IGNTUR AUDEN
ROVEN
TUREN
FRMSYPW
FRMCNT<2:0>
MCLKSEL
—
—
—
ENHBUF 0000
STXISEL<1:0>
SRXISEL<1:0>
TXBUFELM<4:0>
DATA<31:0>
15:0
16/0
SSEN
—
—
AUD
MONO
—
—
—
SPIRBF 0008
0000
AUDMOD<1:0>
—
—
—
CKE
SSEN
—
CKP
—
MSTEN
—
DISSDI
SPIFE
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
0000
ENHBUF 0000
STXISEL<1:0>
SRXISEL<1:0>
TXBUFELM<4:0>
DATA<31:0>
0000
0000
0000
0000
SPIRBF 0008
0000
 2013-2016 Microchip Technology Inc.
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
0000
0000
15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
—
—
—
AUD
MONO
—
MCLKSEL
SSEN
—
CKP
—
MSTEN
—
DISSDI
—
SRMT
—
SPIROV
—
SPIRBE
—
31:16
15:0
1420 SPI3BUF
31:16
15:0
1430 SPI3BRG
31:16
15:0
31:16
Note 1:
21/5
MCLKSEL
15:0
31:16
1410 SPI3STAT
—
—
—
—
—
—
FRMERR
RXBUFELM<4:0>
SPIBUSY
—
—
SPITUR
—
—
STXISEL<1:0>
AUDMOD<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SPIFE ENHBUF 0000
SRXISEL<1:0>
0000
TXBUFELM<4:0>
SPITBE
—
SPITBF
0000
SPIRBF 0008
0000
0000
DATA<31:0>
—
—
—
—
—
—
—
—
—
SPI
FRM
SPI
SPI
15:0
—
—
IGNROV IGNTUR AUDEN
SGNEXT
ERREN
ROVEN
TUREN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1440 SPI3CON2
22/6
CKE
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW
FRMCNT<2:0>
1400 SPI3CON
15:0
ON
—
SIDL
DISSDO MODE32 MODE16
SMP
CKE
Legend:
23/7
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
TABLE 19-1:
—
—
—
BRG<8:0>
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
—
—
—
—
AUD
MONO
—
AUDMOD<1:0>
0000
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 306
19.1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
1600 SPI4CON
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW
FRMCNT<2:0>
15:0
ON
—
SIDL
DISSDO MODE32 MODE16
SMP
CKE
1610 SPI4STAT
31:16
15:0
1620 SPI4BUF
31:16
15:0
1630 SPI4BRG
31:16
15:0
—
—
—
—
—
—
1800 SPI5CON
1810 SPI5STAT
1820 SPI5BUF
1830 SPI5BRG
1840 SPI5CON2
1A00 SPI6CON
1A10 SPI6STAT
1A20 SPI6BUF
1A30 SPI6BRG
DS60001191F-page 307
1A40 SPI6CON2
RXBUFELM<4:0>
SPIBUSY
—
—
22/6
21/5
20/4
MCLKSEL
SSEN
—
CKP
—
MSTEN
—
DISSDI
—
SRMT
—
SPIROV
—
SPIRBE
—
SPITUR
19/3
18/2
—
—
STXISEL<1:0>
17/1
16/0
SPIFE ENHBUF 0000
SRXISEL<1:0>
0000
TXBUFELM<4:0>
SPITBE
—
SPITBF
0000
SPIRBF 0008
0000
0000
DATA<31:0>
—
—
—
—
—
—
31:16
1640 SPI4CON2
FRMERR
23/7
—
—
—
—
—
—
—
—
—
—
—
SPI
15:0
—
—
SGNEXT
31:16 FRMEN FRMSYNC FRMPOL
—
FRM
ERREN
MSSEN
15:0
31:16
ON
—
—
—
SIDL
—
DISSDO
MODE32 MODE16
SMP
RXBUFELM<4:0>
15:0
31:16
—
—
—
FRMERR
SPIBUSY
—
—
—
—
—
—
—
SPI
SPI
IGNROV IGNTUR AUDEN
ROVEN
TUREN
FRMSYPW
FRMCNT<2:0>
MCLKSEL
—
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
SPI1 THROUGH SPI6 REGISTER MAP (CONTINUED)
—
—
—
BRG<8:0>
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
—
—
—
—
AUD
MONO
—
—
—
AUDMOD<1:0>
—
—
—
CKE
SSEN
—
CKP
—
MSTEN
—
DISSDI
SPIFE
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
ENHBUF 0000
STXISEL<1:0>
SRXISEL<1:0>
TXBUFELM<4:0>
DATA<31:0>
0000
0000
0000
SPIRBF 0008
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
0000
0000
—
—
—
SPI
—
—
SGNEXT
31:16 FRMEN FRMSYNC FRMPOL
FRM
ERREN
MSSEN
15:0
31:16
ON
—
—
—
SIDL
—
DISSDO
MODE32 MODE16
SMP
RXBUFELM<4:0>
15:0
31:16
—
—
—
FRMERR
SPIBUSY
15:0
SPI
SPI
IGNROV IGNTUR AUDEN
ROVEN
TUREN
FRMSYPW
FRMCNT<2:0>
MCLKSEL
—
—
AUD
MONO
—
—
—
AUDMOD<1:0>
—
—
—
CKE
SSEN
—
CKP
—
MSTEN
—
DISSDI
SPIFE
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
ENHBUF 0000
STXISEL<1:0>
SRXISEL<1:0>
TXBUFELM<4:0>
DATA<31:0>
0000
0000
0000
SPIRBF 0008
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
0000
0000
15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
—
—
—
AUD
MONO
—
AUDMOD<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 19-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 19-1:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON: SPI CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRMCNT<2:0>
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
MCLKSEL(1)
—
—
—
—
—
SPIFE
ENHBUF(1)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
DISSDO(4)
MODE32
MODE16
SMP
CKE(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP(3)
MSTEN
DISSDI(4)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
STXISEL<1:0>
SRXISEL<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29
FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
bit 28
MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in 
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23
MCLKSEL: Master Clock Enable bit(1)
1 = REFCLKO1 is used by the Baud Rate Generator
0 = PBCLK2 is used by the Baud Rate Generator
bit 22-18 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for
maximum clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.3 “Peripheral Pin Select (PPS)” for more information).
DS60001191F-page 308
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 19-1:
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 17
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16
ENHBUF: Enhanced Buffer Enable bit(1)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15
ON: SPI/I2S Module On bit
1 = SPI/I2S module is enabled
0 = SPI/I2S module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12
DISSDO: Disable SDOx pin bit(4)
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32
MODE16
Communication
1
1
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1
0
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0
1
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0
0
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32
MODE16
Communication
1
x
32-bit
0
1
16-bit
0
0
8-bit
SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
CKE: SPI Clock Edge Select bit(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
CKP: Clock Polarity Select bit(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 9
bit 8
bit 7
bit 6
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for
maximum clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.3 “Peripheral Pin Select (PPS)” for more information).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 309
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 19-1:
bit 5
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
DISSDI: Disable SDI bit(4)
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are 
complete
SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for
maximum clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.3 “Peripheral Pin Select (PPS)” for more information).
DS60001191F-page 310
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 19-2:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON2: SPI CONTROL REGISTER 2
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPISGNEXT
—
—
FRMERREN
SPIROVEN
R/W-0
U-0
U-0
U-0
R/W-0
U-0
AUDEN(1)
—
—
—
AUDMONO(1,2)
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
SPITUREN IGNROV
R/W-0
IGNTUR
R/W-0
AUDMOD<1:0>(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extended
bit 14-13 Unimplemented: Read as ‘0’
bit 12
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
bit 11
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
bit 10
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generates Error Events
bit 9
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation
bit 8
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation
bit 7
AUDEN: Enable Audio CODEC Support bit(1)
1 = Audio protocol enabled
0 = Audio protocol disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 3
AUDMONO: Transmit Audio Data Format bit(1,2)
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 2
Unimplemented: Read as ‘0’
bit 1-0
AUDMOD<1:0>: Audio Protocol Mode bit(1,2)
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I2S mode
Note 1:
2:
This bit can only be written when the ON bit = 0.
This bit is only valid for AUDEN = 1.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 311
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 19-3:
Bit
Range
31:24
23:16
15:8
7:0
SPIxSTAT: SPI STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
U-0
R-0
SPITUR
—
—
—
U-0
U-0
U-0
RXBUFELM<4:0>
—
—
—
U-0
U-0
U-0
R/C-0, HS
R-0
R-0
TXBUFELM<4:0>
U-0
—
—
—
FRMERR
SPIBUSY
—
—
R-0
R/W-0
R-0
U-0
R-1
U-0
R-0
R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
Legend:
C = Clearable bit
HS = Set in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR: SPI Frame Error status bit
1 = Frame error detected
0 = No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4
Unimplemented: Read as ‘0’
DS60001191F-page 312
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 19-3:
SPIxSTAT: SPI STATUS REGISTER
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
 2013-2016 Microchip Technology Inc.
DS60001191F-page 313
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 314
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
20.0
Note:
SERIAL QUAD INTERFACE
(SQI)
This data sheet summarizes the
features of the PIC32MZ Embedded
Connectivity (EC) Family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 46. “Serial Quad Interface
(SQI)” (DS60001244), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The SQI module is a synchronous serial interface that
provides access to serial Flash memories and other
serial devices. The SQI module supports Single Lane
(identical to SPI), Dual Lane, and Quad Lane modes.
Note:
To avoid cache coherency problems on
devices with L1 cache, SQI buffers must
only be allocated or accessed from the
KSEG1 segment.
FIGURE 20-1:
The SQI module offers the following key features:
•
•
•
•
•
•
•
•
•
•
•
•
Supports Single, Dual, and Quad Lane modes
Programmable command sequence
eXecute-In-Place (XIP)
Data transfer:
- Programmed I/O mode (PIO)
- Buffer descriptor DMA
Supports High-Speed Serial Flash mode and SPI
Mode 0 and Mode 3
Programmable Clock Polarity (CPOL) and Clock
Phase (CPHA) bits
Supports up to two Chip Selects
Supports up to four bytes of Flash address
Programmable interrupt thresholds
32-byte transmit data buffer
32-byte receive data buffer
4-word controller buffer
Note:
Once the SQI module is configured,
external devices are memory mapped
into KSEG2 (see Figure 4-1 through
Figure 4-4 in Section 4.0 “Memory
Organization” for more information).
The MMU must be enabled and the TLB
must be set up to access this memory
(see Section 50. “CPU for Devices with
MIPS32® microAptiv™ and M-Class
Cores” (DS60001192) in the “PIC32
Family Reference Manual” for more
information).
SQI MODULE BLOCK DIAGRAM
PBCLK5(2)
REFCLKO2(1)
(TBC)
SQID0
Control
Buffer
SQID1
System Bus
Bus Slave
Bus Master
Control and
Status
Registers
(PIO)
DMA
SQID2
Transmit
Buffer
SQID3
SQI Master
Interface
SQICLK
SQICS0
Receive
Buffer
SQICS1
Note
1:
When configuring the REFCLKO2 clock source, a value of ‘0’ for the ROTRIM<8:0> bits must be selected.
2:
This clock source is only used for SQI Special Function Register (SFR) access.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 315
SQI Control Registers
Register
Name
Bit Range
SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP
Virtual Address
(BF8E_#)
TABLE 20-1:
2000
SQI1
XCON1
31:16
2004
SQI1
XCON2
31:16
—
—
—
—
15:0
—
—
—
—
31:16
SQIEN
—
—
—
—
—
15:0
—
—
—
BURSTEN
—
HOLD
WP
31:16
—
—
—
—
—
—
—
2008 SQI1CFG
200C SQI1CON
31/15
30/14
—
—
15:0
29/13
28/12
27/11
26/10
—
—
—
—
READOPCODE<5:0>
25/9
24/8
—
—
TYPEDATA<1:0>
—
—
DEVSEL<1:0>
—
—
CSEN<1:0>
21/5
—
15:0
20/4
DUMMYBYTES<2:0>
TYPEDUMMY<1:0>
—
—
19/3
18/2
ADDRBYTES<2:0>
TYPEMODE<1:0>
—
—
TYPEADDR<1:0>
—
17/1
16/0
READOPCODE<7:6>
0000
TYPECMD<1:0>
0C00
—
—
—
—
—
RESET
MODECODE<7:0>
—
SERMODE RXLATCH
—
—
DATAEN<1:0>
—
LSBF
DASSERT
CPOL
DEVSEL<1:0>
—
—
—
—
—
—
—
—
2010
2014
31:16
SQI1
CMDTHR 15:0
—
—
—
CPHA
MODE<2:0>
LANEMODE<1:0>
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
PKT
COMPIE
BD
DONEIE
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
0000
CMDINIT<1:0>
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
STABLE
EN
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CON
THRIE
CON
EMPTYIE
CON
FULLIE
RX
THRIE
RX
FULLIE
RX
EMPTYIE
—
—
—
—
0000
—
TXCMDTHR<4:0>
—
0000
—
CLKDIV<7:0>
—
0000
0000
TXRXCOUNT<15:0>
—
2018
22/6
MODEBYTES<1:0>
31:16
SQI1
CLKCON 15:0
SQI1
INTTHR
23/7
All Resets
Bits
—
TXINTTHR<4:0>
RXCMDTHR<4:0>
—
—
—
0000
—
—
—
—
—
0000
TX
THRIE
TX
FULLIE
TX
EMPTYIE
0000
—
0000
RXINTTHR<4:0>
0000
0000
 2013-2016 Microchip Technology Inc.
201C
SQI1
INTEN
2020
SQI1
INTSTAT
2024
31:16
SQI1
TXDATA 15:0
TXDATA<31:16>
0000
TXDATA<15:0>
0000
2028
31:16
SQI1
RXDATA 15:0
RXDATA<31:16>
0000
15:0
—
PKT
BD
COMPIF DONEIF
—
—
—
—
CON
THRIF
CON
EMPTYIF
CON
FULLIF
RX
THRIF
RX
RX
FULLIF EMPTYIF
—
—
TX
THRIF
TX
FULLIF
TX
0000
EMPTYIF
RXDATA<15:0>
0000
202C
SQI1
STAT1
31:16
—
—
—
—
—
—
—
—
TXFIFOFREE<7:0>
15:0
—
—
—
—
—
—
—
—
RXFIFOCNT<7:0>
2030
SQI1
STAT2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
SQID3
SQID2
SQID1
SQID0
—
RXUN
TXOV
00x0
2034
SQI1
BDCON
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
START
POLLEN
DMAEN
0000
2038
SQI1BD 31:16
CURADD 15:0
SQI1BD 31:16
2040
BASEADD 15:0
2044
Legend:
SQI1BD
STAT
31:16
15:0
—
—
—
—
—
—
0000
BDCURRADDR<31:16>
0000
BDCURRADDR<15:0>
0000
BDADDR<31:16>
0000
BDADDR<15:0>
—
0000
—
—
BDCON<15:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
—
BDSTATE<3:0>
DMASTART DMAACTV 0000
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 316
20.1
Virtual Address
(BF8E_#)
SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
SQI1BD 31:16
POLLCON 15:0
—
—
—
—
—
—
—
SQI1BD 31:16
204C
TXDSTAT 15:0
—
—
—
—
—
—
SQI1BD 31:16
2050
RXDSTAT 15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2048
2054
2058
SQI1THR
SQI1INT
SEN
Legend:
15:0
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
POLLCON<15:0>
TXSTATE<3:0>
—
—
—
—
—
RXSTATE<3:0>
—
—
0000
—
0000
RXBUFCNT<4:0>
0000
RXCURBUFLEN<7:0>
PKT
BD
CON
CON
CON
DONEISE DONEISE THRISE EMPTYISE FULLISE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TXBUFCNT<4:0>
TXCURBUFLEN<7:0>
—
0000
0000
—
—
All Resets
Bit Range
Register
Name
Bits
—
—
0000
—
—
—
—
—
THRES<6:0>
—
—
—
RX
RX
RX
TX
THRISE FULLISE EMPTYISE THRISE
0000
0000
TX
FULLISE
0000
TX
0000
EMPTYISE
DS60001191F-page 317
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 20-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-1:
Bit
Range
31:24
23:16
15:8
7:0
SQI1XCON1: SQI XIP CONTROL REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
DUMMYBYTES<2:0>
R-0
R-0
ADDRBYTES<2:0>
R-0
READOPCODE<7:6>
R-0
R/W-0
READOPCODE<5:0>
R/W-0
R/W-0
R/W-0
TYPEDUMMY<1:0>
R/W-0
TYPEMODE<1:0>
R/W-0
TYPEDATA<1:0>
R/W-0
R/W-0
R/W-0
TYPEADDR<1:0>
R/W-0
TYPECMD<1:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-21 DUMMYBYTES<2:0>: Transmit Dummy Bytes bits
111 = Transmit seven dummy bytes after the address bytes
•
•
•
011 = Transmit three dummy bytes after the address bytes
010 = Transmit two dummy bytes after the address bytes
001 = Transmit one dummy bytes after the address bytes
000 = Transmit zero dummy bytes after the address bytes
bit 20-18 ADDRBYTES<2:0>: Address Cycle bits
111 = Reserved
•
•
•
101 = Reserved
100 = Four address bytes
011 = Three address bytes
010 = Two address bytes
001 = One address bytes
000 = Zero address bytes
bit 17-10 READOPCODE<7:0>: Op code Value for Read Operation bits
These bits contain the 8-bit op code value for read operation.
bit 9-8
TYPEDATA<1:0>: SQI Type Data Enable bits
The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode data is enabled
01 = Dual Lane mode data is enabled
00 = Single Lane mode data is enabled
bit 7-6
TYPEDUMMY<1:0>: SQI Type Dummy Enable bits
The boot controller will send the dummy in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode dummy is enabled
01 = Dual Lane mode dummy is enabled
00 = Single Lane mode dummy is enabled
DS60001191F-page 318
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-1:
SQI1XCON1: SQI XIP CONTROL REGISTER 1 (CONTINUED)
bit 5-4
TYPEMODE<1:0>: SQI Type Mode Enable bits
The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode is enabled
01 = Dual Lane mode is enabled
00 = Single Lane mode is enabled
bit 3-2
TYPEADDR<1:0>: SQI Type Address Enable bits
The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode address is enabled
01 = Dual Lane mode address is enabled
00 = Single Lane mode address is enabled
bit 1-0
TYPECMD<1:0>: SQI Type Command Enable bits
The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode command is enabled
01 = Dual Lane mode command is enabled
00 = Single Lane mode command is enabled
 2013-2016 Microchip Technology Inc.
DS60001191F-page 319
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-2:
Bit
Range
31:24
23:16
15:8
7:0
SQI1XCON2: SQI XIP CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
DEVSEL<1:0>
R/W-0
R/W-0
MODEBYTES<1:0>
R/W-0
R/W-0
MODECODE<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-10 DEVSEL<1:0>: Device Select bits
11 = Reserved
10 = Reserved
01 = Device 1 is selected
00 = Device 0 is selected
bit 9-8
MODEBYTES<1:0>: Mode Byte Cycle Enable bits
11 = Three cycles
10 = Two cycles
01 = One cycle
00 = Zero cycles
bit 7-0
MODECODE<7:0>: Mode Code Value bits
These bits contain the 8-bit code value for the mode bits.
DS60001191F-page 320
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-3:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CFG: SQI CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
SQIEN
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0, HC
—
—
—
—
—
RESET
U-0
r-0
r-0
R/W-0
R/W-0
R/W-0
DATAEN<1:0>
r-0
R/W-0
(1)
BURSTEN
CSEN<1:0>
—
—
—
—
HOLD
WP
SERMODE
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXLATCH
—
LSBF
CPOL
CPHA
MODE<2:0>
Legend:
HC = Hardware Cleared
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
SQIEN: SQI Enable bit
1 = SQI module is enabled
0 = SQI module is disabled
bit 30-26 Unimplemented: Read as ‘0’
bit 25-24 CSEN<1:0>: Chip Select Output Enable bits
11 = Chip Select 0 and Chip Select 1 are used
10 = Chip Select 1 is used (Chip Select 0 is not used)
01 = Chip Select 0 is used (Chip Select 1 is not used)
00 = Chip Select 0 and Chip Select 1 are not used
bit 23-22 Unimplemented: Read as ‘0’
bit 21-20 DATAEN<1:0>: Data Output Enable bits
11 = Reserved
10 = SQID3-SQID0 outputs are enabled
01 = SQID1 and SQID0 data outputs are enabled
00 = SQID0 data output is enabled
bit 19-17 Unimplemented: Read as ‘0’
bit 16
RESET: Software Reset Select bit
This bit is automatically cleared by the SQI module. All of the internal state machines and FIFO pointers
are reset by this reset pulse.
1 = A reset pulse is generated
0 = A reset pulse is not generated
bit 15
Unimplemented: Read as ‘0’
bit 14-13 Reserved: Must be programmed as ‘0’
bit 12
BURSTEN: Burst Configuration bit(1)
1 = Burst is enabled
0 = Burst is not enabled
bit 11
Reserved: Must be programmed as ‘0’
bit 10
HOLD: Hold bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices
with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is
connected.
Note 1:
This bit must be programmed as ‘1’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 321
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-3:
SQI1CFG: SQI CONFIGURATION REGISTER (CONTINUED)
bit 9
WP: Write Protect bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices
with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is
connected.
bit 8
SERMODE: Serial Flash Mode Select bit
1 = Hardware ignores CPHA and CPOL bit settings and sends and latches negative edge of SQI CLK
0 = Clock phase and polarity are controlled by the CPHA and CPOL bit settings
bit 7
RXLATCH: RX Latch Control During TX Mode bit
1 = RX Data sent to RX FIFO when CMDINIT<1:0> (SQICON<17:16>) is set to TX
0 = RX Data is discarded when CMDINIT (SQICON<17:16>) is set to TX
bit 6
Unimplemented: Read as ‘0’
bit 5
LSBF: Data Format Select bit
1 = LSB is sent or received first
0 = MSB is sent or received first
bit 4
CPOL: Clock Polarity Select bit
1 = Active-low SQICLK (SQICLK high is the Idle state)
0 = Active-high SQICLK (SQICLK low is the Idle state)
bit 3
CPHA: Clock Phase Select bit
1 = SQICLK starts toggling at the start of the first data bit
0 = SQICLK starts toggling at the middle of the first data bit
bit 2-0
MODE<2:0>: Mode Select bits
111 = Reserved
•
•
•
100 = Reserved
011 = XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP),
but uses the register data to control timing)
010 = DMA mode is selected
001 = CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when
leaving Boot or XIP mode)
000 = Reserved
Note 1:
This bit must be programmed as ‘1’.
DS60001191F-page 322
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-4:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CON: SQI CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
U-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DASSERT
R/W-0
R/W-0
R/W-0
DEVSEL<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
LANEMODE<1:0>
R/W-0
CMDINIT<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXRXCOUNT<15:8>
R/W-0
R/W-0
TXRXCOUNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22
DASSERT: Chip Select Assert bit
1 = Chip Select is deasserted after transmission or reception of the specified number of bytes
0 = Chip Select is not deasserted after transmission or reception of the specified number of bytes
bit 21-20 DEVSEL<1:0>: SQI Device Select bits
11 = Reserved
10 = Reserved
01 = Select Device 1
00 = Select Device 0
bit 19-18 LANEMODE<1:0>: SQI Lane Mode Select bits
11 = Reserved
10 = Quad Lane mode
01 = Dual Lane mode
00 = Single Lane mode
bit 17-16 CMDINIT<1:0>: Command Initiation Mode Select bits
If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX
FIFO. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX FIFO
availability.
11 = Reserved
10 = Receive
01 = Transmit
00 = Idle
bit 15-0
TXRXCOUNT<15:0>: Transmit/Receive Count bits
These bits specify the total number of bytes to transmit or received (based on CMDINIT)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 323
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-5:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CLKCON: SQI CLOCK CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R/W-0
—
—
—
—
—
—
STABLE
EN
CLKDIV<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
CLKDIV<7:0>: SQI Clock TSQI Frequency Select bit(1)
10000000 = Base clock TBC is divided by 512
01000000 = Base clock TBC is divided by 256
00100000 = Base clock TBC is divided by 128
00010000 = Base clock TBC is divided by 64
00001000 = Base clock TBC is divided by 32
00000100 = Base clock TBC is divided by 16
00000010 = Base clock TBC is divided by 8
00000001 = Base clock TBC is divided by 4
00000000 = Base clock TBC is divided by 2
bit 7-2
Unimplemented: Read as ‘0’
bit 1
STABLE: TSQI Clock Stable Select bit
This bit is set to ‘1’ when the SQI clock, TSQI, is stable after writing a ‘1’ to the EN bit.
1 = TSQI clock is stable
0 = TSQI clock is not stable
bit 0
EN: TSQI Clock Enable Select bit
When clock oscillation is stable, the SQI module will set the STABLE bit to ‘1’.
1 = Enable the SQI clock (TSQI) (when clock oscillation is stable, the SQI module sets the STABLE bit to ‘1’)
0 = Disable the SQI clock (TSQI) (the SQI module should stop its clock to enter a low power state); SFRs
can still be accessed, as they use PBCLK5
Note 1:
Refer to Table in Section 37.0 “Electrical Characteristics” for the maximum clock frequency
specifications.
Setting these bits to ‘00000000’ specifies the highest frequency of the SQI clock.
DS60001191F-page 324
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-6:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CMDTHR: SQI COMMAND THRESHOLD REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
—
—
—
TXCMDTHR<4:0>
R/W-0
RXCMDTHR<4:0>(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8
TXCMDTHR<4:0>: Transmit Command Threshold bits
In transmit initiation mode, the SQI module performs a transmit operation when transmit command
threshold bytes are present in the TX FIFO. For 16-bit mode, the value should be multiple of two. These
bits should usually be set to ‘1’ for normal Flash commands, and set to a higher value for page
programming. For 16-bit mode, the value should be a multiple of two.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RXCMDTHR<4:0>: Receive Command Threshold bits(1)
In receive initiation mode, the SQI module attempts to perform receive operations to fetch the receive command threshold number of bytes in the receive buffer. If space for these bytes is not present in the FIFO,
the SQI will not initiate a transfer. For 16-bit mode, the value should be a multiple of two.
If software performs any reads, thereby reducing the FIFO count, hardware would initiate a receive transfer
to make the FIFO count equal to the value in these bits. If software would not like any more words latched
into the FIFO, command initiation mode needs to be changed to Idle before any FIFO reads by software.
In the case of Boot/XIP mode, the SQI module will use the System Bus burst size, instead of the receive
command threshold value.
Note 1:
These bits should only be programmed when a receive is not active (i.e., during Idle mode or a transmit).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 325
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-7:
Bit
Range
31:24
23:16
15:8
7:0
SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
—
—
—
TXINTTHR<4:0>
R/W-0
RXINTTHR<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8
TXINTTHR<4:0>: Transmit Interrupt Threshold bits
A transmit interrupt is set when the transmit FIFO has more space than the transmit interrupt threshold
bytes. For 16-bit mode, the value should be a multiple of two.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RXINTTHR<4:0>: Receive Interrupt Threshold bits
A receive interrupt is set when the receive FIFO count is larger than or equal to the receive interrupt
threshold value. RXINTTHR is the number of bytes in the receive FIFO. For 16-bit mode, the value should
be a multiple of two.
DS60001191F-page 326
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-8:
Bit
Range
31:24
23:16
15:8
7:0
SQI1INTEN: SQI INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CONEMPTYIE CONFULLIE RXTHRIE RXFULLIE RXEMPTYIE
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
PKTCOMPIE BDDONEIE CONTHRIE
R/W-0
TXTHRIE
R/W-0
R/W-0
TXFULLIE TXEMPTYIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10
PKTCOMPIE: DMA Buffer Descriptor Packet Complete Interrupt Enable bit
1 = Interrupts are enabled
0 = Interrupts are not enabled
bit 9
BDDONEIE: DMA Buffer Descriptor Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 8
CONTHRIE: Control Buffer Threshold Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 7
CONEMPTYIE: Control Buffer Empty Interrupt bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 6
CONFULLIE: Control Buffer Full Interrupt Enable bit
This bit enables an interrupt when the receive FIFO buffer is full.
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
RXTHRIE: Receive Buffer Threshold Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 4
RXFULLIE: Receive Buffer Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3
RXEMPTYIE: Receive Buffer Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 2
TXTHRIE: Transmit Threshold Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
TXFULLIE: Transmit Buffer Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 0
TXEMPTYIE: Transmit Buffer Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
 2013-2016 Microchip Technology Inc.
DS60001191F-page 327
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-9:
Bit
Range
31:24
23:16
15:8
7:0
SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
—
—
—
—
—
PKT
COMPIF
BD
DONEIF
CON
THRIF
R/W-1, HS
R/W-0, HS
R/W-1, HS
R/W-0, HS
R/W-1, HS
R/W-1, HS
R/W-0, HS
R/W-1, HS
CON
EMPTYIF
CON
FULLIF
RXFULLIF
RX
EMPTYIF
TXTHRIF
TXFULLIF
TX
EMPTYIF
RXTHRIF
(1)
Legend:
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10
PKTCOMPIF: DMA Buffer Descriptor Processor Packet Completion Interrupt Status bit
1 = DMA BD packet is complete
0 = DMA BD packet is in progress
bit 9
BDDONEIF: DMA Buffer Descriptor Done Interrupt Status bit
1 = DMA BD process is done
0 = DMA BD process is in progress
bit 8
CONTHRIF: Control Buffer Threshold Interrupt Status bit
1 = The control buffer has more than THRES words of space available
0 = The control buffer has less than THRES words of space available
bit 7
CONEMPTYIF: Control Buffer Empty Interrupt Status bit
1 = Control buffer is empty
0 = Control buffer is not empty
bit 6
CONFULLIF: Control Buffer Full Interrupt Status bit
1 = Control buffer is full
0 = Control buffer is not full
bit 5
RXTHRIF: Receive Buffer Threshold Interrupt Status bit(1)
1 = Receive buffer has more than RXINTTHR words of space available
0 = Receive buffer has less than RXINTTHR words of space available
bit 4
RXFULLIF: Receive Buffer Full Interrupt Status bit
1 = Receive buffer is full
0 = Receive buffer is not full
bit 3
RXEMPTYIF: Receive Buffer Empty Interrupt Status bit
1 = Receive buffer is empty
0 = Receive buffer is not empty
bit 2
TXTHRIF: Transmit Buffer Interrupt Status bit
1 = Transmit buffer has more than TXINTTHR words of space available
0 = Transmit buffer has less than TXINTTHR words of space available
Note 1:
In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will
be set to a ‘1’, immediately after a POR until a read request on the System Bus bus is received.
Note:
The bits in the register are cleared by writing a '1' to the corresponding bit position.
DS60001191F-page 328
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-9:
SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED)
bit 1
TXFULLIF: Transmit Buffer Full Interrupt Status bit
1 = The transmit buffer is full
0 = The transmit buffer is not full
bit 0
TXEMPTYIF: Transmit Buffer Empty Interrupt Status bit
1 = The transmit buffer is empty
0 = The transmit buffer has content
Note 1:
In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will
be set to a ‘1’, immediately after a POR until a read request on the System Bus bus is received.
Note:
The bits in the register are cleared by writing a '1' to the corresponding bit position.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 329
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-10: SQI1TXDATA: SQI TRANSMIT DATA BUFFER REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXDATA<31:24>
R/W-0
R/W-0
TXDATA<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXDATA<15:8>
R/W-0
TXDATA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
TXDATA<31:0>: Transmit Command Data bits
Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the
data in TXDATA is loaded into the shift register (SFDR).
Multiple writes to TXDATA can occur even while a transfer is already in progress. There can be a maximum
of eight commands that can be queued.
REGISTER 20-11: SQI1RXDATA: SQI RECEIVE DATA BUFFER REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXDATA<31:24>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXDATA<23:16>
R-0
R-0
RXDATA<15:8>
R-0
R-0
R-0
R-0
R-0
RXDATA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RXDATA<31:0>: Receive Data Buffer bits
At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register
works like a FIFO. The depth of the receive buffer is eight words. These bits indicate the starting write block
address for an erase operation.
DS60001191F-page 330
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-12: SQI1STAT1: SQI STATUS REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TXFIFOFREE<7:0>
RXFIFOCNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-24
bit 23-16
bit 15-8
bit 7-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
TXFIFOFREE<7:0>: Transmit FIFO Available Word Space bits
Unimplemented: Read as ‘0’
RXFIFOCNT<7:0>: Number of words of read data in the FIFO
 2013-2016 Microchip Technology Inc.
DS60001191F-page 331
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-13: SQI1STAT2: SQI STATUS REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
R-0
R-0
R-0
U-0
R-0
R-0
—
SQID3
SQID2
SQID1
SQID0
—
RXUN
TXOV
Legend:
R = Readable bit
-n = Value at POR
bit 31-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
SQID3: SQID3 Status bits
1 = Data is present on SQID3
0 = Data is not present on SQID3
SQID2: SQID2 Status bits
1 = Data is present on SQID2
0 = Data is not present on SQID2
SQID1: SQID1 Status bits
1 = Data is present on SQID1
0 = Data is not present on SQID1
SQID0: SQID0 Status bits
1 = Data is present on SQID0
0 = Data is not present on SQID0
Unimplemented: Read as ‘0’
RXUN: Receive FIFO Underflow Status bit
1 = Receive FIFO Underflow has occurred
0 = Receive FIFO underflow has not occurred
TXOV: Transmit FIFO Overflow Status bit
1 = Transmit FIFO overflow has occurred
0 = Transmit FIFO overflow has not occurred
DS60001191F-page 332
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-14: SQI1BDCON: SQI BUFFER DESCRIPTOR CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
START
POLLEN
DMAEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 2
START: Buffer Descriptor Processor Start bit
1 = Start the buffer descriptor processor
0 = Disable the buffer descriptor processor
bit 1
POLLEN: Buffer Descriptor Poll Enable bit
1 = BDP poll enabled
0 = BDP poll is not enabled
bit 0
DMAEN: DMA Enable bit
1 = DMA is enabled
0 = DMA is disabled
x = Bit is unknown
REGISTER 20-15: SQI1BDCURADD: SQI BUFFER DESCRIPTOR CURRENT ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDCURRADDR<31:24>
R-0
R-0
BDCURRADDR<23:16>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDCURRADDR<15:8>
R-0
R-0
BDCURRADDR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BDCURRADDR<31:0>: Current Buffer Descriptor Address bits
These bits contain the address of the current descriptor being processed by the Buffer Descriptor
Processor.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 333
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-16: SQI1BDBASEADD: SQI BUFFER DESCRIPTOR BASE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDADDR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDADDR<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDADDR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDADDR<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
BDADDR<31:0>: DMA Base Address bits
These bits contain the base address of the DMA. This register should be updated only when the DMA is
idle.
REGISTER 20-17: SQI1BDSTAT: SQI BUFFER DESCRIPTOR STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-x
R-x
R-x
R-x
R-x
R-x
—
—
R-x
R-x
R-x
BDSTATE<3:0>
R-x
R-x
R-x
R-x
R-x
R-x
DMASTART DMAACTV
R-x
R-x
R-x
R-x
R-x
R-x
BDCON<15:8>
Legend:
R = Readable bit
-n = Value at POR
R-x
BDCON<7:0>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21-18 BDSTATE<3:0>: DMA Buffer Descriptor Processor State Status bits
These bits return the current state of the buffer descriptor processor:
5 = Fetched buffer descriptor is disabled
4 = Descriptor is done
3 = Data phase
2 = Buffer descriptor is loading
1 = Descriptor fetch request is pending
0 = Idle
bit 17
DMASTART: DMA Buffer Descriptor Processor Start Status bit
1 = DMA has started
0 = DMA has not started
bit 16
DMAACTV: DMA Buffer Descriptor Processor Active Status bit
1 = Buffer Descriptor Processor is active
0 = Buffer Descriptor Processor is idle
bit 15-0 BDCON<15:0>: DMA Buffer Descriptor Control Word bits
These bits contain the current buffer descriptor control word.
DS60001191F-page 334
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-18: SQI1BDPOLLCON: SQI BUFFER DESCRIPTOR POLL CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLLCON<15:8>
R/W-0
R/W-0
POLLCON<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
POLLCON<15:0>: Buffer Descriptor Processor Poll Status bits
These bits indicate the number of cycles the BDP block would wait before refetching the descriptor control
word if the previous descriptor fetched was disabled.
REGISTER 20-19: SQI1BDTXDSTAT: SQI BUFFER DESCRIPTOR DMA TRANSMIT STATUS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-x
R-x
R-x
R-x
U-0
—
—
—
U-0
U-0
U-0
R-x
R-x
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
TXSTATE<3:0>
R-x
R-x
—
R-x
TXBUFCNT<4:0>
TXCURBUFLEN<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 TXSTATE<3:0>: Current DMA Transmit State Status bits
These bits provide information on the current DMA receive states.
bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal FIFO space.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
TXCURBUFLEN<7:0>: Current DMA Transmit Buffer Length Status bits
These bits provide the length of the current DMA transmit buffer.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 335
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-20: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-x
R-x
R-x
R-x
U-0
R-x
R-x
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
RXSTATE<3:0>
R-x
R-x
U-0
U-0
—
R-x
RXBUFCNT<4:0>
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXCURBUFLEN<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 RXSTATE<3:0>: Current DMA Receive State Status bits
These bits provide information on the current DMA receive states.
bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 RXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal FIFO space.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
RXCURBUFLEN<7:0>: Current DMA Receive Buffer Length Status bits
These bits provide the length of the current DMA receive buffer.
DS60001191F-page 336
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-21: SQI1THR: SQI THRESHOLD CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
THRES<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-5
Unimplemented: Read as ‘0’
bit 4-0
THRES<4:0>: SQI Control Threshold Value bits
The SQI control threshold interrupt is asserted when the amount of space in indicated by THRES<4:0> is
available in the SQI control buffer.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 337
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 20-22: SQI1INTSEN: SQI INTERRUPT SIGNAL ENABLE REGISTER
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
15:8
—
—
—
—
—
PKT
DONEISE
BD
DONEISE
CON
THRISE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7:0
CON
EMPTYISE
CON
FULLISE
RX
THRISE
RX
FULLISE
RX
EMPTYISE
TX
THRISE
TX
FULLISE
TX
EMPTYISE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10
PKTDONEISE: Receive Error Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 9
BDDONEISE: Transmit Error Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 8
CONTHRISE: Control Buffer Threshold Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 7
CONEMPTYISE: Control Buffer Empty Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 6
CONFULLISE: Control Buffer Full Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 5
RXTHRISE: Receive Buffer Threshold Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 4
RXFULLISE: Receive Buffer Full Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 3
RXEMPTYISE: Receive Buffer Empty Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 2
TXTHRISE: Transmit Buffer Threshold Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 1
TXFULLISE: Transmit Buffer Full Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 0
TXEMPTYISE: Transmit Buffer Empty Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
DS60001191F-page 338
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
21.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C)
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard.
Each I2C module offers the following key features:
• I2C interface supporting both master and slave
operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking
• SMBus support
Figure 21-1 illustrates the I2C module block diagram.
Each I2C module has a 2-pin interface:
• SCLx pin is clock
• SDAx pin is data
 2013-2016 Microchip Technology Inc.
DS60001191F-page 339
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 21-1:
I2C BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
SCLx
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
PBCLK2
DS60001191F-page 340
 2013-2016 Microchip Technology Inc.
I2C Control Registers
Virtual Address
(BF82_#)
Register
Name(1)
TABLE 21-1:
0000
I2C1CON
0010
I2C1STAT
0020
I2C1ADD
0030
I2C1MSK
0040
I2C1BRG
0050
I2C1TRN
0060
I2C1RCV
I2C1 THROUGH I2C5 REGISTER MAP
0200 I2C2CON(2)
0210 I2C2STAT
(2)
0220 I2C2ADD(2)
0230 I2C2MSK(2)
0240 I2C2BRG(2)
0250 I2C2TRN(2)
0260 I2C2RCV(2)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
—
SIDL
—
ACKTIM
—
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
—
A10M
—
BCL
—
—
—
—
—
—
DISSLW
—
GCSTAT
—
—
SMEN
—
ADD10
—
—
GCEN
—
IWCOL
—
PCIE
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
SIDL
—
ACKTIM
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
A10M
—
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Baud Rate Generator Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCIE
DISSLW
—
GCSTAT
—
SMEN
—
ADD10
—
GCEN
—
IWCOL
—
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
Baud Rate Generator Register
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
SCIE
BOEN
SDAHT
ACKDT
ACKEN
RCEN
—
—
—
D/A
P
S
—
—
—
Address Register
—
—
—
Address Mask Register
—
—
—
—
—
—
—
Transmit Register
—
—
Receive Register
SCIE
BOEN
SDAHT
ACKDT
ACKEN
RCEN
—
—
—
D/A
P
S
—
—
—
Address Register
—
—
—
Address Mask Register
—
—
—
—
—
—
—
Transmit Register
—
—
Receive Register
18/2
17/1
16/0
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bit Range
Bits
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
DS60001191F-page 341
31:16
—
—
—
—
—
—
—
—
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN 0000
15:0
ON
—
SIDL
SCLREL STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0410 I2C3STAT
15:0 ACKSTAT TRSTAT ACKTIM
—
—
BCL
GCSTAT ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0420 I2C3ADD
15:0
—
—
—
—
—
—
Address Register
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
2:
This register is not available on 64-pin devices.
0400
I2C3CON
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
21.1
Virtual Address
(BF82_#)
Register
Name(1)
0430
I2C3MSK
0440
0450
0460
I2C1 THROUGH I2C5 REGISTER MAP (CONTINUED)
31:16
15:0
31:16
I2C3BRG
15:0
31:16
I2C3TRN
15:0
31:16
I2C3RCV
15:0
0600
I2C4CON
0610
I2C4STAT
0620
I2C4ADD
0630
I2C4MSK
0640
I2C4BRG
0650
I2C4TRN
0660
I2C4RCV
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
ACKTIM
—
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
—
A10M
—
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
—
—
—
—
Baud Rate Generator Register
—
—
—
—
—
—
—
—
—
—
—
—
—
DISSLW
—
GCSTAT
—
—
SMEN
—
ADD10
—
—
GCEN
—
IWCOL
—
PCIE
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
Baud Rate Generator Register
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
—
—
Address Mask Register
—
—
—
—
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
Receive Register
SCIE
BOEN
SDAHT
ACKDT
ACKEN
RCEN
—
—
—
D/A
P
S
—
—
—
Address Register
—
—
—
Address Mask Register
—
—
—
—
—
—
—
Transmit Register
—
—
Receive Register
All Resets
Bit Range
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
31:16
—
—
—
—
—
—
—
—
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN 0000
15:0
ON
—
SIDL
SCLREL STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0810 I2C5STAT
15:0 ACKSTAT TRSTAT ACKTIM
—
—
BCL
GCSTAT ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0820 I2C5ADD
15:0
—
—
—
—
—
—
Address Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0830 I2C5MSK
15:0
—
—
—
—
—
—
Address Mask Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0840 I2C5BRG
15:0
Baud Rate Generator Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0850 I2C5TRN
15:0
—
—
—
—
—
—
—
—
Transmit Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0860 I2C5RCV
15:0
—
—
—
—
—
—
—
—
Receive Register
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
2:
This register is not available on 64-pin devices.
0800
I2C5CON
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 342
TABLE 21-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 21-1:
Bit
Range
31:24
23:16
15:8
7:0
I2CXCON: I2C CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DHEN
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
SCKREL
STRICT
A10M
DISSLW
SMEN
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
Legend:
R = Readable bit
-n = Value at POR
HC = Cleared in Hardware
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22
PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 21
SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 20
BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the
I2COV bit (I2CxSTAT<6>)only if the RBF bit (I2CxSTAT<2>) = 0
0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT<6>) is clear
bit 19
SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 18
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 18
AHEN: Address Hold Enable bit (Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared
and the SCL will be held low.
0 = Address holding is disabled
bit 16
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit
and SCL is held low
0 = Data holding is disabled
bit 15
ON: I2C Enable bit
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
 2013-2016 Microchip Technology Inc.
DS60001191F-page 343
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 21-1:
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
I2CXCON: I2C CONTROL REGISTER (CONTINUED)
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit 
(when operating as I2C master, applicable during master receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. 
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of 
master Repeated Start sequence.
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress
DS60001191F-page 344
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 21-2:
Bit
Range
31:24
23:16
15:8
7:0
I2CXSTAT: I2C STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS, HC
R-0, HS, HC
R/C-0, HS, HC
U-0
U-0
R/C-0, HS
R-0, HS, HC
R-0, HS, HC
ACKSTAT
TRSTAT
ACKTIM
—
—
BCL
GCSTAT
ADD10
R/C-0, HS
R/C-0, HS
R-0, HS, HC
R/C-0, HS, HC
R/C-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit 
(when operating as I2C master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13
ACKTIM: Acknowledge Time Status bit (Valid in I2C Slave mode only)
1 = I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
bit 12-11 Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 345
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 21-2:
I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 5
D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software 
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS60001191F-page 346
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
22.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
The following are primary features of the UART
module:
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS60001107), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The UART module is one of the serial I/O modules
available in PIC32MZ EC family devices. The UART
is a full-duplex, asynchronous communication
channel that communicates with peripheral devices
and personal computers through protocols, such as
RS-232, RS-485, LIN, and IrDA®. The module also
supports the hardware flow control option, with
UxCTS and UxRTS pins, and also includes an IrDA
encoder and decoder.
• One or two Stop bits
• Hardware auto-baud feature
• Hardware flow control option
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
• Baud rates ranging from 76 bps to 25 Mbps at
100 MHz (PBCLK2)
• 8-level deep First-In-First-Out (FIFO) transmit
data buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt-only on address detect 
(9th bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 22-1 illustrates a simplified block diagram of the
UART module.
FIGURE 22-1:
UART SIMPLIFIED BLOCK DIAGRAM
PBCLK2
Baud Rate Generator
IrDA®
Hardware Flow Control
UxRTS/BCLKx
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
 2013-2016 Microchip Technology Inc.
DS60001191F-page 347
UART Control Registers
Virtual Address
(BF82_#)
TABLE 22-1:
U1STA
(1)
2030 U1RXREG
U1BRG(1)
2200 U2MODE
2210
(1)
U2STA(1)
2220 U2TXREG
2230 U2RXREG
2240
U2BRG(1)
2400 U3MODE(1)
 2013-2016 Microchip Technology Inc.
2410
U3STA
(1)
2420 U3TXREG
2430 U3RXREG
2440
30/14
31:16
—
—
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
2020 U1TXREG
2040
31/15
U3BRG(1)
UTXISEL<1:0>
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
IREN
RTSMD
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
UEN<1:0>
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
UTXISEL<1:0>
—
—
UEN<1:0>
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
UTXISEL<1:0>
—
—
UEN<1:0>
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
16/0
—
0000
STSEL
0000
ADDR<7:0>
URXISEL<1:0>
—
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
Receive Register
—
—
0000
—
—
—
—
—
—
—
—
0000
STSEL
0000
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
ADDR<7:0>
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
STSEL
0000
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
ADDR<7:0>
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
—
0000
0000
Receive Register
—
0000
0000
—
—
0000
—
—
URXISEL<1:0>
0000
0000
Receive Register
—
0000
0000
—
—
0000
—
—
URXISEL<1:0>
0000
0000
Baud Rate Generator Prescaler
31:16
15:0
15:0
22/6
Baud Rate Generator Prescaler
31:16
15:0
15:0
23/7
All Resets
Register
Name
Bit Range
Bits
2000 U1MODE(1)
2010
UART1 THROUGH UART6 REGISTER MAP
0000
0000
Baud Rate Generator Prescaler
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 348
22.1
Virtual Address
(BF82_#)
U4STA(1)
2620 U4TXREG
2630 U4RXREG
2640
U4BRG(1)
2800 U5MODE(1)
2810
U5STA
(1)
2830 U5RXREG
2840
U5BRG(1)
2A00 U6MODE
2A10
(1)
U6STA(1)
2A20 U6TXREG
2A30 U6RXREG
DS60001191F-page 349
2A40
U6BRG(1)
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
31:16
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
15:0
UTXISEL<1:0>
UEN<1:0>
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
UTXISEL<1:0>
—
—
UEN<1:0>
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
UTXISEL<1:0>
—
—
UEN<1:0>
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
16/0
—
0000
STSEL
0000
ADDR<7:0>
URXISEL<1:0>
—
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
Receive Register
—
—
0000
—
—
—
—
—
—
—
—
0000
STSEL
0000
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
ADDR<7:0>
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
STSEL
0000
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
ADDR<7:0>
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
—
0000
0000
Receive Register
—
0000
0000
—
—
0000
—
—
URXISEL<1:0>
0000
0000
Receive Register
—
0000
0000
—
—
0000
—
—
URXISEL<1:0>
0000
0000
Baud Rate Generator Prescaler
31:16
15:0
15:0
23/7
Baud Rate Generator Prescaler
31:16
15:0
15:0
2820 U5TXREG
31/15
All Resets
Register
Name
Bit Range
Bits
2600 U4MODE(1)
2610
UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
0000
0000
Baud Rate Generator Prescaler
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 22-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 22-1:
Bit
Range
31:24
23:16
15:8
7:0
UxMODE: UARTx MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
(1)
ON
—
SIDL
IREN
RTSMD
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
UEN<1:0>
R/W-0
PDSEL<1:0>
R/W-0
STSEL
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: UARTx Enable bit
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN 
control bits
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
bit 12
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN<1:0>: UARTx Enable bits(1)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
Note 1:
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see Section 12.3 “Peripheral Pin Select (PPS)” for more information).
DS60001191F-page 350
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 22-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character (requires reception of Sync character (0x55);
cleared by hardware upon completion)
0 = Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see Section 12.3 “Peripheral Pin Select (PPS)” for more information).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 351
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 22-2:
Bit
Range
31:24
23:16
15:8
7:0
UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ADM_EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR<7:0>
R/W-0
R/W-0
UTXISEL<1:0>
R/W-0
R/W-0
URXISEL<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-1
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
R/W-0
R-1
R-0
R-0
R/W-0
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ADM_EN: Automatic Address Detect Mode Enable bit
1 = Automatic Address Detect mode is enabled
0 = Automatic Address Detect mode is disabled
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address
detection.
bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
bit 11
UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion
0 = Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
DS60001191F-page 352
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 22-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least one data character)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
 2013-2016 Microchip Technology Inc.
DS60001191F-page 353
PIC32MZ Embedded Connectivity (EC) Family
Figure 22-2 and Figure 22-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 22-2:
UART RECEPTION
Char 1
Char 2-4
Char 5-10
Char 11-13
Read to
UxRXREG
Start 1
Stop Start 2
Stop 4
Start 5
Stop 10 Start 11
Stop 13
UxRX
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 22-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS60001191F-page 354
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
23.0
PARALLEL MASTER PORT
(PMP)
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS60001128),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
FIGURE 23-1:
Key features of the PMP module include:
•
•
•
•
•
•
•
•
•
•
•
8-bit,16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
Programmable strobe options:
- Individual read and write strobes, or
- Read/write strobe with enable strobe
Address auto-increment/auto-decrement
Programmable address/data multiplexing
Programmable polarity on control signals
Parallel Slave Port support:
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
Programmable Wait states
Operate during Sleep and Idle modes
Fast bit manipulation using CLR, SET, and INV
registers
Note:
On 64-pin devices, data pins PMD<15:8>
are not available in 16-bit Master modes.
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
PBCLK2
Address Bus
Data Bus
Parallel
Master Port
Control Lines
PMA0
PMALL
PMA1
PMALH
Flash
EEPROM
SRAM
Up to 16-bit Address
PMA<13:2>
PMA14
PMCS1
PMA15
PMCS2
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMD<15:8>(1)
Note:
Microcontroller
LCD
FIFO
Buffer
8-bit/16-bit Data (with or without multiplexed addressing)
On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 355
PMP Control Registers
Virtual Address
(BF82_#)
Register
Name(1)
TABLE 23-1:
E000
PMCON
PARALLEL MASTER PORT REGISTER MAP
E010 PMMODE
E020 PMADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
31:16
ON
—
—
—
SIDL
—
15:0
31:16
BUSY
—
15:0
CS2
ADDR15
IRQM<1:0>
—
—
28/12
27/11
—
—
ADRMUX<1:0>
—
—
INCM<1:0>
—
—
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
—
—
—
—
—
—
0000
PMPTTL PTWREN PTRDEN
—
—
—
CSF<1:0>
—
—
ALP
—
CS2P
—
CS1P
—
—
—
WRSP
—
RDSP
—
0000
0000
MODE16
—
WAITB<1:0>
—
—
—
MODE<1:0>
—
—
CS1
ADDR14
WAITM<3:0>
—
—
—
WAITE<1:0>
—
—
0000
0000
0000
ADDR<13:0>
E030 PMDOUT
31:16
15:0
DATAOUT<31:0>
0000
0000
E040
PMDIN
31:16
15:0
DATAIN<31:0>
0000
0000
E050
PMAEN
E060
PMSTAT
Legend:
Note 1:
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTEN<15:0>
—
—
—
—
—
—
—
—
—
0000
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
15:0
31:16
—
—
—
—
—
—
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 356
23.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
PMCON: PARALLEL PORT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
PMPTTL
PTWREN
PTRDEN
R/W-0
R/W-0
(1)
R/W-0
(1)
U-0
R/W-0
R/W-0
—
WRSP
RDSP
CSF<1:0>
ALP
ADRMUX<1:0>
R/W-0
(1)
CS2P
R/W-0
(1)
CS1P
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Lower 8 bits of address are multiplexed on PMD<15:0> pins; upper 8 bits are not used
10 = All 16 bits of address are multiplexed on PMD<15:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
bit 7-6
CSF<1:0>: Chip Select Function bits(1)
11 = Reserved
10 = PMCS1 and PMCS2 function as Chip Select
01 = PMCS2 functions as Chip Select and PMCS1 functions as address bit 14
00 = PMCS1 and PMCS2 function as address bit 14 and address bit 15
bit 5
ALP: Address Latch Polarity bit(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4
CS2P: Chip Select 2 Polarity bit(1)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
Note 1:
These bits have no effect when their corresponding pins are used as address lines.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 357
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-1:
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 3
CS1P: Chip Select 1 Polarity bit(1)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
bit 2
Unimplemented: Read as ‘0’
bit 1
WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master mode 1 (MODE<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (MODE<1:0> = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Master mode 1 (MODE<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1:
These bits have no effect when their corresponding pins are used as address lines.
DS60001191F-page 358
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-2:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
R/W-0
7:0
PMMODE: PARALLEL PORT MODE REGISTER
IRQM<1:0>
R/W-0
(1)
R/W-0
WAITB<1:0>
INCM<1:0>
R/W-0
R/W-0
(1)
MODE16
MODE<1:0>
R/W-0
R/W-0
R/W-0
WAITE<1:0>(1)
WAITM<3:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only)
10 = Decrement ADDR<15:0> and ADDR<14> by 1 every read/write cycle(2)
01 = Increment ADDR<15:0> and ADDR<14> by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10
MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8
MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<15:0>)(3)
10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, and PMD<15:0>)(3)
01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCSx, PMD<7:0>, and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx, and PMD<7:0>)
bit 7-6
WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPBCLK2; multiplexed address phase of 4 TPBCLK2
10 = Data wait of 3 TPBCLK2; multiplexed address phase of 3 TPBCLK2
01 = Data wait of 2 TPBCLK2; multiplexed address phase of 2 TPBCLK2
00 = Data wait of 1 TPBCLK2; multiplexed address phase of 1 TPBCLK2 (default)
Note 1:
Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK2 cycle for a
write operation; WAITB = 1 TPBCLK2 cycle, WAITE = 0 TPBCLK2 cycles for a read operation.
Address bits 14 and 15 are is not subject to auto-increment/decrement if configured as Chip Select.
The PMD<15:8> bits are not active is the MODE16 bit = 1.
2:
3:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 359
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-2:
PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 5-2
WAITM<3:0>: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPBCLK2
•
•
•
0001 = Wait of 2 TPBCLK2
0000 = Wait of 1 TPBCLK2 (default)
bit 1-0
WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPBCLK2
10 = Wait of 3 TPBCLK2
01 = Wait of 2 TPBCLK2
00 = Wait of 1 TPBCLK2 (default)
For Read operations:
11 = Wait of 3 TPBCLK2
10 = Wait of 2 TPBCLK2
01 = Wait of 1 TPBCLK2
00 = Wait of 0 TPBCLK2 (default)
Note 1:
2:
3:
Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK2 cycle for a
write operation; WAITB = 1 TPBCLK2 cycle, WAITE = 0 TPBCLK2 cycles for a read operation.
Address bits 14 and 15 are is not subject to auto-increment/decrement if configured as Chip Select.
The PMD<15:8> bits are not active is the MODE16 bit = 1.
DS60001191F-page 360
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-3:
Bit
Range
31:24
23:16
15:8
7:0
PMADDR: PARALLEL PORT ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
R/W-0
(3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2
CS1
ADDR15(2)
ADDR14(4)
R/W-0
R/W-0
ADDR<13:8>
R/W-0
R/W-0
R/W-0
R/W-0
ADDR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
CS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15
ADDR<15>: Target Address bit 15(2)
bit 14
CS1: Chip Select 1 bit(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14
ADDR<14>: Target Address bit 14(4)
bit 13-0
ADDR<13:0>: Address bits
Note 1:
2:
3:
4:
When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.
When the CSF<1:0> bits (PMCON<7:6>) = 00.
When the CSF<1:0> bits (PMCON<7:6>) = 10.
When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.
Note:
If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target
addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the
PMRADDR register for Read operations and the PMWADDR register for Write operations.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 361
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-4:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN<15:14>
R/W-0
7:0
PMAEN: PARALLEL PORT PIN ENABLE REGISTER
PTEN<13:8>
R/W-0
R/W-0
PTEN<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 15-14 PTEN<15:14>: PMCS1 Strobe Enable bits
1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS1 and PMCS2(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-2
PTEN<13:2>: PMP Address Port Enable bits
1 = PMA<13:2> function as PMP address lines
0 = PMA<13:2> function as port I/O
bit 1-0
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1:
The use of these pins as PMA15 and PMA14 or CS1 and CS2 is selected by the CSF<1:0> bits in the
PMCON register.
The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX<1:0> in the PMCON register.
2:
DS60001191F-page 362
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 23-5:
Bit
Range
31:24
23:16
15:8
7:0
PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0, HS, SC
U-0
U-0
R-0
R-0
R-0
R-0
IB0F
IBF
IBOV
—
—
IB3F
IB2F
IB1F
R-1
R/W-0, HS, SC
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
HS = Hardware Set
SC = Software Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
0 = No overflow occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8
IBxF: Input Buffer x Status Full bits
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OBxE: Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
 2013-2016 Microchip Technology Inc.
DS60001191F-page 363
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 364
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
24.0
EXTERNAL BUS INTERFACE
(EBI)
Note:
TABLE 24-1:
Feature
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 47. “External Bus
Interface (EBI)” (DS60001245), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The External Bus Interface (EBI) module provides a
high-speed, convenient way to interface external
parallel memory devices to the PIC32MZ EC family
device.
Number of Device
Pins
100
124
144
Async SRAM
Y
Y
Y
Async NOR Flash
Y
Y
Y
Available address lines
20
20
24
8-bit data bus support
Y
Y
Y
16-bit data bus support
Y
Y
Y
Available Chip Selects
1
1
4
Timing mode sets
3
3
3
8-bit R/W from 16-bit bus
N
N
Y
Non-memory device
Y
Y
Y
LCD
Y
Y
Y
Note:
With the EBI module, it is possible to connect
asynchronous SRAM and NOR Flash devices, as well
as non-memory devices such as camera sensors and
LCDs.
The features of the EBI module depend on the pin
count of the PIC32MZ EC device, as shown in
Table 24-1.
FIGURE 24-1:
EBI MODULE FEATURES
Once the EBI module is configured, external devices will be memory mapped and
can be access from KSEG2 memory
space (see Figure 4-1 through Figure 4-4
in Section 4.0 “Memory Organization”
for more information). The MMU must be
enabled and the TLB must be set up to
access this memory (see Section 50.
“CPU for Devices with MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192) in the “PIC32 Family Reference Manual” for more information).
EBI SYSTEM BLOCK DIAGRAM
External Bus Interface
Bus Interface
Memory Interface
EBIA<23:0>
EBID<15:0>
PBCLK8
Control
Registers
Address Decoder
EBIBS<1:0>
EBICS<3:0>
System
Bus
Data
FIFO
Control Registers
EBIOE
EBIRP
Static Memory Controller
Address
FIFO
 2013-2016 Microchip Technology Inc.
EBIWE
EBIRDY<3:1>
DS60001191F-page 365
EBI Control Registers
Register
Name
Bit Range
EBI REGISTER MAP
Virtual Address
(BF8E_#)
TABLE 24-2:
1014
EBICS0(1)
31:16
1018
(2)
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
CSADDR<15:0>
—
—
—
—
—
—
—
0000
1000
—
—
CSADDR<15:0>
—
—
—
—
—
—
—
0000
2040
—
—
—
CSADDR<15:0>
—
—
—
—
—
—
—
0000
1040
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
REGSEL<2:0>
—
—
—
MEMTYPE<2:0>
—
—
—
—
MEMSIZE<4:0>
—
—
—
0020
0000
—
—
—
—
—
REGSEL<2:0>
—
—
—
MEMTYPE<2:0>
—
—
—
—
MEMSIZE<4:0>
—
—
—
0020
0000
—
—
—
—
—
—
—
REGSEL<2:0>
—
—
—
MEMTYPE<2:0>
—
—
—
—
MEMSIZE<4:0>
—
—
—
0120
0000
—
—
—
—
—
—
—
—
REGSEL<2:0>
MEMTYPE<2:0>
RDYMODE PAGESIZE<1:0> PAGEMODE
TPRC<3:0>
—
—
TWP<5:0>
—
—
—
TWR<1:0>
TAS<1:0>
RDYMODE PAGESIZE<1:0> PAGEMODE
TPRC<3:0>
15:0
31:16
—
—
TWP<5:0>
—
—
—
TWR<1:0>
TAS<1:0>
RDYMODE PAGESIZE<1:0> PAGEMODE
TPRC<3:0>
15:0
31:16
—
—
TWP<5:0>
—
—
—
—
TWR<1:0>
—
—
TAS<1:0>
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
SMDWIDTH2<2:0>
SMDWIDTH1<2:0>
SMDWIDTH0<2:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is available on 144-pin devices only.
—
EBICS1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
15:0
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
(1)
15:0
31:16
—
—
—
—
—
—
—
—
—
—
(2)
15:0
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
15:0
31:16
—
—
15:0
31:16
101C EBICS2(2)
1020
EBICS3
(2)
1054 EBIMSK0
1058 EBIMSK1
105C EBIMSK2(2)
(2)
1060 EBIMSK3
1094
1098
109C
EBISMT0
EBISMT1
EBISMT2
 2013-2016 Microchip Technology Inc.
10A0 EBIFTRPD
10A4 EBISMCON
Legend:
Note 1:
2:
23/7
All Resets
Bits
CSADDR<15:0>
—
—
—
2000
MEMSIZE<4:0>
TBTA<2:0>
0120
041C
TRC<5:0>
TBTA<2:0>
2D4B
041C
TBTA<2:0>
2D4B
041C
TRC<5:0>
—
TRPD<11:0>
—
—
—
TRC<5:0>
—
—
—
—
2d$b
0000
—
—
—
—
—
00C8
0000
—
—
—
—
SMRP
0201
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 366
24.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 24-1:
Bit
Range
31:24
23:16
15:8
7:0
EBICSx: EXTERNAL BUS INTERFACE CHIP SELECT REGISTER (‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CSADDR<15:8>
R/W-0
CSADDR<7:0>
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 CSADDR<15:0>: Base Address for Device bits
Address in physical memory, which will select the external device.
bit 15-0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 367
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 24-2:
Bit
Range
31:24
23:16
15:8
7:0
EBIMSKx: EXTERNAL BUS INTERFACE ADDRESS MASK REGISTER (‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
REGSEL<2:0>
R/W-0
R/W-0
R/W-0
MEMSIZE<4:0>(1)
MEMTYPE<2:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8
REGSEL<2:0>: Timing Register Set for Chip Select ‘x’ bits
111 = Reserved
•
•
•
011 = Reserved
010 = Use EBISMT2
001 = Use EBISMT1
000 = Use EBISMT0
bit 7-5
MEMTYPE<2:0>: Select Memory Type for Chip Select ‘x’ bits
111 = Reserved
•
•
•
011 = Reserved
010 = NOR-Flash
001 = SRAM
000 = Reserved
bit 4-0
MEMSIZE<4:0>: Select Memory Size for Chip Select ‘x’ bits(1)
11111 = Reserved
•
•
•
01010 = Reserved
01001 = 16 MB
01000 = 8 MB
00111 = 4 MB
00110 = 2 MB
00101 = 1 MB
00100 = 512 KB
00011 = 256 KB
00010 = 128 KB
00001 = 64 KB (smaller memories alias within this range)
00000 = Chip Select is not used
Note 1:
The specified value for these bits depends on the number of available address lines. Refer to the specific
device pin table (Table 2 through Table 5) for the available address lines.
DS60001191F-page 368
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 24-3:
Bit
Range
31:24
23:16
15:8
7:0
EBISMTx: EXTERNAL BUS INTERFACE STATIC MEMORY TIMING REGISTER 
(‘x’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-1
R/W-0
R/W-0
—
RDYMODE
R/W-1
R/W-1
R/W-1
TPRC<3:0>(1)
PAGEMODE
R/W-0
Bit
26/18/10/2
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
TAS<1:0>(1)
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
TBTA<2:0>(1)
R/W-1
R/W-1
TWP<5:0>(1)
R/W-0
PAGESIZE<1:0>
R/W-0
R/W-1
TWR<1:0>(1)
R/W-1
R/W-0
R/W-1
R/W-1
TRC<5:0>(1)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
RDYMODE: Data Ready Device Select bit
The device associated with register set ‘x’ is a data-ready device, and will use the EBIRDYx pin.
1 = EBIRDYx input is used
0 = EBIRDYx input is not used
bit 25-24 PAGESIZE<1:0>: Page Size for Page Mode Device bits
11 = 32-word page
10 = 16-word page
01 = 8-word page
00 = 4-word page
bit 23
PAGEMODE: Memory Device Page Mode Support bit
1 = Device supports Page mode
0 = Device does not support Page mode
bit 22-19 TPRC<3:0>: Page Mode Read Cycle Time bits(1)
Read cycle time is TPRC + 1 clock cycle.
bit 18-16 TBTA<2:0>: Data Bus Turnaround Time bits(1)
Clock cycles (0-7) for static memory between read-to-write, write-to-read, and read-to-read when Chip
Select changes.
bit 15-10 TWP<5:0>: Write Pulse Width bits(1)
Write pulse width is TWP + 1 clock cycle.
bit 9-8
TWR<1:0>: Write Address/Data Hold Time bits(1)
Number of clock cycles to hold address or data on the bus.
bit 7-6
TAS<1:0>: Write Address Setup Time bits(1)
Clock cycles for address setup time. A value of ‘0’ is only valid in the case of SSRAM.
bit 5-0
TRC<5:0>: Read Cycle Time bits(1)
Read cycle time is TRC + 1 clock cycle.
Note 1:
Please refer to Section 47. “External Bus Interface (EBI)” (DS60001245) in the “PIC32 Family Reference Manual” for the EBI timing diagrams and additional information.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 369
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 24-4:
Bit
Range
31:24
23:16
15:8
7:0
EBIFTRPD: EXTERNAL BUS INTERFACE FLASH TIMING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
TRPD<11:8>
R/W-0
R/W-0
TRPD<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-0
TRPD<11:0>: Flash Timing bits
These bits define the number of clock cycles to wait after resetting the external Flash memory before any
read/write access.
DS60001191F-page 370
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 24-5:
Bit
Range
Bit
31/23/15/7
U-0
31:24
23:16
15:8
7:0
EBISMCON: EXTERNAL BUS INTERFACE STATIC MEMORY CONTROL
REGISTER
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
U-0
U-0
U-0
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
SMDWIDTH2<2:0>
SMDWIDTH1<2:0>
SMDWIDTH0<2:1>
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
SMDWIDTH0<0>
—
—
—
—
—
—
SMRP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 SMDWIDTH2<2:0>: Static Memory Width for Register EBISMT2 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 12-10 SMDWIDTH1<2:0>: Static Memory Width for Register EBISMT1 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 9-7
SMDWIDTH0<2:0>: Static Memory Width for Register EBISMT0 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 6-1
Unimplemented: Read as ‘0’
bit 0
SMRP: Flash Reset/Power-down mode Select bit
After a Reset, the controller internally performs a power-down for Flash, and then sets this bit to ‘1’.
1 = Flash is taken out of Power-down mode
0 = Flash is forced into Power-down mode
 2013-2016 Microchip Technology Inc.
DS60001191F-page 371
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 372
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
25.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
This data sheet summarizes the
features of the PIC32MZ Embedded
Connectivity (EC) Family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 29. “Real-Time Clock and
Calendar (RTCC)”
(DS60001125),
which
is
available
from
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The RTCC module is intended for applications in which
accurate time must be maintained for extended periods
of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime
while keeping track of time.
The following are key features of the RTCC module:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FIGURE 25-1:
Time: hours, minutes and seconds
24-hour format (military time)
Visibility of one-half second period
Provides calendar: Weekday, date, month and year
Alarm intervals are configurable for half of a second,
one second, 10 seconds, one minute, 10 minutes,
one hour, one day, one week, one month, and one
year
Alarm repeat with decrementing counter
Alarm with indefinite repeat: Chime
Year range: 2000 to 2099
Leap year correction
BCD format for smaller firmware overhead
Optimized for long-term battery operation
Fractional second synchronization
User calibration of the clock crystal frequency with
auto-adjust
Calibration range: 0.66 seconds error per month
Calibrates up to 260 ppm of crystal error
Uses external 32.768 kHz crystal or 32 kHz
internal oscillator
Alarm pulse, seconds clock, or internal clock output
on RTCC pin
RTCC BLOCK DIAGRAM
RTCCLKSEL<1:0>
32.768 kHz Input from
Secondary Oscillator (SOSC)
32 kHz Input from
Internal Oscillator (LPRC)
TRTC
RTCC Prescalers
0.5 seconds
RTCC Timer
Alarm
Event
YEAR, MTH, DAY
RTCVAL
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
TRTC
RTCOE
RTCOUTSEL<1:0>
 2013-2016 Microchip Technology Inc.
DS60001191F-page 373
RTCC Control Registers
0C00 RTCCON
0C10 RTCALRM
0C20 RTCTIME
0C30 RTCDATE
0C40 ALRMTIME
0C50 ALRMDATE
Legend:
Note 1:
RTCC REGISTER MAP
31/15
30/14
31:16
—
15:0
31:16
ON
—
15:0 ALRMEN
31:16
—
15:0
—
31:16
29/13
28/12
27/11
—
—
—
—
—
—
SIDL
—
—
—
—
—
CHIME
PIV
ALRMSYNC
—
26/10
25/9
24/8
23/7
22/6
21/5
—
SEC10<2:0>
YEAR10<3:0>
—
—
—
—
—
SEC01<3:0>
—
—
—
—
YEAR01<3:0>
—
—
—
MONTH10
—
—
—
DAY10<1:0>
DAY01<3:0>
—
31:16
—
—
HR10<1:0>
HR01<3:0>
—
15:0
—
SEC01<3:0>
—
—
—
—
31:16
—
—
—
—
—
MONTH10
15:0
—
—
—
—
16/0
—
0000
—
—
—
—
xxxx
—
MONTH01<3:0>
—
MIN10<2:0>
—
—
MONTH01<3:0>
xx00
xxxx
xx00
WDAY01<2:0>
MIN01<3:0>
—
0000
0000
0000
MIN01<3:0>
—
—
17/1
RTCWREN RTCSYNC HALFSEC RTCOE
—
—
—
—
MIN10<2:0>
—
—
18/2
ARPT<7:0>
HR01<3:0>
15:0
SEC10<2:0>
19/3
CAL<9:0>
RTCCLKSEL<1:0> RTCOUTSEL<1:0> RTCCLKON
—
—
—
—
—
AMASK<3:0>
HR10<1:0>
20/4
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 25-1:
xxxx
—
xx00
00xx
DAY01<3:0>
—
—
—
—
—
xx0x
DAY10<1:0>
WDAY01<2:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 374
25.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-1:
Bit
Range
Bit
31/23/15/7
U-0
31:24
23:16
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL<9:8>
R/W-0
R/W-0
R/W-0
CAL<7:0>
15:8
7:0
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
ON(1)
—
SIDL
—
—
RTCCLKSEL<1:0>
R/W-0
R-0
U-0
U-0
R/W-0
R-0
—
RTC
WREN(3)
RTC
SYNC
RTC
RTC
OUTSEL<0>(2) CLKON(5)
—
RTC
OUTSEL<1>(2)
R-0
R/W-0
(4)
HALFSEC
RTCOE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 real-time clock pulses every one minute
bit 15
ON: RTCC On bit(1)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Disables RTCC operation when CPU enters Idle mode
0 = Continue normal operation when CPU enters Idle mode
bit 12-11 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
Note:
The ON bit is only writable when RTCWREN = 1.
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
This bit is undefined when RTCCLKSEL<1:0> = 00 (LPRC is the clock source).
This register is reset only on a Power-on Reset (POR).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 375
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-1:
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
(CONTINUED)
bit 10-9
RTCCLKSEL<1:0>: RTCC Clock Select bits
When a new value is written to these bits, the Seconds Value register should also be written to properly
reset the clock prescalers in the RTCC.
11 = Reserved
10 = Reserved
01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
00 = RTCC uses the internal 32 kHz oscillator (LPRC)
bit 8-7
RTCOUTSEL<1:0>: RTCC Output Data Select bits(2)
11 = Reserved
10 = RTCC Clock is presented on the RTCC pin
01 = Seconds Clock is presented on the RTCC pin
00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
bit 6
RTCCLKON: RTCC Clock Enable Status bit(5)
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4
Unimplemented: Read as ‘0’
bit 3
RTCWREN: Real-Time Clock Value Registers Write Enable bit(3)
1 = Real-Time Clock Value registers can be written to by the user
0 = Real-Time Clock Value registers are locked out from being written to by the user
bit 2
RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit
1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid
data read). If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = Real-time clock value registers can be read without concern about a rollover ripple
bit 1
HALFSEC: Half-Second Status bit(4)
1 = Second half period of a second
0 = First half period of a second
bit 0
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is not enabled
Note 1:
2:
3:
4:
5:
The ON bit is only writable when RTCWREN = 1.
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
This bit is undefined when RTCCLKSEL<1:0> = 00 (LPRC is the clock source).
Note:
This register is reset only on a Power-on Reset (POR).
DS60001191F-page 376
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-2:
Bit
Range
31:24
23:16
15:8
7:0
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R-0
R/W-0
R/W-0
CHIME(2)
R/W-0
(2)
R/W-0
ALRMEN(1,2)
R/W-0
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIV
ALRMSYNC
R/W-0
AMASK<3:0>
R/W-0
ARPT<7:0>(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00
bit 13
PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12
ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. 
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is more than
32 real-time clocks away from a half-second rollover
bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(2)
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved
1011 = Reserved
11xx = Reserved
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
This register is reset only on a Power-on Reset (POR).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 377
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-2:
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED)
ARPT<7:0>: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times
bit 7-0
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
This register is reset only on a Power-on Reset (POR).
DS60001191F-page 378
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-3:
Bit
Range
31:24
23:16
15:8
7:0
RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
U-0
R/W-x
—
U-0
HR10<1:0>
R/W-x
R/W-x
HR01<3:0>
MIN10<2:0>
R/W-x
—
R/W-x
R/W-x
R/W-x
MIN01<3:0>
R/W-x
R/W-x
R/W-x
SEC10<2:0>
R/W-x
R/W-x
SEC01<3:0>
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 HR10<1:0>: Binary-Coded Decimal Value of Hours bits, tens digit; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, ones digit; contains a value from 0 to 9
bit 23
Unimplemented: Read as ‘0’
bit 22-20 MIN10<2:0>: Binary-Coded Decimal Value of Minutes bits, tens digit; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, ones digit; contains a value from 0 to 9
bit 15
Unimplemented: Read as ‘0’
bit 14-12 SEC10<2:0>: Binary-Coded Decimal Value of Seconds bits, tens digit; contains a value from 0 to 5
bit 11-8
SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, ones digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1 (RTCCON<3>).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 379
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-4:
Bit
Range
31:24
23:16
15:8
7:0
RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
MONTH10
U-0
U-0
R/W-x
R/W-x
YEAR10<3:0>
YEAR01<3:0>
R/W-x
R/W-x
MONTH01<3:0>
R/W-x
R/W-x
R/W-x
—
—
U-0
U-0
U-0
DAY10<1:0>
U-0
U-0
—
—
—
—
—
R/W-x
R/W-x
DAY01<3:0>
R/W-x
R/W-x
WDAY01<2:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, tens digit
bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, ones digit
bit 23-21 Unimplemented: Read as ‘0’
bit 20
MONTH10: Binary-Coded Decimal Value of Months bit, tens digit; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, ones digit; contains a value from 0 to 9
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAY10<1:0>: Binary-Coded Decimal Value of Days bits, tens digit; contains a value from 0 to 3
bit 11-8
DAY01<3:0>: Binary-Coded Decimal Value of Days bits, ones digit; contains a value from 0 to 9
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY01<2:0>: Binary-Coded Decimal Value of Weekdays bits, ones digit; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1 (RTCCON<3>).
DS60001191F-page 380
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-5:
Bit
Range
31:24
23:16
15:8
7:0
ALRMTIME: ALARM TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
U-0
R/W-x
—
U-0
HR10<1:0>
R/W-x
R/W-x
HR01<3:0>
MIN10<2:0>
R/W-x
—
R/W-x
R/W-x
R/W-x
MIN01<3:0>
R/W-x
R/W-x
R/W-x
SEC10<2:0>
R/W-x
R/W-x
SEC01<3:0>
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 HR10<1:0>: Binary Coded Decimal value of hours bits, tens digit; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, ones digit; contains a value from 0 to 9
bit 23
Unimplemented: Read as ‘0’
bit 22-20 MIN10<2:0>: Binary Coded Decimal value of minutes bits, tens digit; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, ones digit; contains a value from 0 to 9
bit 15
Unimplemented: Read as ‘0’
bit 14-12 SEC10<2:0>: Binary Coded Decimal value of seconds bits, tens digit; contains a value from 0 to 5
bit 11-8
SEC01<3:0>: Binary Coded Decimal value of seconds bits, ones digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
 2013-2016 Microchip Technology Inc.
DS60001191F-page 381
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 25-6:
Bit
Range
31:24
23:16
15:8
7:0
ALRMDATE: ALARM DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MONTH10
U-0
U-0
R/W-x
R/W-x
MONTH01<3:0>
—
—
U-0
U-0
U-0
DAY10<1:0>
U-0
U-0
—
—
—
—
—
R/W-x
R/W-x
DAY01<3:0>
R/W-x
R/W-x
WDAY01<2:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20
MONTH10: Binary Coded Decimal value of months bit, tens digit; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, ones digit; contains a value from 0 to 9
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAY10<1:0>: Binary Coded Decimal value of days bits, tens digit; contains a value from 0 to 3
bit 11-8
DAY01<3:0>: Binary Coded Decimal value of days bits, ones digit; contains a value from 0 to 9
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY01<2:0>: Binary Coded Decimal value of weekdays bits, ones digit; contains a value from 0 to 6
DS60001191F-page 382
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
Note:
CRYPTO ENGINE
Bulk ciphers that are handled by the Crypto Engine
include:
This data sheet summarizes the
features of the PIC32MZ Embedded
Connectivity (EC) Family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 49. “Crypto Engine (CE) and
Random Number Generator (RNG)”
(DS60001246), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Crypto Engine is intended to accelerate applications that need cryptographic functions. By executing
these functions in the hardware module, software
overhead is reduced, and actions such as encryption, decryption, and authentication can execute
much more quickly.
The Crypto Engine uses an internal descriptor-based
DMA for efficient programming of the security
association data and packet pointers (allowing
scatter/gather data fetching). An intelligent state
machine schedules the Crypto Engines based on the
protocol selection and packet boundaries. The hardware engines can perform the encryption and
authentication in sequence or in parallel.
Note:
To avoid cache coherency problems on
devices with L1 cache, Crypto buffers
must only be allocated or accessed from
the KSEG1 segment.
Key features of the Crypto Engine include:
• Bulk ciphers and hash engines
• Integrated DMA to off-load processing:
- Buffer descriptor-based
- Secure association per buffer descriptor
• Some functions can execute in parallel
FIGURE 26-1:
• AES:
- 128-bit, 192-bit, and 256-bit key sizes
- CBC, ECB, CTR, CFB, and OFB modes
• DES/TDES:
- CBC, ECB, CFB, and OFB modes
Authentication engines that are available through the
Crypto Engine include:
•
•
•
•
•
SHA-1
SHA-256
MD-5
AES-GCM
HMAC operation (for all authentication engines)
The rate of data that can be processed by the Crypto
Engine depends on a number of factors, including:
• Which engine is in use
• Whether the engines are used in parallel or in series
• The demands on source and destination memories
by other parts of the system (i.e., CPU, DMA, etc.)
• The speed of PBCLK5, which drives the Crypto
Engine
Table 26-1 shows typical performance for various
engines.
TABLE 26-1:
CRYPTO ENGINE
PERFORMANCE
Engine/
Algorithm
Performance
Factor
(Mbps/MHz)
Maximum Mbps
(PBCLK5 = 100 MHz)
DES
TDES
AES-128
AES-192
AES-256
MD5
SHA-1
SHA-256
14.4
6.6
9.0
7.9
7.2
15.6
13.2
9.3
1440
660
900
790
720
1560
1320
930
CRYPTO ENGINE BLOCK DIAGRAM
INB
FIFO
Packet
RD
DMA
Controller
Crypto
FSM
System
Bus
SFR
System
Bus
OUTB
FIFO
Packet
WR
AES
Local Bus
26.0
TDES
SHA-1
SHA-256
MD5
PBCLK5
 2013-2016 Microchip Technology Inc.
DS60001191F-page 383
Crypto Engine Control Registers
Virtual Address
(BF8E_#)
Register
Name
TABLE 26-2:
5000
CEVER
CRYPTO ENGINE REGISTER MAP
5004
CECON
5008
CEBDADDR
500C
5010
CEBDPADDR
CESTAT
5014
CEINTSRC
5018
CEINTEN
501C
CEPOLLCON
5020
5024
Legend:
CEHDLEN
CETRLLEN
31/15
30/14
29/13
31:16
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
REVISION<7:0>
20/4
19/3
18/2
17/1
16/0
VERSION<7:0>
15:0
0000
ID<15:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
31:16
0000
—
—
SWRST SWAPEN
—
—
—
—
—
—
—
31:16
0000
0000
0000
BASEADDR<31:0>
15:0
31:16
ERRMODE<2:0>
ERROP<2:0>
ERRPHASE<1:0>
15:0
—
0000
—
BDSTATE<3:0>
START
ACTIVE 0000
BDCTRL<15:0>
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
AREIF
PKTIF
CBDIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
AREIE
PKTIE
CBDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
0000
PENDIE 0000
0000
0000
HDRLEN<7:0>
—
0000
PENDIF 0000
BDPPLCON<15:0>
31:16
0000
BDPCHST BDPPLEN DMAEN 0000
BDPADDR<31:0>
15:0
All Resets
Bit Range
Bits
—
—
—
—
TRLRLEN<7:0>
0000
0000
0000
0000
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 384
26.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-1:
Bit
Range
31:24
23:16
15:8
7:0
CEVER: CRYPTO ENGINE REVISION, VERSION, AND ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REVISION<7:0>
R-0
R-0
VERSION<7:0>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
ID<15:8>
ID<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 REVISION<7:0>: Crypto Engine Revision bits
bit 23-16 VERSION<7:0>: Crypto Engine Version bits
bit 15-0
ID<15:0>: Crypto Engine Identification bits
 2013-2016 Microchip Technology Inc.
DS60001191F-page 385
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-2:
Bit
Range
31:24
23:16
15:8
7:0
CECON: CRYPTO ENGINE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0, HC
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
SWRST
SWAPEN
—
—
BDPCHST
BDPPLEN
DMAEN
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-7
Unimplemented: Read as ‘0’
bit 6
SWRST: Software Reset bit
1 = Initiate a software reset of the Crypto Engine
0 = Normal operation
bit 5
SWAPEN: I/O Swap Enable bit
1 = Input data is byte swapped when read by dedicated DMA
0 = Input data is not byte swapped when read by dedicated DMA
bit 4-3
Unimplemented: Read as ‘0’
bit 2
BDPCHST: Buffer Descriptor Processor (BDP) Fetch Enable bit
This bit should be enabled only after all DMA descriptor programming is completed.
1 = BDP descriptor fetch is enabled
0 = BDP descriptor fetch is disabled
bit 1
BDPPLEN: Buffer Descriptor Processor Poll Enable bit
This bit should be enabled only after all DMA descriptor programming is completed.
1 = Poll for descriptor until valid bit is set
0 = Do not poll
bit 0
DMAEN: DMA Enable bit
1 = Crypto Engine DMA is enabled
0 = Crypto Engine DMA is disabled
DS60001191F-page 386
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-3:
Bit
Range
31:24
23:16
15:8
7:0
CEBDADDR: CRYPTO ENGINE BUFFER DESCRIPTOR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDPADDR<31:24>
R-0
R-0
BDPADDR<23:16>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDPADDR<15:8>
R-0
R-0
BDPADDR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
BDPADDR<31:0>: Current Buffer Descriptor Process Address Status bits
These bits contain the current descriptor address that is being processed by the Buffer Descriptor Processor
(BDP).
REGISTER 26-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CEBDPADDR: CRYPTO ENGINE BUFFER DESCRIPTOR PROCESSOR
REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR<23:16>
R/W-0
R/W-0
BASEADDR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BASEADDR<31:0>: Buffer Descriptor Base Address bits
These bits contain the physical address of the first Buffer Descriptor in the Buffer Descriptor chain. When
enabled, the Crypto DMA begins fetching Buffer Descriptors from this address.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 387
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-5:
Bit
Range
31:24
CESTAT: CRYPTO ENGINE STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
R-0
R-0
R-0
R-0
ERRMODE<2:0>
23:16
15:8
U-0
U-0
—
—
R-0
R-0
Bit
27/19/11/3
Bit
26/18/10/2
R-0
R-0
ERROP<2:0>
R-0
R-0
R-0
R-0
R-0
Bit
24/16/8/0
R-0
R-0
ERRPHASE<1:0>
R-0
R-0
R-0
START
ACTIVE
R-0
R-0
R-0
R-0
R-0
R-0
BDSTATE
R-0
Bit
25/17/9/1
BDCTRL<15:8>
R-0
7:0
R-0
R-0
R-0
R-0
BDCTRL<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 ERRMOD<2:0>: Internal Error Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
000 = Normal operation
bit 28-26 ERROP<2:0>: Internal Error Operation Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Authentication
011 = Reserved
010 = Decryption
001 = Encryption
000 = Reserved
bit 25-24 ERRPHASE<1:0>: Internal Error Phase of DMA Status bits
11 = Destination data
10 = Source data
01 = Security Association (SA) access
00 = Buffer Descriptor (BD) access
bit 23-22 Unimplemented: Read as ‘0’
bit 21-18 BDSTATE<3:0>: Buffer Descriptor Processor State Status bits
These bits contain a number, which indicates the current state of the BDP:
1111 = Reserved
•
•
•
bit 17
0111 = Reserved
0110 = SA fetch
0101 = Fetch BDP is disabled
0100 = Descriptor is done
0011 = Data phase
0010 = BDP is loading
0001 = Descriptor fetch request is pending
0000 = BDP is idle
START: DMA Start Status bit
1 = DMA start has occurred
0 = DMA start has not occurred
DS60001191F-page 388
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-5:
bit 16
bit 15-0
CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED)
ACTIVE: Buffer Descriptor Processor Status bit
1 = BDP is active
0 = BDP is idle
BDCTRL<15:0>: Descriptor Control Word Status bits
These bits contain the current descriptor control word.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 389
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-6:
Bit
Range
31:24
23:16
15:8
7:0
CEINTSRC: CRYPTO ENGINE INTERRUPT SOURCE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
AREIF
PKTIF
CBDIF
PENDIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3
AREIF: Access Response Error Interrupt bit
1 = Error occurred trying to access memory outside the Crypto Engine
0 = No error has occurred
bit 2
PKTIF: DMA Packet Completion Interrupt Status bit
1 = DMA packet was completed
0 = DMA packet was not completed
bit 1
CBDIF: BD Transmit Status bit
1 = Last BD transmit was processed
0 = Last BD transmit has not been processed
bit 0
PENDIF: Crypto Engine Interrupt Pending Status bit
1 = Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine)
0 = Crypto Engine interrupt is not pending
DS60001191F-page 390
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-7:
Bit
Range
31:24
23:16
15:8
7:0
CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
AREIE
PKTIE
BDPIE
PENDIE(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3
AREIE: Access Response Error Interrupt Enable bit
1 = Access response error interrupts are enabled
0 = Access response error interrupts are not enabled
bit 2
PKTIE: DMA Packet Completion Interrupt Enable bit
1 = DMA packet completion interrupts are enabled
0 = DMA packet completion interrupts are not enabled
bit 1
BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit
1 = BDP interrupts are enabled
0 = BDP interrupts are not enabled
bit 0
PENDIE: Master Interrupt Enable bit(1)
1 = Crypto Engine interrupts are enabled
0 = Crypto Engine interrupts are not enabled
Note 1:
The PENDIE bit is a Global enable bit and must be enabled together with the other interrupts desired.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 391
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-8:
Bit
Range
31:24
23:16
15:8
7:0
CEPOLLCON: CRYPTO ENGINE POLL CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDPPLCON<15:8>
R/W-0
R/W-0
BDPPLCON<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BDPPLCON<15:0>: Buffer Descriptor Processor Poll Control bits
These bits determine the number of SYSCLK cycles that the Crypto DMA would wait before refetching the
descriptor control word if the Buffer Descriptor fetched was disabled.
DS60001191F-page 392
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 26-9:
Bit
Range
31:24
23:16
15:8
7:0
CEHDLEN: CRYPTO ENGINE HEADER LENGTH REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HDRLEN<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
HDRLEN<7:0>: DMA Header Length bits
For every packet, skip this length of locations and start filling the data.
x = Bit is unknown
REGISTER 26-10: CETRLLEN: CRYPTO ENGINE TRAILER LENGTH REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRLRLEN<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
TRLRLEN<7:0>: DMA Trailer Length bits
For every packet, skip this length of locations at the end of the current packet and start putting the next
packet.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 393
PIC32MZ Embedded Connectivity (EC) Family
26.2
Crypto Engine Buffer Descriptors
Host software creates a linked list of buffer descriptors
and the hardware updates them. Table 26-3 provides a
list of the Crypto Engine buffer descriptors, followed by
format descriptions of each buffer descriptor (see
Figure 26-2 through Figure 26-9).
TABLE 26-3:
Name (see Note 1)
BD_CTRL
CRYPTO ENGINE BUFFER DESCRIPTORS
Bit
31/2315/7
Bit
30/22/14/6
31:24
DESC_EN
—
23:16
—
SA_FETCH_EN
15:8
7:0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
LAST_BD
LIFM
CRY_MODE<2:0>
—
—
—
23:16
BD_SAADDR<23:16>
15:8
BD_SAADDR<15:8>
BD_SRCADDR<31:24>
23:16
BD_SRCADDR<23:16>
15:8
BD_SRCADDR<15:8>
BD_SRCADDR<7:0>
BD_DSTADDR 31:24
BD_DSTADDR<31:24>
23:16
BD_DSTADDR<23:16>
15:8
BD_DSTADDR<15:8>
BD_UPDPTR
7:0
BD_DSTADDR<7:0>
31:24
BD_NXTADDR<31:24>
23:16
BD_NXTADDR<23:16>
15:8
BD_NXTADDR<15:8>
7:0
BD_NXTADDR<7:0>
31:24
BD_UPDADDR<31:24>
23:16
BD_UPDADDR<23:16>
15:8
BD_UPDADDR<15:8>
7:0
BD_UPDADDR<7:0>
BD_MSG_LEN 31:24
MSG_LENGTH<31:24>
23:16
MSG_LENGTH<23:16>
15:8
MSG_LENGTH<15:8>
7:0
MSG_LENGTH<7:0>
BD_ENC_OFF 31:24
ENCR_OFFSET<31:24>
23:16
ENCR_OFFSET<23:16>
15:8
ENCR_OFFSET<15:8>
7:0
ENCR_OFFSET<7:0>
Note
1:
—
BD_SAADR<7:0>
BD_SCRADDR 31:24
BD_NXTPTR
—
PKT_INT_EN CBD_INT_EN
BD_BUFLEN<7:0>
BD_SAADDR<31:24>
7:0
Bit
24/16/8/0
BD_BUFLEN<15:8>
BD_SA_ADDR 31:24
7:0
Bit
25/17/9/1
The buffer descriptor must be allocated in memory on a 64-bit boundary.
DS60001191F-page 394
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 26-2:
FORMAT OF BD_CTRL
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
31-24
DESC_EN
23-16
—
—
SA_
FETCH_EN
Bit
29/21/13/5
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
CRY_MODE<2:0>
—
—
LIFM
—
PKT_
INT_EN
—
CBD_
INT_EN
—
Bit
28/20/12/4
Bit
27/19/11/3
LAST_BD
15-8
BD_BUFLEN<15:8>
7-0
BD_BUFLEN<7:0>
bit 31
DESC_EN: Descriptor Enable
1 = The descriptor is owned by hardware. After processing the BD, hardware resets this bit to ‘0’.
0 = The descriptor is owned by software
bit 30
Unimplemented: Must be written as ‘0’
bit 29-27 CRY_MODE<2:0>: Crypto Mode
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
000 = Normal operation
bit 22
SA_FETCH_EN: Fetch Security Association From External Memory
1 = Fetch SA from the SA pointer. This bit needs to be set to ‘1’ for every new packet.
0 = Use current fetched SA or the internal SA
bit 21-20 Unimplemented: Must be written as ‘0’
bit 19
LAST_BD: Last Buffer Descriptors
1 = Last Buffer Descriptor in the chain
0 = More Buffer Descriptors in the chain
After the last BD, the CEBDADDR goes to the base address in CEBDPADDR.
bit 18
LIFM: Last In Frame
In case of Receive Packets (from H/W-> Host), this field is filled by the Hardware to indicate whether the
packet goes across multiple buffer descriptors. In case of transmit packets (from Host -> H/W), this field
indicates whether this BD is the last in the frame.
bit 17
PKT_INT_EN: Packet Interrupt Enable
Generate an interrupt after processing the current buffer descriptor, if it is the end of the packet.
bit 16
CBD_INT_EN: CBD Interrupt Enable
Generate an interrupt after processing the current buffer descriptor.
bit 15-0
BD_BUFLEN<15:0>: Buffer Descriptor Length
This field contains the length of the buffer and is updated with the actual length filled by the receiver.
FIGURE 26-3:
Bit
Range
FORMAT OF BD_SADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_SAADDR<31:24>
23-16
BD_SAADDR<23:16>
15-8
BD_SAADDR<15:8>
7-0
BD_SAADDR<7:0>
bit 31-0
Bit
25/17/9/1
Bit
24/16/8/0
BD_SAADDR<31:0>: Security Association IP Session Address
The sessions’ SA pointer has the keys and IV values.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 395
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 26-4:
Bit
Range
FORMAT OF BD_SRCADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_SCRADDR<31:24>
23-16
BD_SCRADDR<23:16>
15-8
BD_SCRADDR<15:8>
7-0
BD_SCRADDR<7:0>
bit 31-0
BD_SCRADDR: Buffer Source Address
The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or
authentication. This address must be on a 32-bit boundary.
FIGURE 26-5:
Bit
Range
FORMAT OF BD_DSTADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_DSTADDR<31:24>
23-16
BD_DSTADDR<23:16>
15-8
BD_DSTADDR<15:8>
7-0
BD_DSTADDR<7:0>
bit 31-0
BD_DSTADDR: Buffer Destination Address
The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption
or authentication. This address must be on a 32-bit boundary.
FIGURE 26-6:
Bit
Range
FORMAT OF BD_NXTADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_NXTADDR<31:24>
23-16
BD_NXTADDR<23:16>
15-8
BD_NXTADDR<15:8>
7-0
BD_NXTADDR<7:0>
bit 31-0
Bit
25/17/9/1
Bit
24/16/8/0
BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor
The next buffer can be a next segment of the previous buffer or a new packet.
DS60001191F-page 396
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 26-7:
Bit
Range
FORMAT OF BD_UPDPTR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_UPDADDR<31:24>
23-16
BD_UPDADDR<23:16>
15-8
BD_UPDADDR<15:8>
7-0
BD_UPDADDR<7:0>
bit 31-0
BD_UPDADDR: UPD Address Location
The update address has the location where the CRDMA results are posted. The updated results are
the ICV values, key output values as needed.
FIGURE 26-8:
Bit
Range
FORMAT OF BD_MSG_LEN
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
MSG_LENGTH<31:24>
23-16
MSG_LENGTH<23:16>
15-8
MSG_LENGTH<15:8>
7-0
MSG_LENGTH<7:0>
bit 31-0
Bit
24/16/8/0
MSG_LENGTH: Total Message Length
Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in
case of GCM algorithm (LEN-C).
FIGURE 26-9:
Bit
Range
Bit
25/17/9/1
FORMAT OF BD_ENC_OFF
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
ENCR_OFFSET<31:24>
23-16
ENCR_OFFSET<23:16>
15-8
ENCR_OFFSET<15:8>
7-0
ENCR_OFFSET<7:0>
bit 31-0
ENCR_OFFSET: Encryption Offset
Encryption offset for the multi-task test cases (both encryption and authentication). The number of
AAD bytes in the case of GCM algorithm (LEN-A).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 397
PIC32MZ Embedded Connectivity (EC) Family
26.3
Security Association Structure
Table 26-4 shows the Security Association Structure.
The Crypto Engine uses the Security Association to
determine the settings for processing a Buffer Descriptor Processor. The Security Association contains:
• Which algorithm to use
• Whether to use engines in parallel (for both
authentication and encryption/decryption)
• The size of the key
• Authentication key
• Encryption/decryption key
• Authentication Initialization Vector (IV)
• Encryption IV
TABLE 26-4:
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE
Name
SA_CTRL
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
—
LNC
—
LOADIV
VERIFY
FB
—
FLAGS
NO_RX
OR_EN
ICVONLY
IRFLAG
—
—
—
ALGO<6>
ENCTYPE
KEYSIZE<1>
31:24
23:16
15:8
7:0
SA_AUTHKEY1 31:24
ALGO<5:0>
KEYSIZE<0>
MULTITASK<2:0>
CRYPTOALGO<3:0>
AUTHKEY<31:24>
23:16
15:8
AUTHKEY<23:16>
AUTHKEY<15:8>
7:0
SA_AUTHKEY2 31:24
AUTHKEY<7:0>
AUTHKEY<31:24>
23:16
15:8
AUTHKEY<23:16>
AUTHKEY<15:8>
7:0
SA_AUTHKEY3 31:24
AUTHKEY<7:0>
AUTHKEY<31:24>
23:16
AUTHKEY<23:16>
15:8
AUTHKEY<15:8>
7:0
SA_AUTHKEY4 31:24
AUTHKEY<7:0>
AUTHKEY<31:24>
23:16
AUTHKEY<23:16>
15:8
AUTHKEY<15:8>
7:0
SA_AUTHKEY5 31:24
AUTHKEY<7:0>
AUTHKEY<31:24>
23:16
15:8
AUTHKEY<23:16>
AUTHKEY<15:8>
7:0
SA_AUTHKEY6 31:24
AUTHKEY<7:0>
AUTHKEY<31:24>
23:16
15:8
AUTHKEY<23:16>
AUTHKEY<15:8>
7:0
SA_AUTHKEY7 31:24
AUTHKEY<7:0>
AUTHKEY<31:24>
23:16
AUTHKEY<23:16>
15:8
7:0
AUTHKEY<15:8>
AUTHKEY<7:0>
SA_AUTHKEY8 31:24
23:16
AUTHKEY<31:24>
AUTHKEY<23:16>
15:8
7:0
AUTHKEY<15:8>
AUTHKEY<7:0>
31:24
23:16
ENCKEY<31:24>
ENCKEY<23:16>
15:8
7:0
ENCKEY<15:8>
ENCKEY<7:0>
31:24
ENCKEY<31:24>
SA_ENCKEY1
SA_ENCKEY2
DS60001191F-page 398
Bit
24/16/8/0
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 26-4:
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Bit
31/23/15/7
Name
SA_ENCKEY3
SA_ENCKEY4
SA_ENCKEY5
SA_ENCKEY6
SA_ENCKEY7
SA_ENCKEY8
SA_AUTHIV1
SA_AUTHIV2
SA_AUTHIV3
SA_AUTHIV4
SA_AUTHIV5
SA_AUTHIV6
SA_AUTHIV7
SA_AUTHIV8
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
23:16
ENCKEY<23:16>
15:8
ENCKEY<15:8>
7:0
31:24
ENCKEY<7:0>
ENCKEY<31:24>
23:16
ENCKEY<23:16>
15:8
ENCKEY<15:8>
7:0
ENCKEY<7:0>
31:24
ENCKEY<31:24>
23:16
ENCKEY<23:16>
15:8
ENCKEY<15:8>
7:0
ENCKEY<7:0>
31:24
ENCKEY<31:24>
23:16
15:8
ENCKEY<23:16>
ENCKEY<15:8>
7:0
ENCKEY<7:0>
31:24
ENCKEY<31:24>
23:16
15:8
ENCKEY<23:16>
ENCKEY<15:8>
7:0
ENCKEY<7:0>
31:24
ENCKEY<31:24>
23:16
15:8
ENCKEY<23:16>
ENCKEY<15:8>
7:0
31:24
ENCKEY<7:0>
ENCKEY<31:24>
23:16
ENCKEY<23:16>
15:8
ENCKEY<15:8>
7:0
31:24
ENCKEY<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
31:24
AUTHIV<7:0>
AUTHIV<31:24>
23:16
15:8
AUTHIV<23:16>
AUTHIV<15:8>
7:0
AUTHIV<7:0>
 2013-2016 Microchip Technology Inc.
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
DS60001191F-page 399
PIC32MZ Embedded Connectivity (EC) Family
TABLE 26-4:
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Bit
31/23/15/7
Name
SA_ENCIV1
SA_ENCIV2
SA_ENCIV3
SA_ENCIV4
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
31:24
ENCIV<31:24>
23:16
ENCIV<23:16>
15:8
7:0
ENCIV<15:8>
ENCIV<7:0>
31:24
ENCIV<31:24>
23:16
ENCIV<23:16>
15:8
ENCIV<15:8>
7:0
ENCIV<7:0>
31:24
ENCIV<31:24>
23:16
ENCIV<23:16>
15:8
ENCIV<15:8>
7:0
ENCIV<7:0>
31:24
23:16
ENCIV<31:24>
ENCIV<23:16>
15:8
ENCIV<15:8>
7:0
ENCIV<7:0>
DS60001191F-page 400
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
Figure 26-10 shows the Security Association control
word structure.
The Crypto Engine fetches different structures for
different flows and ensures that hardware fetches
minimum words from SA required for processing. The
structure is ready for hardware optimal data fetches.
FIGURE 26-10:
Bit
Range
FORMAT OF SA_CTRL
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
—
—
VERIFY
—
NO_RX
OR_EN
ICVONLY
IRFLAG
23-16
LNC
LOADIV
FB
FLAGS
—
—
—
ALGO<6>
ENC
KEY
SIZE<1>
15-8
7-0
ALGO<5:0>
KEY
SIZE<0>
MULTITASK<2:0>
CRYPTOALGO<3:0>
bit 31-30 Reserved: Do not use
bit 29
VERIFY: NIST Procedure Verification Setting
1 = NIST procedures are to be used
0 = Do not use NIST procedures
bit 28
Reserved: Do not use
bit 27
NO_RX: Receive DMA Control Setting
1 = Only calculate ICV for authentication calculations
0 = Normal processing
bit 26
OR_EN: OR Register Bits Enable Setting
1 = OR the register bits with the internal value of the CSR register
0 = Normal processing
bit 25
ICVONLY: Incomplete Check Value Only Flag
This affects the SHA-1 algorithm only. It has no effect on the AES algorithm.
1 = Only three words of the HMAC result are available
0 = All results from the HMAC result are available
bit 24
IRFLAG: Immediate Result of Hash Setting
This bit is set when the immediate result for hashing is requested.
1 = Save the immediate result for hashing
0 = Do not save the immediate result
bit 23
LNC: Load New Keys Setting
1 = Load a new set of keys for encryption and authentication
0 = Do not load new keys
bit 22
LOADIV: Load IV Setting
1 = Load the IV from this Security Association
0 = Use the next IV
bit 21
FB: First Block Setting
This bit indicates that this is the first block of data to feed the IV value.
1 = Indicates this is the first block of data
0 = Indicates this is not the first block of data
bit 20
FLAGS: Incoming/Outgoing Flow Setting
1 = Security Association is associated with an outgoing flow
0 = Security Association is associated with an incoming flow
bit 19-17 Reserved: Do not use
 2013-2016 Microchip Technology Inc.
DS60001191F-page 401
PIC32MZ Embedded Connectivity (EC) Family
Figure 26-10: Format of SA_CTRL (Continued)
bit 16-10 ALGO<6:0>: Type of Algorithm to Use
1xxxxxx = HMAC 1
x1xxxxx = SHA-256
xx1xxxx = SHA1
xxx1xxx = MD5
xxxx1xx = AES
xxxxx1x = TDES
xxxxxx1 = DES
bit 9
ENC: Type of Encryption Setting
1 = Encryption
0 = Decryption
bit 8-7
KEYSIZE<1:0>: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx
11 = Reserved; do not use
10 = 256 bits
01 = 192 bits
00 = 128 bits(1)
bit 6-4
MULTITASK<2:0>: How to Combine Parallel Operations in the Crypto Engine
111 = Parallel pass (decrypt and authenticate incoming data in parallel)
101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data)
011 = Reserved
010 = Reserved
001 = Reserved
000 = Encryption or authentication or decryption (no pass)
bit 3-0
CRYPTOALGO: Mode of operation for the Crypto Algorithm
1111 = Reserved
1110 = AES_GCM
(for AES processing)
1101 = RCTR
(for AES processing)
1100 = RCBC_MAC (for AES processing)
1011 = ROFB
(for AES processing)
1010 = RCFB
(for AES processing)
1001 = RCBC
(for AES processing)
1000 = REBC
(for AES processing)
0111 = TOFB
(for Triple-DES processing)
0110 = TCFB
(for Triple-DES processing)
0101 = TCBC
(for Triple-DES processing)
0100 = TECB
(for Triple-DES processing)
0011 = OFB
(for DES processing)
0010 = CFB
(for DES processing)
0001 = CBC
(for DES processing)
0000 = ECB
(for DES processing)
Note 1:
This setting does not alter the size of SA_AUTHKEYx or SA_ENCKEYx in the Security Association,
only the number of bits of SA_AUTHKEYx and SA_ENCKEYx that are used.
DS60001191F-page 402
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
27.0
Note:
RANDOM NUMBER
GENERATOR (RNG)
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 49. “Crypto
Engine (CE) and Random Number
Generator (RNG)” (DS60001246), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Random Number Generator (RNG) core implements a thermal noise-based, True Random Number
Generator (TRNG) and a cryptographically secure
Pseudo-Random Number Generator (PRNG).
The TRNG uses multiple ring oscillators and the
inherent thermal noise of integrated circuits to
generate true random numbers that can initialize the
PRNG.
The PRNG is a flexible LSFR, which is capable of
manifesting a maximal length LFSR of up to 64-bits.
TABLE 27-1:
RANDOM NUMBER
GENERATOR BLOCK
DIAGRAM
System Bus
PRNG
SFR
PBCLK5
TRNG
BIAS Corrector
Edge Comparator
The following are some of the key features of the
Random Number Generator:
• TRNG:
- Up to 25 Mbps of random bits
- Multi-Ring Oscillator based design
- Built-in Bias Corrector
• PRNG:
- LSFR-based
- Up to 64-bit polynomial length
- Programmable polynomial
- TRNG can be seed value
 2013-2016 Microchip Technology Inc.
Ring
Oscillator
Ring
Oscillator
DS60001191F-page 403
RNG Control Registers
Virtual Address
(BF8E_#)
Register
Name
TABLE 27-2:
6000
RNGVER
6004
6008
600C
RANDOM NUMBER GENERATOR (RNG) REGISTER MAP
RNGCON
RNGPOLY1
RNGPOLY2
6010 RNGNUMGEN1
6014 RNGNUMGEN2
6018
601C
6020
Legend:
RNGSEED1
RNGSEED2
RNGCNT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ID<15:0>
15:0
xxxx
VERSION<7:0>
REVISION<7:0>
31:16
—
—
—
—
—
—
15:0
—
—
—
LOAD
—
CONT
—
—
—
—
—
PRNGEN TRNGEN
31:16
—
—
xxxx
—
—
—
PLEN<7:0>
31:16
FFFF
0000
FFFF
POLY<31:0>
15:0
31:16
0000
FFFF
RNG<31:0>
15:0
31:16
FFFF
FFFF
RNG<31:0>
15:0
31:16
FFFF
0000
SEED<31:0>
15:0
31:16
0000
0000
SEED<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0064
POLY<31:0>
15:0
All Resets
Bit Range
Bits
0000
—
—
—
—
RCNT<6:0>
—
—
—
0000
0000
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 404
27.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 27-1:
Bit
Range
31:24
23:16
15:8
7:0
RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
ID<15:8>
ID<7:0>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VERSION<7:0>
R-0
R-0
REVISION<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 ID<15:0>: Block Identification bits
bit 15-8
VERSION<7:0>: Block Version bits
bit 7-0
REVISION<7:0>: Block Revision bits
 2013-2016 Microchip Technology Inc.
DS60001191F-page 405
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 27-2:
Bit
Range
31:24
23:16
15:8
7:0
RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
LOAD
—
CONT
PRNGEN
TRNGEN
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
PLEN<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12
LOAD: Device Select bit
This bit is self-clearing and is used to load the seed from the TRNG (i.e., the random value) as a seed to
the PRNG.
bit 11
Unimplemented: Read as ‘0’
bit 10
CONT: PRNG Number Shift Enable bit
1 = The PRNG random number is shifted every cycle
0 = The PRNG random number is shifted when the previous value is removed
bit 9
PRNGEN: PRNG Operation Enable bit
1 = PRNG operation is enabled
0 = PRNG operation is not enabled
bit 8
TRNGEN: TRNG Operation Enable bit
1 = TRNG operation is enabled
0 = TRNG operation is not enabled
bit 7-0
PLEN<7:0>: PRNG Polynomial Length bits
These bits contain the length of the polynomial used for the PRNG.
DS60001191F-page 406
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 27-3:
Bit
Range
31:24
23:16
15:8
7:0
RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER ‘x’ 
(‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY<31:24>
R/W-1
POLY<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY<15:8>
R/W-0
POLY<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
POLY<31:0>: PRNG LFSR Polynomial MSb/LSb bits (RNGPOLY1 = LSb, RNGPOLY2 = MSb)
REGISTER 27-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
RNGNUMGENx: RANDOM NUMBER GENERATOR REGISTER ‘x’ (‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG<31:24>
R/W-1
RNG<23:16>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG<15:8>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RNG<31:0>: Current PRNG MSb/LSb Value bits (RNGNUMGEN1 = LSb, RNGNUMGEN2 = MSb)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 407
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 27-5:
Bit
Range
31:24
23:16
15:8
7:0
RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’ 
(‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SEED<31:24>
R-0
R-0
SEED<23:16>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SEED<15:8>
R-0
SEED<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
SEED<31:0>: TRNG MSb/LSb Value bits (RNGSEED1 = LSb, RNGSEED2 = MSb)
REGISTER 27-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
RNGCNT: TRUE RANDOM NUMBER GENERATOR COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
RCNT<6:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-7
Unimplemented: Read as ‘0’
bit 6-0
RCNT<6:0>: Number of Valid TRNG MSB 32 bits
DS60001191F-page 408
x = Bit is unknown
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
28.0
Note:
PIPELINED ANALOG-TODIGITAL CONVERTER (ADC)
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 18. “12-bit
Pipelined Analog-to-Digital Converter
(ADC)” (DS60001194), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The PIC32MZ EC Pipelined Analog-to-Digital
Converter (ADC) includes the following features:
•
•
•
•
•
•
•
•
•
10-bit resolution
Six-stage conversion pipeline
External voltage reference input pins
Six Sample and Hold (S&H) circuits, SH0 - SH5:
- Five dedicated S&H circuits with individual input
selection and individual conversion trigger
selection for high-speed conversions
- One shared S&H circuit with automatic Input Scan
mode and common conversion trigger selection
Up to 48 analog input sources, in addition to the
internal voltage reference and an internal
temperature sensor
32-bit conversion result registers with dedicated
interrupts:
- Conversion result can be formatted as unsigned
or signed fractional or integer data
Six digital comparators with dedicated interrupts:
- Multiple comparison options
- Assignable to specific analog input
Six oversampling filters with dedicated interrupts:
- Provides increased resolution
- Assignable to specific analog input
Operation during Sleep and Idle modes
 2013-2016 Microchip Technology Inc.
Besides the analog inputs that can be converted, there
are two analog input pins for external voltage reference
connections. These voltage reference inputs can be
shared with other analog input pins, and can also be
used by other analog module references.
The analog inputs are connected through multiplexers
(MUXs) to the S&H circuits. Each of the dedicated S&H
circuits, is assigned to analog inputs, and can
optionally use another analog input in a differential configuration. The dedicated S&H circuits are used for
high-speed and precise sampling/conversion of time
sensitive or transient inputs.
The sixth S&H circuit, SH5, can be used in Input Scan
mode and is connected to all the available analog
inputs on a device, along with internal voltage
reference and the temperature sensor signals. Input
Scan mode sequentially converts user-specified
analog input sources. The control registers specify the
analog input sources that are included in the scanning
sequence.
A simplified block diagram of the ADC1 module is
illustrated in Figure 28-1. Diagrams for the Dedicated
and Shared ADC modules are provided in Figure 28-2
and Figure 28-3, respectively.
DS60001191F-page 409
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 28-1:
ADC1 MODULE BLOCK DIAGRAM
VREFSEL<2:0>
AVDD
AVSS
VREF+
VREF-
Reference
Voltage
Selection
VREFH
AN0
AN45
AN5
Sample and Hold 0
(Dedicated)
SH0ALT<1:0>
SH0MOD<1:0>
(see Figure 28-2)
Six-Stage
Conversion
Pipeline
VREFL
Analog Stages
Six Digital
Comparators
Interrupt
FLTRDATA
Six Digital
Filters
Result
Registers
ADC1DATA0
ADC1DATA44
AN1
AN46
AN6
AN2
AN47
AN7
AN3
AN48
AN8
AN4
AN49
AN9
Sample and Hold 1
(Dedicated)
SH1ALT<1:0>
SH1MOD<1:0>
(see Figure 28-2)
Sample and Hold 2
(Dedicated)
SH2ALT<1:0>
SH2MOD<1:0>
(see Figure 28-2)
Digital Stages
PBCLK3
TAD
Divider
1, 2, 4, 6, ...254
ADCDIV<6:0>
TQ
Sample and Hold 3
(Dedicated)
SH3ALT<1:0>
SH3MOD<1:0>
(see Figure 28-2)
ADCSEL<1:0>
Clock Selection
FRC
SYSCLK REFCLKO3
Sample and Hold 4
(Dedicated)
SH4ALT<1:0>
SH4MOD<1:0>
(see Figure 28-2)
AN5
AN42
IVREF (AN43)
IVTEMP (AN44)
Sample and Hold 5
(Shared)
SH5MOD<1:0>
(see Figure 28-3)
AN10
DS60001191F-page 410
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
FIGURE 28-2:
DEDICATED S&H 0-4 BLOCK DIAGRAM
Positive Input
(Class 1)
00
Alternate
Positive Input
01
S&H
To Analog Stages
Single-Ended
VREFL
0x
To Analog Stages
Negative Input
1x
Differential
SHxMOD<1:0>
SHxALT<1:0>
Channel
Configuration
To Digital Stages
SHxALT<1:0>
SHxMOD<1:0>
FIGURE 28-3:
SHARED S&H 5 BLOCK DIAGRAM
AN5
Positive Input
(Class 2)
AN11
Positive Input
(Class 3)
AN12
AN42
IVREF (AN43)
IVTEMP (AN44)
S&H
Channel Scan Logic
To Analog
Stages
Single-Ended
VREFL
0x
To Analog
Stages
AN10
(Negative Input)
1x
Differential
SHxMOD<1:0>
Channel
Configuration
To Digital
Stages
SH5ALT<1:0>
SH5MOD<1:0>
 2013-2016 Microchip Technology Inc.
DS60001191F-page 411
PIC32MZ Embedded Connectivity (EC) Family
28.1
Note:
ADC Configuration Requirements
A related code example is available in
the latest release of MPLAB Harmony
(visit http://www.micochip.com/harmony
for more information).
To meet ADC specifications, the following steps
must be performed:
1.
2.
Set the ADC Configuration words, as follows:
AD1CAL1 = 0xB3341210;
AD1CAL2 = 0x01FFA769;
AD1CAL3 = 0x0BBBBBB8;
AD1CAL4 = 0x000004AC;
AD1CAL5 = 0x02028002;
Perform self-calibration. The input mode for
SH0-SH5 must be set to the unipolar differential input mode by setting the SHxMOD<1:0>
bits (AD1MOD<1:0>) = 10.
Note:
Unsupported ADC operating modes:
•
•
•
•
•
•
•
•
•
Software polling of ADC status bits
Manual software ADC triggering
ADC interrupt modes (use DMA Interrupt mode)
ADC SFR accesses by the CPU while ADC is
operating
ADC Boost or low-power mode.
Individual ADC Input Conversion Requests (i.e.,
RQCNVRT bit in the ADCCON3 register)
Use of ADC S&H Channels 0-4 except for
calibration
Any ADC references other than external VREF+
and VREF- pins
ADC Differential mode
SH0 through SH4 functionality
and ADC Differential mode are
not supported; however, both
are required for auto-calibration.
Sampling must be performed on
SH5 only.
In addition, the following restrictions apply:
Supported ADC operating modes:
• Scan mode only with DMA interrupt
• The maximum number of used ANx inputs are
limited by the available DMA channels
(maximum of eight)
• The first (8) conversion after enabling the ADC
must be discarded
• ADC Single-ended mode only
• The ADC Clock, TAD, must be limited to 500 kHz
< TAD < 1 MHz (i.e., 2 µs < TAD < 1 µs).
• HDW Oversampling is supported, but is not
required, and will not impair accuracy; however,
it will reduce the ADC ANx input throughput by
the oversample ratio in use
• ANx VIN maximum is limited to < 2.5V
• VREF+ < VDD = AVDD  2.5V
• Use of external VREF+ and VREF- pins only for
ADC reference (VREFSEL<2:0> bits are equal
to 'b011):
- VREF- = Can be connected to AVSS externally,
but not internally
- VREF+ can be connected to AVDD externally if
required, but not internally
DS60001191F-page 412
 2013-2016 Microchip Technology Inc.
ADC Control Registers
B000 AD1CON1
B004 AD1CON2
B008 AD1CON3
B00C AD1IMOD
B010 AD1GIRQEN1
B014 AD1GIRQEN2
B018 AD1CSS1
B01C AD1CSS2
B020 AD1DSTAT1
B024 AD1DSTAT2
B028 AD1CMPEN1
B02C AD1CMP1
B030 AD1CMPEN2
B034 AD1CMP2
B038 AD1CMPEN3
DS60001191F-page 413
B03C AD1CMP3
B040 AD1CMPEN4
B044 AD1CMP4
Legend:
ADC REGISTER MAP
31/15
30/14
28/12
27/11
26/10
25/9
ADCEN
—
ADSIDL
—
FRACT
—
—
—
—
—
—
—
—
—
—
31:16
15:0
29/13
FILTRDLY4:0>
31:16 ADCRDY
24/8
23/7
22/6
—
—
STRGSRC<4:0>
21/5
20/4
19/3
—
—
—
—
—
—
18/2
17/1
16/0
EIE<2:0>
—
—
0000
—
SAMC<7:0>
—
0000
0000
15:0
—
BOOST
LOWPWR
—
—
—
31:16
CAL
GSWTRG
RQCNVRT
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
SH4ALT<1:0>
SH3ALT<1:0>
SH2ALT<1:0>
SH1ALT<1:0>
SH0ALT<1:0>
0000
15:0
—
—
—
—
SH5MOD<1:0>
SH4MOD<1:0>
SH3MOD<1:0>
SH2MOD<1:0>
SH1MOD<1:0>
SH0MOD<1:0>
0000
31:16 AGIEN31
AGIEN30
AGIEN29
AGIEN28 AGIEN27
AGIEN26
AGIEN25
AGIEN24
AGIEN23
AGIEN22
AGIEN21 AGIEN20 AGIEN19 AGIEN18 AGIEN17 AGIEN16 0000
VREFSEL<2:0>
ADCSEL<1:0>
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF84_#)
TABLE 28-1:
ADCDIV<6:0>
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
ADINSEL<5:0>
0000
0000
15:0
AGIEN15
AGIEN14
AGIEN13
AGIEN12
AGIEN11
AGIEN10
AGIEN9
AGIEN8
AGIEN7
AGIEN6
AGIEN5
AGIEN4
AGIEN3
AGIEN2
AGIEN1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
AGIEN42
AGIEN41
AGIEN40
AGIEN39
AGIEN38
31:16
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
0000
15:0
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
CSS44
CSS43
CSS42
CSS41
CSS40
CSS39
CSS38
CSS37
CSS36
CSS35
CSS34
CSS33
CSS32
0000
31:16 ARDY31
ARDY30
ARDY29
ARDY28
ARDY27
ARDY26
ARDY25
ARDY24
ARDY23
ARDY22
ARDY21 ARDY20 ARDY19 ARDY18 ARDY17 ARDY16 0000
AGIEN44 AGIEN43
AGIEN0 0000
—
0000
AGIEN37 AGIEN36 AGIEN35 AGIEN34 AGIEN33 AGIEN32 0000
15:0
ARDY15
ARDY14
ARDY13
ARDY12
ARDY11
ARDY10
ARDY9
ARDY9
ARDY7
ARDY6
ARDY5
ARDY4
ARDY3
ARDY2
ARDY1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
ARDY44
ARDY43
ARDY42
ARDY41
ARDY40
ARDY39
ARDY38
ARDY37 ARDY36 ARDY35 ARDY34 ARDY33 ARDY32 0000
31:16 CMPE31
CMPE30
CMPE29
CMPE28
CMPE27
CMPE26
CMPE25
CMPE24
CMPE23
CMPE22
CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
15:0
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
CMPE7
CMPE6
CMPE5
CMPE15
31:16
ACMPHI<15:0>
15:0
ADCMPLO<15:0>
31:16 CMPE31
CMPE30
CMPE29
CMPE28
CMPE27
CMPE26
CMPE25
15:0
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE15
CMPE27
CMPE26
CMPE25
15:0
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE15
CMPE8
CMPE7
CMPE6
CMPE5
CMPE27
CMPE26
CMPE25
15:0
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE15
CMPE2
CMPE1
CMPE0 0000
0000
0000
CMPE22
CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
CMPE8
CMPE7
CMPE6
CMPE5
ADCMPLO<15:0>
CMPE28
CMPE3
CMPE23
15:0
CMPE29
CMPE4
CMPE24
ADCMPHI<15:0>
CMPE30
0000
CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
31:16
31:16 CMPE31
CMPE0 0000
CMPE22
ADCMPLO<15:0>
CMPE28
CMPE1
CMPE23
15:0
CMPE29
CMPE2
0000
CMPE24
ADCMPHI<15:0>
CMPE30
CMPE3
—
0000
31:16
31:16 CMPE31
CMPE4
ARDY0 0000
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0 0000
0000
0000
CMPE24
CMPE23
CMPE22
CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
CMPE8
CMPE7
CMPE6
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0 0000
31:16
ADCMPHI<15:0>
0000
15:0
ADCMPLO<15:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
28.2
B04C AD1CMP5
B050 AD1CMPEN6
B054 AD1CMP6
B058 AD1FLTR1
B05C AD1FLTR2
B060 AD1FLTR3
B064 AD1FLTR4
B068 AD1FLTR5
B06C AD1FLTR6
B070 AD1TRG1
B074 AD1TRG2
B078 AD1TRG3
 2013-2016 Microchip Technology Inc.
B090 AD1CMPCON1
B094 AD1CMPCON2
B098 AD1CMPCON3
B09C AD1CMPCON4
B0A0 AD1CMPCON5
B0A4 AD1CMPCON6
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16 CMPE31
CMPE30
CMPE29
CMPE28
CMPE27
CMPE26
CMPE25
CMPE24
CMPE23
CMPE22
CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
15:0
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
CMPE7
CMPE6
CMPE5
CMPE15
31:16
ADCMPHI<15:0>
15:0
ADCMPLO<15:0>
31:16 CMPE31
CMPE30
CMPE29
CMPE28
CMPE27
CMPE26
CMPE25
15:0
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE15
AFGIEN
OVRSAM<2:0>
15:0
31:16
AFEN
—
—
AFEN
—
—
0000
0000
CMPE7
CMPE6
CMPE5
AFRDY
AFGIEN
OVRSAM<2:0>
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0 0000
0000
0000
—
—
CHNLID<5:0>
—
—
CHNLID<5:0>
—
—
CHNLID<5:0>
—
—
CHNLID<5:0>
—
—
CHNLID<5:0>
—
—
CHNLID<5:0>
0000
0000
0000
AFRDY
0000
0000
FLTRDATA<15:0>
AFEN
—
—
AFGIEN
OVRSAM<2:0>
AFRDY
0000
0000
FLTRDATA<15:0>
AFEN
—
—
AFGIEN
OVRSAM<2:0>
15:0
31:16
CMPE0 0000
FLTRDATA<15:0>
15:0
31:16
CMPE1
CMPE8
AFRDY
AFGIEN
OVRSAM<2:0>
15:0
31:16
CMPE2
16/0
FLTRDATA<15:0>
15:0
31:16
CMPE3
17/1
CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
ADCMPLO<15:0>
—
18/2
CMPE22
15:0
—
CMPE4
19/3
CMPE23
ADCMPHI<15:0>
AFEN
20/4
CMPE24
31:16
31:16
21/5
All Resets
Bit Range
Register
Name
Virtual Address
(BF84_#)
Bits
B048 AD1CMPEN5
Legend:
ADC REGISTER MAP (CONTINUED)
AFRDY
0000
0000
FLTRDATA<15:0>
AFEN
—
—
AFGIEN
OVRSAM<2:0>
15:0
AFRDY
0000
0000
FLTRDATA<15:0>
0000
31:16
—
—
—
TRGSRC3<4:0>
—
—
—
TRGSRC2<4:0>
0000
15:0
—
—
—
TRGSRC1<4:0>
—
—
—
TRGSRC0<4:0>
0000
31:16
—
—
—
TRGSRC7<4:0>
—
—
—
TRGSRC6<4:0>
0000
15:0
—
—
—
TRGSRC5<4:0>
—
—
—
TRGSRC4<4:0>
0000
31:16
—
—
—
TRGSRC11<4:0>
—
—
—
TRGSRC10<4:0>
0000
15:0
—
—
—
TRGSRC9<4:0>
—
—
—
TRGSRC8<4:0>
31:16
—
—
—
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
AINID<4:0>
—
—
—
ENDCMP DCMPGIEN DCMPED IEBTWN
—
—
AINID<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ENDCMP DCMPGIEN DCMPED IEBTWN
—
—
AINID<4:0>
—
—
ENDCMP DCMPGIEN DCMPED IEBTWN
AINID<4:0>
—
—
ENDCMP DCMPGIEN DCMPED IEBTWN
AINID<4:0>
—
—
—
—
—
—
ENDCMP DCMPGIEN DCMPED IEBTWN
—
AINID<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
ENDCMP DCMPGIEN DCMPED IEBTWN
0000
—
—
—
IEHIHI
IEHILO
IELOHI
—
—
—
IEHIHI
IEHILO
IELOHI
—
—
—
IEHIHI
IEHILO
IELOHI
—
—
—
IEHIHI
IEHILO
IELOHI
—
—
—
IEHIHI
IEHILO
IELOHI
—
—
—
IEHIHI
IEHILO
IELOHI
—
0000
IELOLO 0000
—
0000
IELOLO 0000
—
0000
IELOLO 0000
—
0000
IELOLO 0000
—
0000
IELOLO 0000
—
0000
IELOLO 0000
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 414
TABLE 28-1:
B0BC AD1DATA1
B0C0 AD1DATA2
B0C4 AD1DATA3
B0C8 AD1DATA4
B0CC AD1DATA5
B0D0 AD1DATA6
B0D4 AD1DATA7
B0D8 AD1DATA8
B0DC AD1DATA9
B0E0 AD1DATA10
B0E4 AD1DATA11
B0E8 AD1DATA12
B0EC AD1DATA13
B0F0 AD1DATA14
B0F4 AD1DATA15
DS60001191F-page 415
B0F8 AD1DATA16
B0FC AD1DATA17
B100 AD1DATA18
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name
Virtual Address
(BF84_#)
Bits
B0B8 AD1DATA0
Legend:
ADC REGISTER MAP (CONTINUED)
31:16
ADC Output Register 0 <31:16>
0000
15:0
ADC Output Register 0 <15:0>
0000
31:16
ADC Output Register 1 <31:16>
0000
15:0
ADC Output Register 1 <15:0>
0000
31:16
ADC Output Register 2 <31:16>
0000
15:0
ADC Output Register 2 <15:0>
0000
31:16
ADC Output Register 3 <31:16>
0000
15:0
ADC Output Register 3 <15:0>
0000
31:16
ADC Output Register 4 <31:16>
0000
15:0
ADC Output Register 4 <15:0>
0000
31:16
ADC Output Register 5 <31:16>
0000
15:0
ADC Output Register <15:0>
0000
31:16
ADC Output Register 6 <31:16>
0000
15:0
ADC Output Register 6 <15:0>
0000
31:16
ADC Output Register 7 <31:16>
0000
15:0
ADC Output Register 7 <15:0>
0000
31:16
ADC Output Register 8 <31:16>
0000
15:0
ADC Output Register 8 <15:0>
0000
31:16
ADC Output Register 9 <31:16>
0000
15:0
ADC Output Register 9 <15:0>
0000
31:16
ADC Output Register 10 <31:16>
0000
15:0
ADC Output Register 10 <15:0>
0000
31:16
ADC Output Register 11 <31:16>
0000
15:0
ADC Output Register 11 <15:0>
0000
31:16
ADC Output Register 12 <31:16>
0000
15:0
ADC Output Register 12 <15:0>
0000
31:16
ADC Output Register 13 <31:16>
0000
15:0
ADC Output Register 13 <15:0>
0000
31:16
ADC Output Register 14 <31:16>
0000
15:0
ADC Output Register 14 <15:0>
0000
31:16
ADC Output Register 15 <31:16>
0000
15:0
ADC Output Register 15 <15:0>
0000
31:16
ADC Output Register 16 <31:16>
0000
15:0
ADC Output Register 16 <15:0>
0000
31:16
ADC Output Register 17 <31:16>
0000
15:0
ADC Output Register 17<15:0>
0000
31:16
ADC Output Register 18 <31:16>
0000
15:0
ADC Output Register18 <15:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 28-1:
B108 AD1DATA20
B10C AD1DATA21
B110 AD1DATA22
B114 AD1DATA23
B118 AD1DATA24
B11C AD1DATA25
B120 AD1DATA26
B124 AD1DATA27
B128 AD1DATA28
B12C AD1DATA29
B130 AD1DATA30
B134 AD1DATA31
 2013-2016 Microchip Technology Inc.
B138 AD1DATA32
B13C AD1DATA33
B140 AD1DATA34
B144 AD1DATA35
B148 AD1DATA36
B14C AD1DATA37
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name
Virtual Address
(BF84_#)
Bits
B104 AD1DATA19
Legend:
ADC REGISTER MAP (CONTINUED)
31:16
ADC Output Register 19 <31:16>
0000
15:0
ADC Output Register 19<15:0>
0000
31:16
ADC Output Register 20 <31:16>
0000
15:0
ADC Output Register 20<15:0>
0000
31:16
ADC Output Register 21 <31:16>
0000
15:0
ADC Output Register 21 <15:0>
0000
31:16
ADC Output Register 22 <31:16>
0000
15:0
ADC Output Register 22<15:0>
0000
31:16
ADC Output Register 23 <31:16>
0000
15:0
ADC Output Register 23<15:0>
0000
31:16
ADC Output Register 24 <31:16>
0000
15:0
ADC Output Register 24<15:0>
0000
31:16
ADC Output Register 25 <31:16>
0000
15:0
ADC Output Register 25 <15:0>
0000
31:16
ADC Output Register 26 <31:16>
0000
15:0
ADC Output Register 26<15:0>
0000
31:16
ADC Output Register 27 <31:16>
0000
15:0
ADC Output Register 27<15:0>
0000
31:16
ADC Output Register 28 <31:16>
0000
15:0
ADC Output Register 28<15:0>
0000
31:16
ADC Output Register 29 <31:16>
0000
15:0
ADC Output Register 29 <15:0>
0000
31:16
ADC Output Register 30 <31:16>
0000
15:0
ADC Output Register 30<15:0>
0000
31:16
ADC Output Register 31 <31:16>
0000
15:0
ADC Output Register 31 <15:0>
0000
31:16
ADC Output Register 32 <31:16>
0000
15:0
ADC Output Register 32 <15:0>
0000
31:16
ADC Output Register 33 <31:16>
0000
15:0
ADC Output Register 33 <15:0>
0000
31:16
ADC Output Register 34 <31:16>
0000
15:0
ADC Output Register 34 <15:0>
0000
31:16
ADC Output Register 35 <31:16>
0000
15:0
ADC Output Register 35 <15:0>
0000
31:16
ADC Output Register 36 <31:16>
0000
15:0
ADC Output Register 36 <15:0>
0000
31:16
ADC Output Register 37 <31:16>
0000
15:0
ADC Output Register 37 <15:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 416
TABLE 28-1:
B154 AD1DATA39
B158 AD1DATA40
B15C AD1DATA41
B160 AD1DATA42
B164 AD1DATA43
B168 AD1DATA44
B200 AD1CAL1
B204 AD1CAL2
B208 AD1CAL3
B20C AD1CAL4
B210 AD1CAL5
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name
Virtual Address
(BF84_#)
Bits
B150 AD1DATA38
Legend:
ADC REGISTER MAP (CONTINUED)
31:16
ADC Output Register 38 <31:16>
0000
15:0
ADC Output Register 38 <15:0>
0000
31:16
ADC Output Register 38 <31:16>
0000
15:0
ADC Output Register 38 <15:0>
0000
31:16
ADC Output Register 40 <31:16>
0000
15:0
ADC Output Register 40 <15:0>
0000
31:16
ADC Output Register 41 <31:16>
0000
15:0
ADC Output Register 41 <15:0>
0000
31:16
ADC Output Register 42 <31:16>
0000
15:0
ADC Output Register 42 <15:0>
0000
31:16
ADC Output Register 43 <31:16>
0000
15:0
ADC Output Register 43 <15:0>
0000
31:16
ADC Output Register 44 <31:16>
0000
15:0
ADC Output Register 44 <15:0>
0000
31:16
ADC Calibration Data
0000
15:0
ADC Calibration Data
0000
31:16
ADC Calibration Data
0000
15:0
ADC Calibration Data
0000
31:16
ADC Calibration Data
0000
15:0
ADC Calibration Data
0000
31:16
ADC Calibration Data
0000
15:0
ADC Calibration Data
0000
31:16
ADC Calibration Data
0000
15:0
ADC Calibration Data
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS60001191F-page 417
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 28-1:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-1:
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
FILTRDLY<4:0>
R/W-0
23:16
15:8
R/W-0
STRGSRC<1:0>
STRGSRC<4:2>
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
EIE<2:0>(1)
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
ADCEN(2,4)
—
ADSIDL
—
FRACT
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
7:0
Legend:
R = Readable bit
-n = Value at POR
bit 31-27
AD1CON1: ADC1 CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
FILTRDLY<4:0>: Oversampling Digital Filter Delay bits
Specifies the sampling time for subsequent automatic triggers when using the Oversampling Digital Filter.
Sample time is 1.5 + FILTRDLY<4:0> TAD.
11111 = Sample time is 32.5 TAD
11110 = Sample time is 31.5 TAD
•
•
•
00001 = Sample time is 2.5 TAD
00000 = Sample time is 1.5 TAD
bit 26-22
STRGSRC<4:0>: Scan Trigger Source Select bits
11111 = Reserved
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT(3)
01011 = Comparator 1 COUT(3)
01010 = OCMP5(3)
01001 = OCMP3(3)
01000 = OCMP1(3)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = Reserved
00010 = Reserved
00001 = Global software trigger (GSWTRG)
00000 = No trigger
Note 1:
2:
3:
4:
Note:
The early interrupt feature should not be used if polling any of the ARDY bits to determine if the
conversion is complete. Early interrupts should be used only when all results from the ADC module are
retrieved using an individual interrupt routine to fetch ADC results.
The ADCEN bit should be set only after the ADC module has been configured. Changing ADC Configuration bits when ADCEN = 1, will result in unpredictable behavior. When ADCEN = 0, the ADC clocks are
disabled, the internal control logic is reset, and all status flags used by the module are cleared. However,
the SFRs are available for reading and writing.
The rising edge of the module output signal triggers an ADC conversion. See Figure 18-1 in Section 18.0
“Output Compare” and Figure 31-1 in Section 31.0 “Comparator” for more information.
See 28.1 “ADC Configuration Requirements” for detailed ADC calibration information.
The ADC module is not available for normal operations until the ADCRDY bit (AD1CON2<31>) is set.
DS60001191F-page 418
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-1:
bit 21-19
bit 18-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-0
Note 1:
2:
3:
4:
Note:
AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
Unimplemented: Read as ‘0’
EIE<2:0>: Early Interrupt Enable bits(1)
These bits select the number of clocks prior to the actual arrival of valid data when the associated
ARDYx bit is set. Since the ARDYx bit triggers an interrupt, these bits allow for early interrupt generation.
111 = The data ready bit, ARDYx, is set 7 TAD clocks prior to when the data is ready
110 = The data ready bit, ARDYx, is set 6 TAD clocks prior to when the data is ready
101 = The data ready bit, ARDYx, is set 5 TAD clocks prior to when the data is ready
100 = The data ready bit, ARDYx, is set 4 TAD clocks prior to when the data is ready
011 = The data ready bit, ARDYx, is set 3 TAD clocks prior to when the data is ready
010 = The data ready bit, ARDYx, is set 2 TAD clocks prior to when the data is ready
001 = The data ready bit, ARDYx, is set 1 TAD clock prior to when the data is ready
000 = The data ready bit, ARDYx, when the data is ready
ADCEN: ADC Operating Mode bit(2,4)
1 = ADC module is enabled
0 = ADC module is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
FRACT: Fractional Data Output Format bit
1 = Fractional
0 = Integer
Unimplemented: Read as ‘0’
The early interrupt feature should not be used if polling any of the ARDY bits to determine if the
conversion is complete. Early interrupts should be used only when all results from the ADC module are
retrieved using an individual interrupt routine to fetch ADC results.
The ADCEN bit should be set only after the ADC module has been configured. Changing ADC Configuration bits when ADCEN = 1, will result in unpredictable behavior. When ADCEN = 0, the ADC clocks are
disabled, the internal control logic is reset, and all status flags used by the module are cleared. However,
the SFRs are available for reading and writing.
The rising edge of the module output signal triggers an ADC conversion. See Figure 18-1 in Section 18.0
“Output Compare” and Figure 31-1 in Section 31.0 “Comparator” for more information.
See 28.1 “ADC Configuration Requirements” for detailed ADC calibration information.
The ADC module is not available for normal operations until the ADCRDY bit (AD1CON2<31>) is set.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 419
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-2:
AD1CON2: ADC1 CONTROL REGISTER 2
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R-0, HS, HC
U-0
U-0
U-0
U-0
U-0
U-0
U-0
ADCRDY(1)
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
23:16
SAMC<7:0>
15:8
7:0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
—
BOOST
LOWPWR
—
—
—
ADCSEL<1:0>(2)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(2)
—
ADCDIV<6:0>
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
ADCRDY: ADC Ready bit(1)
1 = ADC module is ready for normal operation
0 = ADC is not ready for use
bit 30-24
Unimplemented: Read as ‘0’
bit 23-16
SAMC<7:0>: Sample Time for Shared S&H bits
11111111 = 256 TAD
x = Bit is unknown
•
•
•
00000001 = 2 TAD
00000000 = 1 TAD
This field specifies the number of ADC clock cycles allocated to the ADC sample time for the shared
S&H circuit.
bit 15
Unimplemented: Read as ‘0’
bit 14
BOOST: Voltage Reference Boost bit
1 = Boost VREF
0 = Do not boost VREF
Changing the state of this bit requires that the ADC module be recalibrated by setting the
CAL bit (AD1CON3<31>).
bit 13
LOWPWR: ADC Low-power bit
1 = Force the ADC module into a low-power state
0 = Exit ADC low-power state
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
ADCSEL<1:0>: ADC Clock Source (TQ) bits(2)
11 = FRC
10 = REFCLKO3
01 = SYSCLK
00 = Reserved
bit 7
Unimplemented: Read as ‘0’
Note 1:
2:
This bit is set to ‘0’ when ADCEN (AD1CON1<15>) = 0.
These bits should be configured prior to enabling the ADC by setting the ADCEN bit (AD1CON1<15>) = 1.
DS60001191F-page 420
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-2:
bit 6-0
AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED)
ADCDIV<6:0>: ADC Input Clock Divider bits(2)
These bits divide the selected clock source to derive the desired ADC clock rate (TAD).
1111111 = 2 TQ * (ADCDIV<6:0>) = 254 * TQ = TAD
•
•
•
0000011 = 2 TQ * (ADCDIV<6:0>) = 6 * TQ = TAD
0000010 = 2 TQ * (ADCDIV<6:0>) = 4 * TQ = TAD
0000001 = 2 TQ * (ADCDIV<6:0>) = 2 * TQ = TAD
0000000 = TQ = TAD
Note 1:
2:
This bit is set to ‘0’ when ADCEN (AD1CON1<15>) = 0.
These bits should be configured prior to enabling the ADC by setting the ADCEN bit (AD1CON1<15>) = 1.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 421
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-3:
Bit
Range
31:24
23:16
15:8
7:0
AD1CON3: ADC1 CONTROL REGISTER 3
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, HC
R/W-0, HC
R/W-0, HC
U-0
U-0
U-0
U-0
U-0
GSWTRG
RQCNVRT
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
CAL
(2)
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
Legend:
R = Readable bit
-n = Value at POR
VREFSEL<2:0>(1)
R/W-0
R/W-0
ADINSEL<5:0>
W = Writable bit
‘1’ = Bit is set
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CAL: Calibration bit(2)
1 = Initiate an ADC calibration cycle
0 = Calibration cycle is not in progress
bit 30
GSWTRG: Global Software Trigger bit
1 = Trigger analog-to-digital conversion for ADC inputs that have selected the GSWTRG bit as the trigger
signal, either through the associated TRGSRC<4:0> bits in the AD1TRGn registers or through the
STRGSRC<4:0> bits in the AD1CON1 register
0 = This bit is automatically cleared
bit 29
RQCNVRT: Individual ADC Input Conversion Request bit
This bit and its associated ADINSEL<5:0> bits enable the user to individually request an analog-to-digital
conversion of an analog input without having to reprogram the TRGSRC<4:0> bits or the STRGSRC<4:0>
bits. This is very useful during debugging or error handling situations where the user software needs to
obtain an immediate ADC result of a specific input.
1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL<5:0> bits
0 = This bit is automatically cleared
bit 28-13 Unimplemented: Read as ‘0’
bit 12-10 VREFSEL<2:0>: VREF Input Selection bits(1)
bit 31
VREFSEL<2:0>
VREFH
VREFL
111
110
101
100
011
010
001
000
Reserved
Reserved
Reserved
Reserved
VREF+
AVDD
VREF+
AVDD
Reserved
Reserved
Reserved
Reserved
VREFVREFAVss
AVss
bit 9-6
Unimplemented: Read as ‘0’
Note 1:
These bits should be configured prior to enabling the ADC module by setting the ADCEN bit
(AD1CON1<15> = 1).
See 28.1 “ADC Configuration Requirements” for detailed ADC calibration information.
2:
DS60001191F-page 422
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-3:
AD1CON3: ADC1 CONTROL REGISTER 3 (CONTINUED)
bit 5-0
ADINSEL<5:0>: ADC Input Select bits
This binary encoded bit-field selects the ADC module input to be converted when the RQCNVRT bit is set.
111111 = Reserved
•
•
•
101101 = Reserved
101100 = IVTEMP
101011 = IVREF
101010 = AN42
•
•
•
000010 = AN2
000001 = AN1
000000 = AN0
Note 1:
These bits should be configured prior to enabling the ADC module by setting the ADCEN bit
(AD1CON1<15> = 1).
See 28.1 “ADC Configuration Requirements” for detailed ADC calibration information.
2:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 423
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-4:
Bit Range
31:24
23:16
15:8
7:0
AD1IMOD: ADC1 INPUT MODE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SH3ALT<1:0>(1,2)
U-0
SH2ALT<1:0>(1,2)
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
SH3MOD<1:0>
SH1ALT<1:0>(1,2)
R/W-0
R/W-0
SH5MOD<1:0>
R/W-0
SH2MOD<1:0>
R/W-0
SH1MOD<1:0>
SH4ALT<1:0>(1,2)
R/W-0
R/W-0
SH0ALT<1:0>(1,2)
R/W-0
R/W-0
SH4MOD<1:0>
R/W-0
R/W-0
SH0MOD<1:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26
Unimplemented: Read as ‘0’
bit 25-24
SH4ALT<1:0>: Analog Input to Dedicated S&H 4 (SH4) Select bits(1,2)
11 = Reserved
10 = Reserved
01 = Alternate input AN49
00 = Default Class 1 input AN4
bit 23-22
SH3ALT<1:0>: Analog Input to Dedicated S&H 3 (SH3) Select bits(1,2)
11 = Reserved
10 = Reserved
01 = Alternate input AN48
00 = Default Class 1 input AN3
bit 21-20
SH2ALT<1:0>: Analog Input to Dedicated S&H 2 (SH2) Select bits(1,2)
11 = Reserved
10 = Reserved
01 = Alternate input AN47
00 = Default Class 1 input AN2
bit 19-18
SH1ALT<1:0>: Analog Input to Dedicated S&H 1 (SH1) Select bits(1,2)
11 = Reserved
10 = Reserved
01 = Alternate input AN46
00 = Default Class 1 input AN1
bit 17-16
SH0ALT<1:0>: Analog Input to Dedicated S&H 0 (SH0) Select bits(1,2)
11 = Reserved
10 = Reserved
01 = Alternate input AN45
00 = Default Class 1 input AN0
bit 15-12
Unimplemented: Read as ‘0’
Note 1:
2:
Alternate inputs are only available for Class 1 Inputs.
When an alternate input is selected (SHxALT<1:0>  0), the data, status, and control registers for the
default Class 1 input are still used. Selecting an alternate input changes the physical input source only.
DS60001191F-page 424
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-4:
AD1IMOD: ADC1 INPUT MODE CONTROL REGISTER (CONTINUED)
bit 11-10
SH5MOD<1:0>: Input Configuration for S&H 5 (SH5) Select bits
11 = Differential inputs, two’s complement (signed) data output
10 = Differential inputs, unipolar encoded (unsigned) data output
01 = Single ended inputs, two’s complement (signed) data output
00 = Single ended inputs, unipolar encoded (unsigned) data output
bit 9-8
SH4MOD<1:0>: Input Configuration for S&H 4 (SH4) Select bits
11 = Differential inputs, two’s complement (signed) data output
10 = Differential inputs, unipolar encoded (unsigned) data output
01 = Single ended inputs, two’s complement (signed) data output
00 = Single ended inputs, unipolar encoded (unsigned) data output
bit 7-6
SH3MOD<1:0>: Input Configuration for S&H 3 (SH3) Select bits
11 = Differential inputs, two’s complement (signed) data output
10 = Differential inputs, unipolar encoded (unsigned) data output
01 = Single ended inputs, two’s complement (signed) data output
00 = Single ended inputs, unipolar encoded (unsigned) data output
bit 5-4
SH2MOD<1:0>: Input Configuration for S&H 2 (SH2) Select bits
11 = Differential inputs, two’s complement (signed) data output
10 = Differential inputs, unipolar encoded (unsigned) data output
01 = Single ended inputs, two’s complement (signed) data output
00 = Single ended inputs, unipolar encoded (unsigned) data output
bit 3-2
SH1MOD<1:0>: Input Configuration for S&H 1 (SH1) Select bits
11 = Differential inputs, two’s complement (signed) data output
10 = Differential inputs, unipolar encoded (unsigned) data output
01 = Single ended inputs, two’s complement (signed) data output
00 = Single ended inputs, unipolar encoded (unsigned) data output
bit 1-0
SH0MOD<1:0>: Input Configuration for S&H 0 (SH0) Select bits
11 = Differential inputs, two’s complement (signed) data output
10 = Differential inputs, unipolar encoded (unsigned) data output
01 = Single ended inputs, two’s complement (signed) data output
00 = Single ended inputs, unipolar encoded (unsigned) data output
Note 1:
2:
Alternate inputs are only available for Class 1 Inputs.
When an alternate input is selected (SHxALT<1:0>  0), the data, status, and control registers for the
default Class 1 input are still used. Selecting an alternate input changes the physical input source only.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 425
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-5:
Bit Range
31:24
23:16
15:8
7:0
AD1GIRQEN1: ADC1 GLOBAL INTERRUPT ENABLE REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN31
AGIEN30
AGIEN29
AGIEN28
AGIEN27
AGIEN26
AGIEN25
AGIEN24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN23
AGIEN22
AGIEN21
AGIEN20
AGIEN19
AGIEN18
AGIEN17
AGIEN16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN15
AGIEN14
AGIEN13
AGIEN12
AGIEN11
AGIEN10
AGIEN9
AGIEN8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN7
AGIEN6
AGIEN5
AGIEN4
AGIEN3
AGIEN2
AGIEN1
AGIEN0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
AGIENx: Global ADC Interrupt Enable bits (‘x’ = 0-31)
1 = A data ready event (transition from 0 to 1 of the ARDYx bit) will generate a Global ADC interrupt
0 = No global interrupt is generated on a data ready event
The Global ADC Interrupt is enabled by setting a bit in the IECx registers (refer to Section 7.0 “CPU
Exceptions and Interrupt Controller” for details).
Note 1:
2:
The enable bits do not affect assertion of the individual interrupt output. Interrupts generated for individual
ARDY events are enabled in the IECx register.
AGIENx = ANx, where ‘x’ = 0-31.
DS60001191F-page 426
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-6:
Bit Range
31:24
23:16
15:8
7:0
AD1GIRQEN2: ADC1 GLOBAL INTERRUPT ENABLE REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
AGIEN44
AGIEN43
AGIEN42
AGIEN41
AGIEN40
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN39
AGIEN38
AGIEN37
AGIEN36
AGIEN35
AGIEN34
AGIEN33
AGIEN32
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13
Unimplemented: Read as ‘0’
bit 12-0
AGIENx: Global ADC Interrupt Enable bits (‘x’ = 32-44)
1 = A data ready event (transition from 0 to 1 of the ARDYx bit) will generate a Global ADC interrupt
0 = No global interrupt is generated on a data ready event
Note 1:
2:
The enable bits do not affect assertion of the individual interrupt output. Interrupts generated for individual
ARDYx events are enabled in the IECx register.
AGIENx = ANx, where ‘x’ = 32-42, AGIEN43 = IVREF, and AGIEN44 = IVTEMP.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 427
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-7:
Bit Range
31:24
23:16
15:8
7:0
AD1CSS1: ADC1 INPUT SCAN SELECT REGISTER 1
Bit
31/23/15/7
Note 1:
2:
31:24
23:16
15:8
7:0
Note 1:
2:
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CSSx: ADC Input Scan Select bits (‘x’ = 0-31)
1 = Select ANx for input scan
0 = Skip ANx for input scan
CSSx = ANx, where ‘x’ = 0-31.
Class 1 and Class 2 analog inputs must select the STRIG input as the trigger source if they are to be
scanned through the CSSx bits. Refer to the bit descriptions in the AD1TRGn register (Register 28-15) for
selecting the STRIG option.
AD1CSS2: ADC1 INPUT SCAN SELECT REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS40
—
—
—
CSS44
CSS43
CSS42
CSS41
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS39
CSS38
CSS37
CSS36
CSS35
CSS34
CSS33
CSS32
Legend:
R = Readable bit
-n = Value at POR
bit 31-13
bit 12-0
Bit
28/20/12/4
R/W-0
REGISTER 28-8:
Bit Range
Bit
29/21/13/5
CSS31
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
30/22/14/6
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
CSSx: ADC Input Scan Select bits (‘x’ = 32-44)
1 = Select ANx for input scan
0 = Skip ANx for input scan
CSSx = ANx, where ‘x’ = 32-42, CSS43 = IVREF, and CS44 = IVTEMP.
Class 1 and Class 2 analog inputs must select the STRIG input as the trigger source if they are to be
scanned through the CSSx bits. Refer to the bit descriptions in the AD1TRGn register (Register 28-15) for
selecting the STRIG option.
DS60001191F-page 428
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-9:
Bit Range
31:24
23:16
15:8
7:0
AD1DSTAT1: ADC1 DATA READY STATUS REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
R-0, HS, HC R-0, HS, HC
ARDY31
ARDY30
R-0, HS, HC R-0, HS, HC
ARDY23
ARDY22
R-0, HS, HC R-0, HS, HC
ARDY15
ARDY14
R-0, HS, HC R-0, HS, HC
ARDY7
ARDY6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
ARDY29
ARDY28
ARDY27
ARDY26
ARDY21
ARDY20
ARDY19
ARDY18
ARDY17
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
ARDY13
ARDY12
ARDY11
ARDY10
ARDY9
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
ARDY5
ARDY4
ARDY3
ARDY2
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
ARDY25
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
Legend:
bit 31-0
Bit
25/17/9/1
ARDY1
Bit
24/16/8/0
R-0, HS, HC
ARDY24
R-0, HS, HC
ARDY16
R-0, HS, HC
ARDY8
R-0, HS, HC
ARDY0
x = Bit is unknown
ARDYx: Conversion Data Ready for Corresponding Analog Input Ready bits (‘x’ = 31-0)
1 = This bit is set when data is ready in the buffer. An interrupt will be generated if the appropriate bit in
the IECx register is set or if enabled for the ADC Global interrupt in the AD1GIRQEN register.
0 = This bit is cleared when the associated data register is read
ARDYx = ANx, where ‘x’ = 0-31.
REGISTER 28-10: AD1DSTAT2: ADC1 DATA READY STATUS REGISTER 2
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
—
—
—
R-0, HS, HC R-0, HS, HC
ARDY39
ARDY38
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
ARDY44
ARDY43
ARDY42
ARDY41
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
ARDY37
ARDY36
ARDY35
ARDY34
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
ARDY33
—
R-0, HS, HC
ARDY40
R-0, HS, HC
ARDY32
x = Bit is unknown
bit 31-13
Unimplemented: Read as ‘0’
bit 12-0
ARDYx: Conversion Data Ready for Corresponding Analog Input Ready bits (‘x’ = 32-44)
1 = This bit is set when data is ready in the buffer. An interrupt will be generated if the appropriate bit in
the IECx register is set or if enabled for the ADC Global interrupt in the AD1GIRQEN register.
0 = This bit is cleared when the associated data register is read
Note:
ARDYx = ANx, where ‘x’ =32-42, ARDY43 = IVREF, and ARDY44 = IVTEMP.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 429
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-11: AD1CMPCONn: ADC1 DIGITAL COMPARATOR CONTROL REGISTER ‘n’ 
(‘n’ = 1, 2, 3, 4, 5, OR 6)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
—
—
—
R/W-0
R/W-0
R-0, HS, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ENDCMP
DCMPGIEN(1)
DCMPED
IEBTWN(1)
IEHIHI(1)
IEHILO(1)
IELOHI(1)
IELOLO(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-13
bit 12-8
Bit
Bit
27/19/11/3 26/18/10/2
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
AINID<4:0>
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
AINID<4:0>: Analog Input Identification (ID) bits
When a digital comparator event occurs, these read-only bits contain the analog input identification
number. AINID = ANx, where ‘x’ = 0-31.
ENDCMP: Digital Comparator Enable bit
1 = Digital Comparator is enabled
0 = Digital Comparator is not enabled, and the DCMPED status bit is cleared
DCMPGIEN: Digital Comparator Global ADC Interrupt Enable bit(1)
1 = A Digital Comparator Event (DCMPED transitions from ‘0’ to ‘1’) will generate a Global ADC interrupt.
0 = A Digital Comparator Event will not generate a Global ADC interrupt.
DCMPED: Digital Comparator Event Detected Status bit
1 = This bit is set by the digital comparator hardware when a comparison event is detected. An interrupt will
be generated if the appropriate bit in the IECx register is set or if enabled for the ADC Global interrupt
in the DCMPGIEN bit.
0 = This bit is cleared by reading the AINID<4:0> bits or when the ADC module is disabled
IEBTWN: Between Low/High Digital Comparator Event bit(1)
1 = Generate a digital comparator event when ADCMPLO<15:0>  DATA<31:0> < ADCMPHI<15:0>
0 = Do not generate a digital comparator event
IEHIHI: High/High Digital Comparator Event bit(1)
1 = Generate a Digital Comparator Event when ADCMPHI<15:0>  DATA<31:0>
0 = Do not generate a digital comparator event when ADCMPHI<15:0>  DATA<31:0>
IEHILO: High/Low Digital Comparator Event bit(1)
1 = Generate a Digital Comparator Event when DATA<31:0> < ADCMPHI<15:0>
0 = Do not generate a digital comparator event when DATA<31:0> < ADCMPHI<15:0>
IELOHI: Low/High Digital Comparator Event bit(1)
1 = Generate a Digital Comparator Event when ADCMPLO<15:0>  DATA<31:0>
0 = Do not generate a digital comparator event when ADCMPLO<15:0>  DATA<31:0>
IELOLO: Low/Low Digital Comparator Event bit(1)
1 = Generate a Digital Comparator Event when DATA<31:0> < ADCMPLO<15:0>
0 = Do not generate a digital comparator event when DATA<31:0> < ADCMPLO<15:0>
Changing these bits while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable
behavior.
DS60001191F-page 430
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-12: AD1CMPENn: ADC1 DIGITAL COMPARATOR ENABLE REGISTER ‘n’ 
(‘n’ = 1, 2, 3, 4, 5 OR 6)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE31
CMPE30
CMPE29
CMPE28
CMPE27
CMPE26
CMPE25
CMPE24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE23
CMPE22
CMPE21
CMPE20
CMPE19
CMPE18
CMPE17
CMPE16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE7
CMPE6
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
x = Bit is unknown
CMPE31:CMPE0: ADC1 Digital Comparator Enable bits
These bits enable conversion results corresponding to the Analog Input to be processed by the digital
comparator.
CMPEx = ANx, where ‘x’ = 0-31.
Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in
unpredictable behavior.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 431
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-13: AD1CMPn: ADC1 DIGITAL COMPARATOR REGISTER ‘n’ (‘n’ = 1, 2, 3, 4, 5 OR 6)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
27/19/11/3 26/18/10/2
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCMPHI<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCMPHI<7:0>
R/W-0
ADCMPLO<15:8>
R/W-0
ADCMPLO<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
ADCMPHI<15:0>: Digital Analog Comparator High Limit Value bits
These bits store the high limit value, which is used for comparisons with the analog-to-digital conversion
data. The user is responsible for formatting the data as signed or unsigned to match the data format as
specified by the SHxMOD<1:0> bits for the associated S&H circuit and the FRACT bit.
bit 15-0
ADCMPLO<15:0>: Digital Analog Comparator Low Limit Value bits
These bits store the low limit value, which is used for comparisons with the analog-to-digital conversion
data. The user is responsible for formatting the data as signed or unsigned to match the data format as
specified by the SHxMOD<1:0> bits for the associated S&H circuit and the FRACT bit.
Note:
Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in
unpredictable behavior.
DS60001191F-page 432
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-14: AD1FLTRn: ADC1 FILTER REGISTER ‘n’ (‘n’ = 1, 2, 3, 4, 5, OR 6)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0, HS
AFGIEN
AFRDY
R/W-0
R/W-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
31:24
AFEN
—
—
U-0
U-0
R/W-0
—
—
R-0, HS, HC
R-0, HS, HC
23:16
15:8
7:0
bit 30-29
bit 28-26
bit 25
bit 24
bit 23-22
bit 21-16
R/W-0
R/W-0
CHNLID<5:0>
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC R-0, HS, HC
FLTRDATA<15:8>
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC R-0, HS, HC
FLTRDATA<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31
OVRSAM<2:0>
R/W-0
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
AFEN: Oversampling Filter Enable bit
1 = Oversampling filter is enabled
0 = Oversampling filter is disabled and the AFRDY bit is cleared
Unimplemented: Read as ‘0’
OVRSAM<2:0>: Oversampling Filter Ratio bits
111 = 128x (shift sum 3 bits to right, output data is in 15.1 format)
110 = 32x (shift sum 2 bits to right, output data is in 14.1 format)
101 = 8x (shift sum 1 bit to right, output data is in 13.1 format)
100 = 2x (shift sum 0 bits to right, output data is in 12.1 format)
011 = 256x (shift sum 4 bits to right, output data is 16 bits)
010 = 64x (shift sum 3 bits to right, output data is 15 bits)
001 = 16x (shift sum 2 bits to right, output data is 14 bits)
000 = 4x (shift sum 1 bit to right, output data is 13 bits)
AFGIEN: Oversampling Filter Global ADC Interrupt Enable bit
1 = An Oversampling Filter Data Ready event (AFRDY transitions from ‘0’ to ‘1’) will generate an ADC
Global Interrupt
0 = An Oversampling Filter Data Ready event will not generate an ADC Global Interrupt
AFRDY: Oversampling Filter Data Ready Flag bit
1 = This bit is set when data is ready in the FLTRDATA<15:0> bits
0 = This bit is cleared when FLTRDATA<15:0> is read, or if the module is disabled
Unimplemented: Read as ‘0’
CHNLID<5:0>: Channel ID Selection bits
These bits specify the analog input to be used as the oversampling filter data source.
111111 = Reserved
•
•
•
101101 = Reserved
101100 = IVTEMP
101011 = IVREF
101010 = AN42
•
•
•
bit 15-0
000010 = AN2
000001 = AN1
000000 = AN0
FLTRDATA<15:0>: Oversampling Filter Data Output Value bits
These bits contain the oversampling filter result.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 433
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-15: AD1TRG1: ADC1 INPUT CONVERT CONTROL REGISTER 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
TRGSRC3<4:0>
R/W-0
R/W-0
R/W-0
TRGSRC2<4:0>(1)
R/W-0
R/W-0
R/W-0
TRGSRC1<4:0>(1)
R/W-0
R/W-0
R/W-0
TRGSRC0<4:0>(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC3<4:0>: Trigger Source for Conversion of Analog Channel AN3 Select bits(1)
11111 = Reserved
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT(2)
01011 = Comparator 1 COUT(2)
01010 = OCMP5(2)
01001 = OCMP3(2)
01000 = OCMP1(2)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = STRIG(3)
00010 = Reserved
00001 = Global software trigger (GSWTRG)
00000 = No trigger
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC2<4:0>: Trigger Source for Conversion of Analog Channel AN2 Select bits(1)
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC1<4:0>: Trigger Source for Conversion of Analog Channel AN1 Select bits(1)
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC0<4:0>: Trigger Source for Conversion of Analog Channel AN0 Select bits(1)
See bits 28-24 for bit value definitions.
Note 1:
2:
3:
If the same trigger source is used for multiple ANx channels, the trigger source must wait until the hold
time for all channels has completed (due to the last trigger) and the sample time for all ANx channels is
satisfied before issuing the next trigger. This condition can cause hole insertions into the ADC pipeline
and affect overall ADC throughput.
The rising edge of the associated module output signal triggers the conversion. Refer to the block diagram
of the specific module for more information.
Using STRIG as the trigger source specifies this input to use the Scan Trigger source for its trigger. The
STRGSRC<4:0> bits (AD1CON1<26:22>), as well as the appropriate CSSx bit(s) in the AD1CSS1 and
AD1CSS2 registers must be set for proper scan operation.
DS60001191F-page 434
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-16: AD1TRG2: ADC1 INPUT CONVERT CONTROL REGISTER 2
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
TRGSRC7<4:0>
R/W-0
R/W-0
R/W-0
TRGSRC6<4:0>(1)
R/W-0
R/W-0
R/W-0
TRGSRC5<4:0>(1)
R/W-0
R/W-0
R/W-0
TRGSRC4<4:0>(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC7<4:0>: Trigger Source for Conversion of Analog Channel AN7 Select bits(1)
11111 = Reserved
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT(2)
01011 = Comparator 1 COUT(2)
01010 = OCMP5(2)
01001 = OCMP3(2)
01000 = OCMP1(2)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = STRIG(3)
00010 = Reserved
00001 = Global software trigger (GSWTRG)
00000 = No trigger
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC6<4:0>: Trigger Source for Conversion of Analog Channel AN6 Select bits(1)
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC5<4:0>: Trigger Source for Conversion of Analog Channel AN5 Select bits(1)
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC4<4:0>: Trigger Source for Conversion of Analog Channel AN4 Select bits(1)
See bits 28-24 for bit value definitions.
Note 1:
2:
3:
If the same trigger source is used for multiple ANx channels, the trigger source must wait until the hold
time for all channels has completed (due to the last trigger) and the sample time for all ANx channels is
satisfied before issuing the next trigger. This condition can cause hole insertions into the ADC pipeline
and affect overall ADC throughput.
The rising edge of the associated module output signal triggers the conversion. Refer to the block diagram
of the specific module for more information.
Using STRIG as the trigger source specifies this input to use the Scan Trigger source for its trigger. The
STRGSRC<4:0> bits (AD1CON1<26:22>), as well as the appropriate CSSx bit(s) in the AD1CSS1 and
AD1CSS2 registers must be set for proper scan operation.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 435
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-17: AD1TRG3: ADC1 INPUT CONVERT CONTROL REGISTER 3
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
TRGSRC11<4:0>
R/W-0
R/W-0
R/W-0
TRGSRC10<4:0>(1)
R/W-0
R/W-0
R/W-0
TRGSRC9<4:0>(1)
R/W-0
R/W-0
R/W-0
TRGSRC8<4:0>(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC11<4:0>: Trigger Source for Conversion of Analog Channel AN11 Select bits(1)
11111 = Reserved
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT(2)
01011 = Comparator 1 COUT(2)
01010 = OCMP5(2)
01001 = OCMP3(2)
01000 = OCMP1(2)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = STRIG(3)
00010 = Reserved
00001 = Global software trigger (GSWTRG)
00000 = No trigger
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC10<4:0>: Trigger Source for Conversion of Analog Channel AN10 Select bits(1)
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC9<4:0>: Trigger Source for Conversion of Analog Channel AN9 Select bits(1)
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC8<4:0>: Trigger Source for Conversion of Analog Channel AN8 Select bits(1)
See bits 28-24 for bit value definitions.
Note 1:
2:
3:
If the same trigger source is used for multiple ANx channels, the trigger source must wait until the hold
time for all channels has completed (due to the last trigger) and the sample time for all ANx channels is
satisfied before issuing the next trigger. This condition can cause hole insertions into the ADC pipeline
and affect overall ADC throughput.
The rising edge of the associated module output signal triggers the conversion. Refer to the block diagram
of the specific module for more information.
Using STRIG as the trigger source specifies this input to use the Scan Trigger source for its trigger. The
STRGSRC<4:0> bits (AD1CON1<26:22>), as well as the appropriate CSSx bit(s) in the AD1CSS1 and
AD1CSS2 registers must be set for proper scan operation.
DS60001191F-page 436
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-18: AD1DATAn: ADC1 DATA OUTPUT REGISTER (‘n’ = 0 through 44)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
R-0
R-0
R-0
R-0
Bit
Bit
27/19/11/3 26/18/10/2
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DATA<31:24>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DATA<23:16>
R-0
DATA<15:8>
R-0
DATA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
x = Bit is unknown
DATA<31:0>: Data Output Value bits (formatted as specified by the SHxMOD<1:0> bits for the associated
S&H circuits and the FRACT bit)
AD1DATAn = ANx, where ‘x’ and ‘n’ =0-42, AD1DATA 43 = IVREF, and AD1DATA44 = IVTEMP.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 437
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 28-19: AD1CALx: ADC1 CALIBRATION REGISTER ‘x’ (‘x’ = 1-5)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCAL<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCAL<23:16>
R/W-0
ADCAL<15:8>
R/W-0
ADCAL<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 ADCAL<31:0>: Calibration Data for the ADC Module bits
This data must be copied from the corresponding DEVADCx register. Refer to Section 34.1 “Configuration
Bits” for more information.
DS60001191F-page 438
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
29.0
Note:
CONTROLLER AREA
NETWORK (CAN)
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” (DS60001154),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Controller Area Network (CAN) module supports
the following key features:
• Standards Compliance:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a
total of 1024 messages
- FIFO can be a transmit message FIFO or a
receive message FIFO
FIGURE 29-1:
- User-defined priority levels for message
FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
- Loopback, Listen All Messages and Listen
Only modes for self-test, system diagnostics
and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the PIC32
System Bus
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data-only Message Reception mode
Figure 29-1 illustrates the general structure of the CAN
module.
Note:
To avoid cache coherency problems on
devices with L1 cache, CAN buffers must
only be allocated or accessed from the
KSEG1 segment.
PIC32 CAN MODULE BLOCK DIAGRAM
CxTX
PBCLK5
(‘x’ = 1-2)
32 Filters
4 Masks
CPU
CxRX
CAN Module
Up to 32 Message Buffers
System Bus
Message
Buffer Size
2 or 4 Words
System RAM
Message Buffer 31
Message Buffer 31
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
FIFO1
FIFO31
FIFO0
CAN Message FIFO (up to 32 FIFOs)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 439
CAN Control Registers
Note:
The ‘i’ shown in register names denotes
CAN1 or CAN2.
Virtual Address
(BF88_#)
Register
Name(1)
TABLE 29-1:
0000
C1CON
0010
C1CFG
CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES
0020
C1INT
0030
C1VEC
0040
C1TREC
0050
C1FSTAT
0060
C1RXOVF
0070
C1TMR
0080
C1RXM0
0090
C1RXM1
 2013-2016 Microchip Technology Inc.
00A0
C1RXM2
00B0
C1RXM3
00C0 C1FLTCON0
00D0 C1FLTCON1
00E0 C1FLTCON2
Legend:
Note
1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 SEG2PHTS
29/13
28/12
—
—
—
ABAT
—
SIDLE
—
CANBUSY
—
—
—
—
—
—
SAM
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
WAKFIL
—
REQOP<2:0>
SEG1PH<2:0>
22/6
21/5
OPMOD<2:0>
PRSEG<2:0>
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT<4:0>
—
SJW<1:0>
—
All Resets
Bit Range
Bits
0480
0000
SEG2PH<2:0>
0000
BRP<5:0>
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
0000
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
TXWARN
RXWARN
15:0
FILHIT<4:0>
—
—
—
ICODE<6:0>
—
TXBO
—
—
—
FIFOIP24
FIFOIP23
FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18
FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP1
TERRCNT<7:0>
RXBP
EWARN 0000
RERRCNT<7:0>
31:16 FIFOIP31
FIFOIP30
FIFOIP29 FIFOIP28 FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14
FIFOIP13 FIFOIP12 FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
TXBP
0040
—
FIFOIP8
FIFOIP5
FIFOIP4
0000
FIFOIP3
FIFOIP2
FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0 0000
CANTS<15:0>
15:0
0000
CANTSPRE<15:0>
31:16
0000
SID<10:0>
15:0
-—
MIDE
—
EID<17:16>
xxxx
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
xxxx
-—
MIDE
—
EID<17:16>
xxxx
xxxx
EID<15:0>
31:16
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
SID<10:0>
15:0
EID<15:0>
31:16
FLTEN3
MSEL3<1:0>
FSEL3<4:0>
FLTEN2
MSEL2<1:0>
FSEL2<4:0>
0000
15:0
FLTEN1
MSEL1<1:0>
FSEL1<4:0>
FLTEN0
MSEL0<1:0>
FSEL0<4:0>
0000
31:16
FLTEN7
MSEL7<1:0>
FSEL7<4:0>
FLTEN6
MSEL6<1:0>
FSEL6<4:0>
0000
15:0
FLTEN5
MSEL5<1:0>
FSEL5<4:0>
FLTEN4
MSEL4<1:0>
FSEL4<4:0>
0000
31:16 FLTEN11
MSEL11<1:0>
FSEL11<4:0>
FLTEN10
MSEL10<1:0>
FSEL10<4:0>
0000
15:0
MSEL9<1:0>
FSEL9<4:0>
FLTEN8
MSEL8<1:0>
FSEL8<4:0>
0000
FLTEN9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 440
29.1
Virtual Address
(BF88_#)
0100 C1FLTCON4
0110 C1FLTCON5
0120 C1FLTCON6
0130 C1FLTCON7
0340
C1RXFn
(n = 0-31)
C1FIFOBA
C1FIFOINTn
(n = 0)
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FLTEN15
MSEL15<1:0>
FSEL15<4:0>
FLTEN14
MSEL14<1:0>
FSEL14<4:0>
0000
15:0
FLTEN13
MSEL13<1:0>
FSEL13<4:0>
FLTEN12
MSEL12<1:0>
FSEL12<4:0>
0000
31:16 FLTEN19
MSEL19<1:0>
FSEL19<4:0>
FLTEN18
MSEL18<1:0>
FSEL18<4:0>
0000
15:0
FLTEN17
MSEL17<1:0>
FSEL17<4:0>
FLTEN16
MSEL16<1:0>
FSEL16<4:0>
0000
31:16 FLTEN23
MSEL23<1:0>
FSEL23<4:0>
FLTEN22
MSEL22<1:0>
FSEL22<4:0>
0000
15:0
FLTEN21
MSEL21<1:0>
FSEL21<4:0>
FLTEN20
MSEL20<1:0>
FSEL20<4:0>
0000
31:16 FLTEN27
MSEL27<1:0>
FSEL27<4:0>
FLTEN26
MSEL26<1:0>
FSEL26<4:0>
0000
15:0
FLTEN25
MSEL25<1:0>
FSEL25<4:0>
FLTEN24
MSEL24<1:0>
FSEL24<4:0>
0000
31:16 FLTEN31
MSEL31<1:0>
FSEL31<4:0>
FLTEN30
MSEL30<1:0>
FSEL30<4:0>
0000
15:0
MSEL29<1:0>
FSEL29<4:0>
FLTEN28
MSEL28<1:0>
FSEL28<4:0>
FLTEN29
31:16
SID<10:0>
-—
15:0
EXID
—
0000
EID<17:16>
EID<15:0>
31:16
xxxx
xxxx
0000
C1FIFOBA<31:0>
15:0
C1FIFOCONn 31:16
0350
(n = 0)
15:0
0360
31/15
All Resets
Bit Range
Register
Name(1)
Bits
00F0 C1FLTCON3
01400330
CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES (CONTINUED)
0000
—
—
—
—
—
—
—
—
—
—
—
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
FSIZE<4:0>
TXERR
TXREQ
RTREN
0000
TXPRI<1:0>
0000
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
RXN
RXOVFLIE RXFULLIE RXHALFIE
0000
EMPTYIE
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
RXN
0000
EMPTYIF
0370
C1FIFOUAn 31:16
(n = 0)
15:0
0380
C1FIFOCIn 31:16
(n = 0)
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1FIFOCI<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
FSIZE<4:0>
15:0
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
TXERR
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
RXOVFLIE RXFULLIE RXHALFIE
RXN
0000
EMPTYIE
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
RXN
0000
EMPTYIF
C1FIFOCONn
C1FIFOINTn
0390C1FIFOUAn 15:0
0B40
C1FIFOCIn
(n = 1-31) 31:16
15:0
DS60001191F-page 441
Legend:
Note
1:
0000
C1FIFOUA<31:0>
0000
—
—
—
TXREQ
RTREN
—
—
0000
0000
0000
TXPRI<1:0>
0000
0000
C1FIFOUA<31:0>
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1FIFOCI<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 29-1:
Virtual Address
(BF88_#)
Register
Name(1)
1000
C2CON
1010
C2CFG
1040
1050
1060
1070
C2INT
C2VEC
C2TREC
C2FSTAT
C2RXOVF
C2TMR
1080
C2RXM0
10A0
C2RXM1
10B0
10B0
C2RXM2
C2RXM3
 2013-2016 Microchip Technology Inc.
1010 C2FLTCON0
10D0 C2FLTCON1
10E0 C2FLTCON2
10F0 C2FLTCON3
Legend:
Note
1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 SEG2PHTS
29/13
28/12
—
—
—
ABAT
—
SIDLE
—
CANBUSY
—
—
—
—
—
—
SAM
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
WAKFIL
—
—
—
REQOP<2:0>
SEG1PH<2:0>
22/6
21/5
OPMOD<2:0>
PRSEG<2:0>
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT<4:0>
SJW<1:0>
All Resets
Bit Range
Bits
1020
1030
CAN2 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES
0480
0000
SEG2PH<2:0>
0000
BRP<5:0>
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
0000
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN
RXWARN
EWARN
0000
FIFOIP24
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
15:0
FILHIT<4:0>
—
ICODE<6:0>
TERRCNT<7:0>
0040
RERRCNT<7:0>
31:16 FIFOIP31
FIFOIP30 FIFOIP29 FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14 FIFOIP13 FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP8
0000
FIFOIP0
0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
CANTS<15:0>
15:0
0000
CANTSPRE<15:0>
31:16
0000
SID<10:0>
15:0
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
0000
EID<15:0>
xxxx
31:16
FLTEN3
MSEL3<1:0>
FSEL3<4:0>
FLTEN2
MSEL2<1:0>
FSEL2<4:0>
0000
15:0
FLTEN1
MSEL1<1:0>
FSEL1<4:0>
FLTEN0
MSEL0<1:0>
FSEL0<4:0>
0000
31:16
FLTEN7
MSEL7<1:0>
FSEL7<4:0>
FLTEN6
MSEL6<1:0>
FSEL6<4:0>
0000
15:0
FLTEN5
MSEL5<1:0>
FSEL5<4:0>
FLTEN4
MSEL4<1:0>
FSEL4<4:0>
0000
31:16 FLTEN11
MSEL11<1:0>
FSEL11<4:0>
FLTEN10
MSEL10<1:0>
FSEL10<4:0>
0000
15:0
FLTEN9
MSEL9<1:0>
FSEL9<4:0>
FLTEN8
MSEL8<1:0>
FSEL8<4:0>
0000
31:16 FLTEN15
MSEL15<1:0>
FSEL15<4:0>
FLTEN14
MSEL14<1:0>
FSEL14<4:0>
0000
15:0
MSEL13<1:0>
FSEL13<4:0>
FLTEN12
MSEL12<1:0>
FSEL12<4:0>
0000
FLTEN13
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 442
TABLE 29-2:
Virtual Address
(BF88_#)
1110 C2FLTCON5
1120 C2FLTCON6
1130 C2FLTCON7
1340
C2RXFn
(n = 0-31)
C2FIFOBA
C2FIFOINTn
(n = 0)
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FLTEN19
MSEL19<1:0>
FSEL19<4:0>
FLTEN18
MSEL18<1:0>
FSEL18<4:0>
0000
15:0
FLTEN17
MSEL17<1:0>
FSEL17<4:0>
FLTEN16
MSEL16<1:0>
FSEL16<4:0:
0000
31:16 FLTEN23
MSEL23<1:0>
FSEL23<4:0>
FLTEN22
MSEL22<1:0>
FSEL22<4:0>
0000
15:0
FLTEN21
MSEL21<1:0>
FSEL21<4:0>
FLTEN20
MSEL20<1:0>
FSEL20<4:0>
0000
31:16 FLTEN27
MSEL27<1:0>
FSEL27<4:0>
FLTEN26
MSEL26<1:0>
FSEL26<4:0>
0000
15:0
FLTEN25
MSEL25<1:0>
FSEL25<4:0>
FLTEN24
MSEL24<1:0>
FSEL24<4:0>
0000
31:16 FLTEN31
MSEL31<1:0>
FSEL31<4:0>
FLTEN30
MSEL30<1:0>
FSEL30<4:0>
0000
15:0
MSEL29<1:0>
FSEL29<4:0>
FLTEN28
MSEL28<1:0>
FSEL28<4:0>
FLTEN29
31:16
-—
SID<10:0>
15:0
EXID
—
0000
EID<17:16>
EID<15:0>
31:16
xxxx
xxxx
0000
C2FIFOBA<31:0>
15:0
C2FIFOCONn 31:16
1350
(n = 0)
15:0
1360
31/15
All Resets
Bit Range
Register
Name(1)
Bits
1100 C2FLTCON4
11401330
CAN2 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES (CONTINUED)
0000
—
—
—
—
—
—
—
—
—
—
—
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
FSIZE<4:0>
TXERR
TXREQ
RTREN
0000
TXPRI<1:0>
0000
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
RXN
0000
RXOVFLIE RXFULLIE RXHALFIE
EMPTYIE
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
1370
C2FIFOUAn 31:16
(n = 0)
15:0
1380
C2FIFOCIn 31:16
(n = 0)
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2FIFOCI<4:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
FSIZE<4:0>
15:0
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
RXN
0000
EMPTYIF
0000
C2FIFOUA<31:0>
0000
—
TXERR
—
TXREQ
—
RTREN
—
—
0000
0000
0000
TXPRI<1:0>
0000
DS60001191F-page 443
31:16
C2FIFOCONn
C2FIFOINTn
1390C2FIFOUAn 15:0
1B40
C2FIFOCIn
(n = 1-31) 31:16
15:0
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
RXN
0000
RXOVFLIE RXFULLIE RXHALFIE
EMPTYIE
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
Legend:
Note
1:
RXN
0000
EMPTYIF
0000
C2FIFOUA<31:0>
0000
—
—
—
—
—
C2FIFOCI<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
0000
0000
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 29-2:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-1:
Bit
Range
31:24
23:16
15:8
7:0
CiCON: CAN MODULE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
S/HC-0
R/W-1
—
—
—
—
ABAT
R-0
R-0
R/W-0
U-0
U-0
U-0
U-0
CANCAP
—
—
—
—
U-0
R-1
OPMOD<2:0>
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
REQOP<2:0>
R/W-0
U-0
R/W-0
U-0
R-0
U-0
U-0
ON(1)
—
SIDLE
—
CANBUSY
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DNCNT<4:0>
Legend:
HC = Hardware Clear
S = Settable bit
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-28 Unimplemented: Read as ‘0’
bit 27
ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved - Do not use
101 = Reserved - Do not use
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 20
CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message
0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
bit 19-16 Unimplemented: Read as ‘0’
bit 15
ON: CAN On bit(1)
1 = CAN module is enabled
0 = CAN module is disabled
bit 14
Unimplemented: Read as ‘0’
Note 1:
If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
DS60001191F-page 444
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-1:
CiCON: CAN MODULE CONTROL REGISTER (CONTINUED)
bit 13
SIDLE: CAN Stop in Idle bit
1 = CAN Stops operation when system enters Idle mode
0 = CAN continues operation when system enters Idle mode
bit 12
Unimplemented: Read as ‘0’
bit 11
CANBUSY: CAN Module is Busy bit
1 = The CAN module is active
0 = The CAN module is completely disabled
bit 10-5
Unimplemented: Read as ‘0’
bit 4-0
DNCNT<4:0>: Device Net Filter Bit Number bits
10011-11111 = Invalid Selection (compare up to 18-bits of data with EID)
10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)
•
•
•
00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)
00000 = Do not compare data bytes
Note 1:
If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 445
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-2:
Bit
Range
31:24
23:16
15:8
7:0
CiCFG: CAN BAUD RATE CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
WAKFIL
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
SEG2PHTS
(1)
(2)
SAM
R/W-0
R/W-0
SEG1PH<2:0>
R/W-0
SEG2PH<2:0>(1,4)
R/W-0
R/W-0
(4)
R/W-0
R/W-0
R/W-0
(4)
PRSEG<2:0>
R/W-0
(3)
SJW<1:0>
R/W-0
R/W-0
R/W-0
BRP<5:0>
Legend:
HC = Hardware Clear
S = Settable bit
R = Readable bit
W = Writable bit
P = Programmable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-23 Unimplemented: Read as ‘0’
bit 22
WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 21-19 Unimplemented: Read as ‘0’
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits(1,4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 15
SEG2PHTS: Phase Segment 2 Time Select bit(1)
1 = Freely programmable
0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14
SAM: Sample of the CAN Bus Line bit(2)
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
Note 1:
2:
3:
4:
Note:
SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
3 Time bit sampling is not allowed for BRP < 2.
SJW  SEG2PH.
The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
DS60001191F-page 446
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-2:
CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED)
bit 10-8
PRSEG<2:0>: Propagation Time Segment bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7-6
SJW<1:0>: Synchronization Jump Width bits(3)
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/TPBCLK5
111110 = TQ = (2 x 63)/TPBCLK5
•
•
•
000001 = TQ = (2 x 2)/TPBCLK5
000000 = TQ = (2 x 1)/TPBCLK5
Note 1:
2:
3:
4:
SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
3 Time bit sampling is not allowed for BRP < 2.
SJW  SEG2PH.
The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 447
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-3:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
CiINT: CAN INTERRUPT REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
(1)
IVRIF
WAKIF
CERRIF
RBOVIF
—
—
—
U-0
U-0
U-0
SERRIF
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 30
WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 29
CERRIE: CAN Bus Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 28
SERRIE: System Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 27
RBOVIE: Receive Buffer Overflow Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
x = Bit is unknown
bit 26-20 Unimplemented: Read as ‘0’
bit 19
MODIE: Mode Change Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 18
CTMRIE: CAN Timestamp Timer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 17
RBIE: Receive Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 16
TBIE: Transmit Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 15
IVRIF: Invalid Message Received Interrupt Flag bit
1 = An invalid messages interrupt has occurred
0 = An invalid message interrupt has not occurred
Note 1:
This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).
DS60001191F-page 448
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-3:
CiINT: CAN INTERRUPT REGISTER (CONTINUED)
bit 14
WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = A bus wake-up activity interrupt has occurred
0 = A bus wake-up activity interrupt has not occurred
bit 13
CERRIF: CAN Bus Error Interrupt Flag bit
1 = A CAN bus error has occurred
0 = A CAN bus error has not occurred
bit 12
SERRIF: System Error Interrupt Flag bit(1)
1 = A system error occurred (typically an illegal address was presented to the System Bus)
0 = A system error has not occurred
bit 11
RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred
0 = A receive buffer overflow has not occurred
bit 10-4
Unimplemented: Read as ‘0’
bit 3
MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)
0 = A CAN module mode change has not occurred
bit 2
CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred
0 = A CAN timer (CANTMR) overflow has not occurred
bit 1
RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending
0 = A receive buffer interrupt is not pending
bit 0
TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending
0 = A transmit buffer interrupt is not pending
Note 1:
This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 449
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-4:
Bit
Range
31:24
23:16
15:8
7:0
CiVEC: CAN INTERRUPT CODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
—
U-0
R-1
R-0
FILHIT<4:0>
—
ICODE<6:0>
R-0
(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8
FILHIT<4:0>: Filter Hit Number bit
11111 = Filter 31
11110 = Filter 30
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE<6:0>: Interrupt Flag Code bits(1)
1001000-1111111 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SERRIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT<31> set)
0011110 = FIFO30 Interrupt (CiFSTAT<30> set)
•
•
•
0000001 = FIFO1 Interrupt (CiFSTAT<1> set)
0000000 = FIFO0 Interrupt (CiFSTAT<0> set)
Note 1:
These bits are only updated for enabled interrupts.
DS60001191F-page 450
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-5:
Bit
Range
31:24
23:16
15:8
7:0
CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT<7:0>
R-0
RERRCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21
TXBO: Transmitter in Error State Bus OFF (TERRCNT  256)
bit 20
TXBP: Transmitter in Error State Bus Passive (TERRCNT  128)
bit 19
RXBP: Receiver in Error State Bus Passive (RERRCNT  128)
bit 18
TXWARN: Transmitter in Error State Warning (128 > TERRCNT  96)
bit 17
RXWARN: Receiver in Error State Warning (128 > RERRCNT  96)
bit 16
EWARN: Transmitter or Receiver is in Error State Warning
bit 15-8
TERRCNT<7:0>: Transmit Error Counter
bit 7-0
RERRCNT<7:0>: Receive Error Counter
REGISTER 29-6:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
CiFSTAT: CAN FIFO STATUS REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP31
FIFOIP30
FIFOIP29
FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
FIFOIP24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17
FIFOIP16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP15
FIFOIP14
FIFOIP13
FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
FIFOIP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 FIFOIP<31:0>: FIFOn Interrupt Pending bits
1 = One or more enabled FIFO interrupts are pending
0 = No FIFO interrupts are pending
 2013-2016 Microchip Technology Inc.
DS60001191F-page 451
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-7:
Bit
Range
31:24
23:16
15:8
7:0
CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF31
RXOVF30
RXOVF29
RXOVF28
RXOVF27
RXOVF26
RXOVF25
RXOVF24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF23
RXOVF22
RXOVF21
RXOVF20
RXOVF19
RXOVF18
RXOVF17
RXOVF16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF15
RXOVF14
RXOVF13
RXOVF12
RXOVF11
RXOVF10
RXOVF9
RXOVF8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF7
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
RXOVF<31:0>: FIFOn Receive Overflow Interrupt Pending bit
1 = FIFO has overflowed
0 = FIFO has not overflowed
REGISTER 29-8:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CiTMR: CAN TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTS<15:8>
R/W-0
CANTS<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTSPRE<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTSPRE<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
CANTS<15:0>: CAN Time Stamp Timer bits
This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit
(CiCON<20>) is set.
bit 15-0
CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits
1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks
•
•
•
0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock
Note 1:
2:
CiTMR will be frozen when CANCAP = 0.
The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).
DS60001191F-page 452
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-9:
Bit
Range
31:24
23:16
15:8
7:0
CiRXMN: CAN ACCEPTANCE FILTER MASK N REGISTER (N = 0, 1, 2 OR 3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SID<10:3>
R/W-0
R/W-0
R/W-0
SID<2:0>
U-0
R/W-0
U-0
—
MIDE
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EID<17:16>
EID<15:8>
R/W-0
EID<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21
SID<10:0>: Standard Identifier bits
1 = Include bit, SIDx, in filter comparison
0 = Bit SIDx is ‘don’t care’ in filter operation
bit 20
Unimplemented: Read as ‘0’
bit 19
MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 18
Unimplemented: Read as ‘0’
bit 17-0
EID<17:0>: Extended Identifier bits
1 = Include bit, EIDx, in filter comparison
0 = Bit EIDx is ‘don’t care’ in filter operation
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 453
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN3
R/W-0
FLTEN2
R/W-0
FLTEN1
R/W-0
FLTEN0
MSEL3<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL2<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
MSEL1<1:0>
R/W-0
Bit
25/17/9/1
FSEL3<4:0>
MSEL2<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL1<4:0>
MSEL0<1:0>
R/W-0
FSEL0<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN3: Filter 3 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL3<1:0>: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL3<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN2: Filter 2 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL2<1:0>: Filter 2 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL2<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 454
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED)
bit 15
FLTEN1: Filter 1 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL1<1:0>: Filter 1 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL1<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN0: Filter 0 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL0<1:0>: Filter 0 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL0<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 455
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN7
R/W-0
FLTEN6
R/W-0
FLTEN5
R/W-0
FLTEN4
MSEL7<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL6<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
MSEL5<1:0>
R/W-0
Bit
25/17/9/1
FSEL7<4:0>
MSEL6<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL5<4:0>
MSEL4<1:0>
R/W-0
FSEL4<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN6: Filter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 456
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
bit 15
FLTEN5: Filter 17 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL5<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN4: Filter 4 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL4<1:0>: Filter 4 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL4<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 457
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN11
R/W-0
FLTEN10
R/W-0
FLTEN9
R/W-0
FLTEN8
MSEL11<1:0>
R/W-0
R/W-0
FSEL11<4:0>
R/W-0
R/W-0
MSEL10<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL9<1:0>
R/W-0
R/W-0
R/W-0
FSEL10<4:0>
R/W-0
FSEL9<4:0>
MSEL8<1:0>
R/W-0
FSEL8<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN11: Filter 11 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL11<1:0>: Filter 11 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL11<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN10: Filter 10 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL10<1:0>: Filter 10 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL10<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 458
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)
bit 15
FLTEN9: Filter 9 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL9<1:0>: Filter 9 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL9<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN8: Filter 8 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL8<1:0>: Filter 8 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL8<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 459
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN15
R/W-0
FLTEN14
R/W-0
FLTEN13
R/W-0
FLTEN12
MSEL15<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL14<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL13<1:0>
R/W-0
Bit
25/17/9/1
FSEL15<4:0>
MSEL14<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL13<4:0>
R/W-0
MSEL12<1:0>
R/W-0
FSEL12<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN15: Filter 15 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL15<1:0>: Filter 15 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL15<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN14: Filter 14 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL14<1:0>: Filter 14 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL14<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 460
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED)
bit 15
FLTEN13: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL13<1:0>: Filter 13 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL13<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN12: Filter 12 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL12<1:0>: Filter 12 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL12<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 461
PIC32MZ Embedded Connectivity (EC) Family
,4
REGISTER 29-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN19
R/W-0
FLTEN18
R/W-0
FLTEN17
R/W-0
FLTEN16
MSEL19<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL18<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL17<1:0>
R/W-0
Bit
25/17/9/1
FSEL19<4:0>
MSEL18<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL17<4:0>
R/W-0
MSEL16<1:0>
R/W-0
FSEL16<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN19: Filter 19 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL19<1:0>: Filter 19 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL19<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN18: Filter 18 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL18<1:0>: Filter 18 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL18<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 462
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED)
bit 15
FLTEN17: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL17<1:0>: Filter 17 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL17<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN16: Filter 16 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL16<1:0>: Filter 16 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL16<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 463
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN23
R/W-0
23:16
FLTEN22
R/W-0
15:8
FLTEN21
R/W-0
7:0
FLTEN20
MSEL23<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL22<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL21<1:0>
R/W-0
Bit
25/17/9/1
FSEL23<4:0>
MSEL22<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL21<4:0>
R/W-0
MSEL20<1:0>
R/W-0
FSEL20<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN23: Filter 23 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL23<1:0>: Filter 23 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL23<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN22: Filter 22 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL22<1:0>: Filter 22 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL22<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 464
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED)
bit 15
FLTEN21: Filter 21 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL21<1:0>: Filter 21 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL21<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN20: Filter 20 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL20<1:0>: Filter 20 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL20<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 465
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN27
R/W-0
FLTEN26
R/W-0
FLTEN25
R/W-0
FLTEN24
MSEL27<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL26<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL25<1:0>
R/W-0
Bit
25/17/9/1
FSEL27<4:0>
MSEL26<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL25<4:0>
R/W-0
MSEL24<1:0>
R/W-0
FSEL24<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN27: Filter 27 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL27<1:0>: Filter 27 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL27<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN26: Filter 26 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL26<1:0>: Filter 26 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL26<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 466
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED)
bit 15
FLTEN25: Filter 25 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL25<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN24: Filter 24 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL24<1:0>: Filter 24 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL24<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 467
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN31
R/W-0
FLTEN30
R/W-0
FLTEN29
R/W-0
FLTEN28
MSEL31<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL30<4:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL29<1:0>
R/W-0
Bit
25/17/9/1
FSEL31<4:0>
MSEL30<1:0>
R/W-0
Bit
26/18/10/2
R/W-0
FSEL29<4:0>
R/W-0
MSEL28<1:0>
R/W-0
FSEL28<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN31: Filter 31 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL31<1:0>: Filter 31 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL31<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN30: Filter 30Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL30<1:0>: Filter 30Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL30<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001191F-page 468
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED)
bit 15
FLTEN29: Filter 29 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL29<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN28: Filter 28 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL28<1:0>: Filter 28 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL28<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 469
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-18: CiRXFn: CAN ACCEPTANCE FILTER N REGISTER 7 (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID<10:3>
R/W-x
R/W-x
R/W-x
SID<2:0>
U-0
R/W-0
U-0
—
EXID
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<17:16>
EID<15:8>
R/W-x
EID<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 SID<10:0>: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
bit 20
Unimplemented: Read as ‘0’
bit 19
EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
bit 18
Unimplemented: Read as ‘0’
bit 17-0
EID<17:0>: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Note:
This register can only be modified when the filter is disabled (FLTENn = 0).
DS60001191F-page 470
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0(1)
R-0(1)
CiFIFOBA<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CiFIFOBA<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CiFIFOBA<15:8>
R/W-0
CiFIFOBA<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
CiFIFOBA<31:0>: CAN FIFO Base Address bits
These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Note that bits <1:0> are
read-only and read ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1:
This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
 2013-2016 Microchip Technology Inc.
DS60001191F-page 471
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
S/HC-0
S/HC-0
U-0
U-0
FSIZE<4:0>(1)
R/W-0
DONLY
U-0
(1)
U-0
—
FRESET
UINC
—
—
—
—
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXEN
TXABAT(2)
TXLARB(3)
TXERR(3)
TXREQ
RTREN
TXPR<1:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 FSIZE<4:0>: FIFO Size bits(1)
11111 = FIFO is 32 messages deep
•
•
•
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 15
Unimplemented: Read as ‘0’
bit 14
FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll if this bit is clear before taking any action
0 = No effect
bit 13
UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12
DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)
This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 11-8
Unimplemented: Read as ‘0’
Note 1:
These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
This bit is updated when a message completes (or aborts) or when the FIFO is reset.
This bit is reset on any read of this register or when the FIFO is reset.
2:
3:
DS60001191F-page 472
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER (n = 0 THROUGH 31)
(CONTINUED)
bit 7
TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
bit 6
TXABAT: Message Aborted bit(2)
1 = Message was aborted
0 = Message completed successfully
bit 5
TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent
0 = Message did not loose arbitration while being sent
bit 4
TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO)
Setting this bit to ‘1’ requests sending a message.
The bit will automatically clear when all the messages queued in the FIFO are successfully sent
Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a Receive FIFO)
This bit has no effect.
bit 2
RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0
TXPR<1:0>: Message Transmit Priority bits
11 = Highest Message Priority
10 = High Intermediate Message Priority
01 = Low Intermediate Message Priority
00 = Lowest Message Priority
Note 1:
These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
This bit is updated when a message completes (or aborts) or when the FIFO is reset.
This bit is reset on any read of this register or when the FIFO is reset.
2:
3:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 473
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER (n = 0 THROUGH 31)
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
TXNFULLIE
TXHALFIE
TXEMPTYIE
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RXOVFLIE
RXFULLIE
RXHALFIE
RXNEMPTYIE
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
TXNFULLIF(1)
TXHALFIF
TXEMPTYIF(1)
U-0
U-0
U-0
U-0
R/W-0
R-0
R-0
R-0
—
—
—
—
(1)
RXOVFLIF RXFULLIF
(1)
RXHALFIF
RXNEMPTYIF(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25
TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24
TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19
RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18
RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17
RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16
RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10
TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
Note 1:
This bit is read-only and reflects the status of the FIFO.
DS60001191F-page 474
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER (n = 0 THROUGH 31)
(CONTINUED)
bit 9
TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is  half full
0 = FIFO is > half full
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
bit 8
TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
bit 7-4
Unimplemented: Read as ‘0’
bit 3
RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2
RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1
RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is half full
0 = FIFO is < half full
bit 0
RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
Note 1:
This bit is read-only and reflects the status of the FIFO.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 475
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 29-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-0(1)
R-0(1)
CiFIFOUAn<31:24>
R-x
R-x
R-x
R-x
R-x
R-x
CiFIFOUAn<15:8>
R-x
R-x
R-x
R-x
R-x
CiFIFOUAn<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R-x
CiFIFOUAn<23:16>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CiFIFOUAn<31:0>: CAN FIFO User Address bits
TXEN = 1: (FIFO configured as a Transmit Buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0: (FIFO configured as a Receive Buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1:
Note:
This bit will always read ‘0’, which forces byte-alignment of messages.
This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when
the module is not in Configuration mode.
REGISTER 29-23: CiFIFOCIn: CAN MODULE MESSAGE INDEX REGISTER (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
CiFIFOCIn<4:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0
CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits
TXEN = 1: (FIFO configured as a Transmit Buffer)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0: (FIFO configured as a Receive Buffer)
A read of this register will return an index to the message that the FIFO will use to save the next message.
DS60001191F-page 476
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
30.0
ETHERNET CONTROLLER
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” (DS60001155), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Key features of the Ethernet Controller include:
FIGURE 30-1:
Figure 30-1 illustrates a block diagram of the Ethernet
controller.
Note:
Supports 10/100 Mbps data transfer rates
Supports full-duplex and half-duplex operation
Supports RMII and MII PHY interface
Supports MIIM PHY management interface
To avoid cache coherency problems on
devices with L1 cache, Ethernet buffers
must only be allocated or accessed from
the KSEG1 segment.
ETHERNET CONTROLLER BLOCK DIAGRAM
TX
FIFO
•
•
•
•
• Supports both manual and automatic Flow Control
• RAM descriptor-based DMA operation for both
receive and transmit path
• Fully configurable interrupts
• Configurable receive packet filtering
- CRC check
- 64-byte pattern match
- Broadcast, multi-cast and uni-cast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
• Supports packet payload checksum calculation
• Supports various hardware statistics counters
TX DMA
TX BM
TX Bus
Master
TX Function
System Bus
TX Flow Control
RX DMA
RX
FIFO
MII/RMII
IF
RX Flow
Control
RX BM
External
PHY
MAC
RX Bus
Master
RX Filter
RX Function
Fast Peripheral Bus
Checksum
DMA
Control
Registers
Ethernet DMA
MIIM
IF
MAC Control
and
Configuration
Registers
Host IF
Ethernet Controller
 2013-2016 Microchip Technology Inc.
PBCLK5
DS60001191F-page 477
PIC32MZ Embedded Connectivity (EC) Family
Table 30-1, Table 30-2, Table 30-3 and Table 30-4
show four interfaces and the associated pins that can
be used with the Ethernet Controller.
TABLE 30-1:
MII MODE DEFAULT
INTERFACE SIGNALS 
(FMIIEN = 1, FETHIO = 1)
Pin Name
Description
TABLE 30-3:
Pin Name
AEMDC
MII MODE ALTERNATE
INTERFACE SIGNALS 
(FMIIEN = 1, FETHIO = 0)
Description
Management Clock
AEMDIO
Management I/O
AETXCLK
Transmit Clock
Management Clock
AETXEN
Transmit Enable
EMDIO
Management I/O
AETXD0
Transmit Data
ETXCLK
Transmit Clock
AETXD1
Transmit Data
ETXEN
Transmit Enable
AETXD2
Transmit Data
ETXD0
Transmit Data
AETXD3
Transmit Data
ETXD1
Transmit Data
AETXERR
Transmit Error
ETXD2
Transmit Data
AERXCLK
Receive Clock
ETXD3
Transmit Data
AERXDV
Receive Data Valid
ETXERR
Transmit Error
AERXD0
Receive Data
ERXCLK
Receive Clock
AERXD1
Receive Data
ERXDV
Receive Data Valid
AERXD2
Receive Data
ERXD0
Receive Data
AERXD3
Receive Data
ERXD1
Receive Data
AERXERR
Receive Error
ERXD2
Receive Data
AECRS
Carrier Sense
ERXD3
Receive Data
AECOL
Collision Indication
ERXERR
Receive Error
ECRS
Carrier Sense
ECOL
Collision Indication
EMDC
TABLE 30-2:
RMII MODE DEFAULT
INTERFACE SIGNALS 
(FMIIEN = 0, FETHIO = 1)
Pin Name
EMDC
Description
Management Clock
EMDIO
Management I/O
ETXEN
Transmit Enable
ETXD0
Transmit Data
ETXD1
Transmit Data
EREFCLK
Reference Clock
ECRSDV
Carrier Sense – Receive Data Valid
ERXD0
Receive Data
ERXD1
Receive Data
ERXERR
Receive Error
Note:
Note:
The MII mode Alternate Interface is not
available on 64-pin devices.
TABLE 30-4:
Pin Name
RMII MODE ALTERNATE
INTERFACE SIGNALS 
(FMIIEN = 0, FETHIO = 0)
Description
AEMDC
Management Clock
AEMDIO
Management I/O
AETXEN
Transmit Enable
AETXD0
Transmit Data
AETXD1
Transmit Data
AEREFCLK
Reference Clock
AECRSDV
Carrier Sense – Receive Data Valid
AERXD0
Receive Data
AERXD1
Receive Data
AERXERR
Receive Error
Ethernet controller pins that are not used
by a selected interface can be used by
other peripherals.
DS60001191F-page 478
 2013-2016 Microchip Technology Inc.
Ethernet Control Registers
Virtual Address
(BF88_#)
Register
Name(1)
TABLE 30-5:
2000
ETHCON1
2010
ETHCON2
2020
ETHTXST
2030
ETHRXST
2040
ETHHT0
2050
ETHHT1
2060
ETHPMM0
2070
ETHPMM1
2080
ETHPMCS
2090
ETHPMO
ETHERNET CONTROLLER REGISTER SUMMARY
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
15:0
ON
—
SIDL
—
—
—
TXRTS
RXEN
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
20A0
ETHRXFC
20/4
19/3
18/2
17/1
16/0
AUTOFC
—
—
MANFC
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
—
—
—
0000
BUFCDEC 0000
TXSTADDR<31:16>
0000
TXSTADDR<15:2>
31:16
RXSTADDR<31:16>
15:0
31:16
0000
0000
HT<63:32>
15:0
31:16
0000
0000
PMM<31:0>
15:0
31:16
0000
0000
PMM<63:32>
15:0
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CRC
ERREN
CRC
OKEN
RUNT
ERREN
UCEN
NOT
MEEN
MCEN
BCEN
0000
PMCS<15:0>
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
15:0
HTEN
MPEN
—
NOTPM
31:16
—
—
—
—
—
—
—
—
RXFWM<7:0>
15:0
—
—
—
—
—
—
—
—
RXEWM<7:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TX
BUSEIE
RX
BUSEIE
—
—
—
EW
MARKIE
FW
MARKIE
RX
DONEIE
PK
TPENDIE
RX
ACTIE
—
TX
DONEIE
TX
ABORTIE
RX
BUFNAIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BUSY
TXBUSY
RXBUSY
—
—
—
—
—
0000
31:16
ETH
2100
RXOVFLOW 15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
20B0 ETHRXWM
DS60001191F-page 479
20C0
ETHIEN
20D0
ETHIRQ
20E0
ETHSTAT
Legend:
Note
PMMODE<3:0>
0000
0000
PMO<15:0>
—
0000
0000
HT<31:0>
15:0
0000
0000
RXSTADDR<15:2>
31:16
31:16
21/5
RXBUFSZ<6:0>
15:0
31:16
22/6
PTV<15:0>
31:16
31:16
23/7
All Resets
Bit Range
Bits
RUNTEN
0000
0000
—
—
0000
RXOVFLW 0000
BUFCNT<7:0>
RXOVFLWCNT<15:0>
0000
RX
0000
OVFLWIE
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
30.1
Virtual Address
(BF88_#)
ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
2110
31:16
ETH
FRMTXOK 15:0
—
2120
31:16
ETH
SCOLFRM 15:0
—
2130
31:16
ETH
MCOLFRM 15:0
—
2140
31:16
ETH
FRMRXOK 15:0
—
31:16
—
2150
2160
ETH
FCSERR
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXPAUSE
PASSALL
—
—
FRMTXOKCNT<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
BP
NOBKOFF
CRC
ENABLE
—
ALGNERRCNT<15:0>
 2013-2016 Microchip Technology Inc.
EMAC1
CFG1
2210
EMAC1
CFG2
15:0
—
EXCESS
DFR
NOBKOFF
—
—
LONGPRE
PUREPRE
AUTOPAD
VLANPAD
PAD
ENABLE
2220
EMAC1
IPGT
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
2230
EMAC1
IPGR
31:16
—
—
—
—
—
—
—
—
—
15:0
—
2240
EMAC1
CLRT
31:16
—
—
15:0
—
—
2250
EMAC1
MAXF
31:16
—
—
2260
EMAC1
SUPP
2270
EMAC1
TEST
2280
EMAC1
MCFG
2290
22A0
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
—
—
—
—
—
—
—
—
—
—
—
NB2BIPKTGP2<6:0>
—
0000
0012
0000
0C12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RETX<3:0>
0000
370F
MACMAXF<15:0>
—
0000
RXENABLE 800D
B2BIPKTGP<6:0>
—
CWINDOW<5:0>
—
LOOPBACK TXPAUSE
0000
05EE
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
RESET
RMII
—
—
SPEED
RMII
—
—
—
—
—
—
—
—
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
TESTBP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
RESET
MGMT
—
—
—
—
—
—
—
—
—
EMAC1
MCMD
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
READ
0000
EMAC1
MADR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
Legend:
Note
—
0000
0000
2200
—
0000
0000
31:16
ETH
ALGNERR 15:0
NB2BIPKTGP1<6:0>
0000
0000
FCSERRCNT<15:0>
—
0000
0000
FRMRXOKCNT<15:0>
—
0000
0000
MCOLFRMCNT<15:0>
—
0000
0000
SCOLFRMCNT<15:0>
—
All Resets
Bit Range
Register
Name(1)
Bits
PHYADDR<4:0>
TESTPAUSE SHRTQNTA 0000
CLKSEL<3:0>
—
NOPRE
REGADDR<4:0>
—
0000
SCANINC 0020
0100
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 480
TABLE 30-5:
Virtual Address
(BF88_#)
Register
Name(1)
Bit Range
ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED)
22B0
EMAC1
MWTD
31:16
22C0
EMAC1
MRDD
31:16
22D0
EMAC1
MIND
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
LINKFAIL
NOTVALID
SCAN
2300
EMAC1
SA0(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2310
EMAC1
SA1(2)
31:16
—
—
—
2320
EMAC1
SA2(2)
31:16
—
—
—
Legend:
Note
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
MWTD<15:0>
—
—
—
—
—
—
—
15:0
—
—
—
15:0
—
—
—
—
—
—
—
STNADDR4<7:0>
—
—
—
—
—
—
—
—
STNADDR2<7:0>
—
—
—
—
—
—
STNADDR1<7:0>
xxxx
xxxx
STNADDR3<7:0>
—
0000
MIIMBUSY 0000
STNADDR5<7:0>
—
0000
0000
STNADDR6<7:0>
—
0000
0000
MRDD<15:0>
15:0
15:0
—
All Resets
Bits
xxxx
xxxx
xxxx
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
Reset values default to the factory programmed value.
DS60001191F-page 481
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 30-5:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-1:
Bit Range
31:24
23:16
15:8
7:0
ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1
Bit
31/23/15/7
R/W-0
Bit
Bit
30/22/14/6 29/21/13/5
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTV<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ON
—
SIDL
—
—
—
TXRTS
RXEN(1)
R/W-0
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
AUTOFC
—
—
MANFC
—
—
—
BUFCDEC
PTV<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
x = Bit is unknown
PTV<15:0>: PAUSE Timer Value bits
PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1<8>) is not set.
These bits are only used for Flow Control operations.
bit 15
ON: Ethernet ON bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode
0 = Ethernet module transfers continue during Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’, it will clear to a ‘0’ whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmit
logic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8
RXEN: Receive Enable bit(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter 
configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.
Note 1:
It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
DS60001191F-page 482
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-1:
bit 7
ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control enabled
0 = Automatic Flow Control disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to
automatically enable and disable the Flow Control, respectively. When the number of received buffers
BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled. When
the BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 6-5
Unimplemented: Read as ‘0’
bit 4
MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled
0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame
using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *
PTV<15:0>/2 TX clock cycles until the bit is cleared.
Note:
For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at
25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000
PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 3-1
Unimplemented: Read as ‘0’
bit 0
BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as ‘0’. When written with a ‘1’, the Descriptor Buffer Counter,
BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bit
is written, the BUFCNT value will remain unchanged. Writing a ‘0’ will have no effect.
This bit is only used for RX operations.
Note 1:
It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 483
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-2:
Bit Range
Bit
31/23/15/7
31:24
23:16
15:8
7:0
ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
RXBUFSZ<3:0>
RXBUFSZ<6:4>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11
Unimplemented: Read as ‘0’
bit 10-4
RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes
•
•
•
1100000 = RX data Buffer size for descriptors is 1536 bytes
•
•
•
0000011 = RX data Buffer size for descriptors is 48 bytes
0000010 = RX data Buffer size for descriptors is 32 bytes
0000001 = RX data Buffer size for descriptors is 16 bytes
0000000 = Reserved
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
DS60001191F-page 484
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-3:
Bit
Range
31:24
23:16
15:8
7:0
ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
TXSTADDR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR<7:2>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 TXSTADDR<31:2>: Starting Address of First Transmit Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for TX operations.
This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
REGISTER 30-4:
Bit
Range
31:24
23:16
15:8
7:0
ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
RXSTADDR<31:24>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR<23:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR<7:2>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for RX operations.
This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 485
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-5:
Bit
Range
ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
HT<31:24>
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
HT<23:16>
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT<15:8>
7:0
R/W-0
HT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
HT<31:0>: Hash Table Bytes 0-3 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.
REGISTER 30-6:
Bit Range
31:24
23:16
15:8
7:0
x = Bit is unknown
ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT<63:56>
R/W-0
HT<55:48>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT<47:40>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT<39:32>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
x = Bit is unknown
HT<63:32>: Hash Table Bytes 4-7 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.
DS60001191F-page 486
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-7:
Bit Range
31:24
ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM<31:24>
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 31-24
bit 23-16
bit 15-8
bit 7-0
Note 1:
2:
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER
Bit
24/16/8/0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM<63:56>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM<55:48>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM<47:40>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM<39:32>
Legend:
R = Readable bit
-n = Value at POR
bit 31-24
bit 23-16
bit 15-8
bit 7-0
R/W-0
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.
Bit Range
7:0
R/W-0
PMM<31:24>: Pattern Match Mask 3 bits
PMM<23:16>: Pattern Match Mask 2 bits
PMM<15:8>: Pattern Match Mask 1 bits
PMM<7:0>: Pattern Match Mask 0 bits
REGISTER 30-8:
15:8
R/W-0
PMM<7:0>
Legend:
R = Readable bit
-n = Value at POR
23:16
R/W-0
PMM<15:8>
7:0
31:24
R/W-0
PMM<23:16>
15:8
Note 1:
2:
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PMM<63:56>: Pattern Match Mask 7 bits
PMM<55:48>: Pattern Match Mask 6 bits
PMM<47:40>: Pattern Match Mask 5 bits
PMM<39:32>: Pattern Match Mask 4 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 487
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-9:
Bit Range
31:24
23:16
15:8
7:0
ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM
REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Note 1:
2:
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMCS<15:8>
R/W-0
PMCS<7:0>
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-8
bit 7-0
Bit
24/16/8/0
Bit
31/23/15/7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMCS<15:8>: Pattern Match Checksum 1 bits
PMCS<7:0>: Pattern Match Checksum 0 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.
REGISTER 30-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMO<15:8>
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
Note 1:
2:
R/W-0
PMO<7:0>
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMO<15:0>: Pattern Match Offset 1 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.
DS60001191F-page 488
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
Bit
25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HTEN
MPEN
—
NOTPM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CRCERREN
CRCOKEN
RUNTERREN
RUNTEN
UCEN
NOTMEEN
MCEN
BCEN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
PMMODE<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
HTEN: Enable Hash Table Filtering bit
1 = Enable Hash Table Filtering
0 = Disable Hash Table Filtering
bit 14
MPEN: Magic Packet™ Enable bit
1 = Enable Magic Packet Filtering
0 = Disable Magic Packet Filtering
bit 13
Unimplemented: Read as ‘0’
bit 12
NOTPM: Pattern Match Inversion bit
1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur
0 = The Pattern Match Checksum must match for a successful Pattern Match to occur
This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match
to occur.
bit 11-8 PMMODE<3:0>: Pattern Match Mode bits
1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND 
(Packet = Magic Packet)(1,3)
1000 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND 
(Hash Table Filter match)(1,2)
0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND 
(Destination Address = Broadcast Address)(1)
0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND 
(Destination Address = Unicast Address)(1)
0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND 
(Destination Address = Unicast Address)(1)
0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND 
(Destination Address = Station Address)(1)
0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful
Note 1:
2:
3:
XOR = True when either one or the other conditions are true, but not both.
This Hash Table Filter match is active regardless of the value of the HTEN bit.
This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 489
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER (CONTINUED)
bit 7
bit 6
bit 5
bit 4
CRCERREN: CRC Error Collection Enable bit
1 = The received packet CRC must be invalid for the packet to be accepted
0 = Disable CRC Error Collection filtering
This bit allows the user to collect all packets that have an invalid CRC.
CRCOKEN: CRC OK Enable bit
1 = The received packet CRC must be valid for the packet to be accepted
0 = Disable CRC filtering
This bit allows the user to reject all packets that have an invalid CRC.
RUNTERREN: Runt Error Collection Enable bit
1 = The received packet must be a runt packet for the packet to be accepted
0 = Disable Runt Error Collection filtering
This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as
any packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than
64 bytes that has a valid CRC (when CRCOKEN = 1).
RUNTEN: Runt Enable bit
1 = The received packet must not be a runt packet for the packet to be accepted
0 = Disable Runt filtering
bit 3
This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a
size of less than 64 bytes.
UCEN: Unicast Enable bit
1 = Enable Unicast Filtering
0 = Disable Unicast Filtering
bit 2
This bit allows the user to accept all unicast packets whose Destination Address matches the Station
Address.
NOTMEEN: Not Me Unicast Enable bit
1 = Enable Not Me Unicast Filtering
0 = Disable Not Me Unicast Filtering
bit 1
This bit allows the user to accept all unicast packets whose Destination Address does not match the Station
Address.
MCEN: Multicast Enable bit
1 = Enable Multicast Filtering
0 = Disable Multicast Filtering
bit 0
This bit allows the user to accept all Multicast Address packets.
BCEN: Broadcast Enable bit
1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
This bit allows the user to accept all Broadcast Address packets.
Note 1:
2:
3:
XOR = True when either one or the other conditions are true, but not both.
This Hash Table Filter match is active regardless of the value of the HTEN bit.
This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
DS60001191F-page 490
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
31:24
23:16
RXFWM<7:0>
U-0
15:8
7:0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXEWM<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-24
Unimplemented: Read as ‘0’
bit 23-16
RXFWM<7:0>: Receive Full Watermark bits
x = Bit is unknown
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to
determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when
automatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the Empty
Watermark Pointer.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
RXEWM<7:0>: Receive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to
determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when
automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full
Watermark Pointer.
Note:
This register is only used for RX operations.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 491
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
—
R/W-0
TXBUSEIE(1) RXBUSEIE(2)
R/W-0
R/W-0
RXDONEIE(2) PKTPENDIE(2) RXACTIE(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U-0
—
EWMARKIE(2) FWMARKIE(2)
R/W-0
R/W-0
TXDONEIE(1) TXABORTIE(1) RXBUFNAIE(2) RXOVFLWIE(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13
RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 12-10 Unimplemented: Read as ‘0’
bit 9
EWMARKIE: Empty Watermark Interrupt Enable bit(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Interrupt
bit 8
FWMARKIE: Full Watermark Interrupt Enable bit(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7
RXDONEIE: Receiver Done Interrupt Enable bit(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6
PKTPENDIE: Packet Pending Interrupt Enable bit(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5
RXACTIE: RX Activity Interrupt Enable bit
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 4
Unimplemented: Read as ‘0’
bit 3
TXDONEIE: Transmitter Done Interrupt Enable bit(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2
TXABORTIE: Transmitter Abort Interrupt Enable bit(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1
RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0
RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt
Note 1:
2:
This bit is only used for TX operations.
This bit is only used for RX operations.
DS60001191F-page 492
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
R/W-0
—
TXBUSE(1)
31:24
23:16
15:8
7:0
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
RXBUSE(2)
—
—
—
EWMARK(2)
FWMARK(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
RXDONE(2)
PKTPEND(2)
RXACT(2)
—
TXDONE(1)
TXABORT(1)
RXBUFNA(2) RXOVFLW(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-15
Unimplemented: Read as ‘0’
bit 14
TXBUSE: Transmit BVCI Bus Error Interrupt bit(1)
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
x = Bit is unknown
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 13
RXBUSE: Receive BVCI Bus Error Interrupt bit(2)
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10
Unimplemented: Read as ‘0’
bit 9
EWMARK: Empty Watermark Interrupt bit(2)
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>)
being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8
FWMARK: Full Watermark Interrupt bit(2)
1 = Full Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement the
BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
Note 1:
2:
Note:
This bit is only used for TX operations.
This bit is only used for RX operations.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 493
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
(CONTINUED)
bit 7
RXDONE: Receive Done Interrupt bit(2)
1 = RX packet was successfully received
0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU write
of a ‘1’ to the CLR register.
bit 6
PKTPEND: Packet Pending Interrupt bit(2)
1 = RX packet pending in memory
0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by
writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 5
RXACT: Receive Activity Interrupt bit(2)
1 = RX packet data was successfully received
0 = No interrupt pending
This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset or
CPU write of a ‘1’ to the CLR register.
bit 4
Unimplemented: Read as ‘0’
bit 3
TXDONE: Transmit Done Interrupt bit(1)
1 = TX packet was successfully sent
0 = No interrupt pending
This bit is set when the currently transmitted TX packet completes transmission, and the Transmit Status
Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write
of a ‘1’ to the CLR register.
bit 2
TXABORT: Transmit Abort Condition Interrupt bit(1)
1 = TX abort condition occurred on the last TX packet
0 = No interrupt pending
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
•
•
•
•
•
Jumbo TX packet abort
Underrun abort
Excessive defer abort
Late collision abort
Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
bit 1
RXBUFNA: Receive Buffer Not Available Interrupt bit(2)
1 = RX Buffer Descriptor Not Available condition has occurred
0 = No interrupt pending
This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU write
of a ‘1’ to the CLR register.
bit 0
RXOVFLW: Receive FIFO Over Flow Error bit(2)
1 = RX FIFO Overflow Error condition has occurred
0 = No interrupt pending
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset
or CPU write of a ‘1’ to the CLR register.
Note 1:
2:
Note:
This bit is only used for TX operations.
This bit is only used for RX operations.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
DS60001191F-page 494
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
BUFCNT<7:0>(1)
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
ETHBUSY(4,5) TXBUSY(2,6) RXBUSY(3,6)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits(1)
Number of packet buffers received in memory. Once a packet has been successfully received, this register
is incremented by hardware based on the number of descriptors used by the packet. Software decrements
the counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet has
been read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to increment
the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)
when software tries to decrement the register and the register is already at 0x0000. When software attempts
to decrement the counter at the same time that the hardware attempts to increment the counter, the counter
value will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)
awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at
a value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,
depending on the value of the ETHIEN bit <PKTPENDIE> register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note:
BUFCNT will not be cleared when ON is set to ‘0’. This enables software to continue to utilize
and decrement this count.
bit 15-8
Unimplemented: Read as ‘0’
bit 7
ETHBUSY: Ethernet Module busy bit(4,5)
1 = Ethernet logic has been turned on (ON (ETHCON1<15>) = 1) or is completing a transaction
0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is completing a transaction after being turned off.
Note 1:
2:
3:
4:
5:
6:
This bit is only used for RX operations.
This bit is only affected by TX operations.
This bit is only affected by RX operations.
This bit is affected by TX and RX operations.
This bit will be set when the ON bit (ETHCON1<15>) = 1.
This bit will be cleared when the ON bit (ETHCON1<15>) = 0.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 495
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
bit 6
TXBUSY: Transmit Busy bit(2,6)
1 = TX logic is receiving data
0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily
reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
bit 5
RXBUSY: Receive Busy bit(3,6)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
6:
This bit is only used for RX operations.
This bit is only affected by TX operations.
This bit is only affected by RX operations.
This bit is affected by TX and RX operations.
This bit will be set when the ON bit (ETHCON1<15>) = 1.
This bit will be cleared when the ON bit (ETHCON1<15>) = 0.
DS60001191F-page 496
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS
REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
RXOVFLWCNT<15:8>
R/W-0
R/W-0
RXOVFLWCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive
error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ<0>) interrupt flag.
Note 1:
2:
3:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 497
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMTXOKCNT<15:8>
R/W-0
R/W-0
FRMTXOKCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits
Increment counter for frames successfully transmitted.
Note 1:
2:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
DS60001191F-page 498
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES
STATISTICS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
SCOLFRMCNT<15:8>
R/W-0
R/W-0
SCOLFRMCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
SCOLFRMCNT<15:0>: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.
Note 1:
2:
3:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 499
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
24/16/8/0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MCOLFRMCNT<15:8>
R/W-0
R/W-0
MCOLFRMCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.
Note 1:
2:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
DS60001191F-page 500
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMRXOKCNT<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMRXOKCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
FRMRXOKCNT<15:0>: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented if
there is a Frame Check Sequence (FCS) or Alignment error.
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 501
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FCSERRCNT<15:8>
R/W-0
R/W-0
FCSERRCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
FCSERRCNT<15:0>: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of
8 bits.
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
3:
DS60001191F-page 502
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS
REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALGNERRCNT<15:8>
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
ALGNERRCNT<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
ALGNERRCNT<15:0>: Alignment Error Count bits
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS
error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
3:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 503
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
LOOPBACK
TX
PAUSE
RX
PAUSE
PASSALL
RX
ENABLE
—
Legend:
R = Readable bit
-n = Value at POR
—
—
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is ‘1’.
bit 14
SIMRESET: Simulation Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 13-12 Unimplemented: Read as ‘0’
bit 11
RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10
RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9
RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8
RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 7-5
Unimplemented: Read as ‘0’
bit 4
LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface
0 = MAC normal operation
bit 3
TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted
0 = PAUSE Flow Control frames are blocked
bit 2
RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames
0 = Received PAUSE Flow Control frames are ignored
bit 1
PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)
0 = The received Control frames are ignored
bit 0
RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames
0 = Disable the MAC receiving of frames
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
DS60001191F-page 504
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
25/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
EXCESS
DFR
BPNOBK
OFF
NOBK
OFF
—
—
LONGPRE
PUREPRE
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
AUTO
PAD(1,2)
VLAN
PAD(1,2)
PAD
ENABLE(1,3)
CRC
ENABLE
DELAYCRC HUGEFRM LENGTHCK FULLDPLX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard
0 = The MAC will abort when the excessive deferral limit is reached
bit 13
BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit without
backoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12
NOBKOFF: No Backoff bit
1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Backoff algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
bit 9
LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
0 = The MAC allows any length preamble as per the Standard
bit 8
PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with
errors in its preamble is discarded
0 = The MAC does not perform any preamble checking
bit 7
AUTOPAD: Automatic Detect Pad Enable bit(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two
octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection
Note 1:
2:
3:
Note:
Table 30-6 provides a description of the pad function based on the configuration of this register.
This bit is ignored if the PADENABLE bit is cleared.
This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware
 2013-2016 Microchip Technology Inc.
DS60001191F-page 505
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
(CONTINUED)
bit 6
VLANPAD: VLAN Pad Enable bit(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC
0 = The MAC does not perform padding of short frames
bit 5
PADENABLE: Pad/CRC Enable bit(1,3)
1 = The MAC will pad all short frames
0 = The frames presented to the MAC have a valid length
bit 4
CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the
PADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3
DELAYCRC: Delayed CRC bit
This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the
IEEE 802.3 frames.
1 = Four bytes of header (ignored by the CRC function)
0 = No proprietary header
bit 2
HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received
0 = Huge frames are not allowed for receive or transmit
bit 1
LENGTHCK: Frame Length checking bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported on the transmit/receive
statistics vector.
0 = Length/Type field check is not performed
bit 0
FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode
0 = The MAC operates in Half-Duplex mode
Note 1:
2:
3:
Note:
Table 30-6 provides a description of the pad function based on the configuration of this register.
This bit is ignored if the PADENABLE bit is cleared.
This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware
TABLE 30-6:
PAD OPERATION
Type
AUTOPAD
VLANPAD
PADENABLE
Any
x
x
0
No pad, check CRC
Any
0
0
1
Pad to 60 Bytes, append CRC
Any
x
1
1
Pad to 64 Bytes, append CRC
Any
1
0
1
If untagged: Pad to 60 Bytes, append CRC
If VLAN tagged: Pad to 64 Bytes, append CRC
DS60001191F-page 506
Action
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET
GAP REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
—
B2BIPKTGP<6:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-7
Unimplemented: Read as ‘0’
bit 6-0
B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between
the end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register value
should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which
represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps). In Half-Duplex mode, the
recommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 µs (in 100 Mbps) or
9.6 µs (in 10 Mbps).
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 507
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK
INTERPACKET GAP REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
—
U-0
NB2BIPKTGP1<6:0>
—
R/W-0
NB2BIPKTGP2<6:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15
Unimplemented: Read as ‘0’
bit 14-8
NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section
4.2.3.2.1 “Deference” of the IEEE 80.23 Specification. If carrier is detected during the timing of IPGR1, the
MAC defers to carrier. If, however, carrier becomes after IPGR1, the MAC continues timing IPGR2 and
transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to
IPGR2. Its recommend value is 0xC (12d).
bit 7
Unimplemented: Read as ‘0’
bit 6-0
NB2BIPKTGP2<6:0>: Non-Back-to-Back Interpacket Gap Part 2 bits
This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value
is 0x12 (18d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps).
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
DS60001191F-page 508
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY
LIMIT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-1
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U-0
U-0
U-0
U-0
CWINDOW<5:0>
—
—
—
—
R/W-1
R/W-1
RETX<3:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8
CWINDOW<5:0>: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur in
properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of
the window.
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RETX<3:0>: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision before
aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts
(attemptLimit) to be 0xF (15d). Its default is ‘0xF’.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 509
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
MACMAXF<15:8>(1)
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
MACMAXF<7:0>(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
MACMAXF<15:0>: Maximum Frame Length bits(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged
maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If
a shorter/longer maximum length restriction is desired, program this 16-bit field.
Note 1:
If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers
are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN
tagged frame plus the 4-byte header.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
DS60001191F-page 510
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
Bit
26/18/10/2 25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
—
—
—
—
RESETRMII(1)
—
—
SPEEDRMII(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-12
Unimplemented: Read as ‘0’
bit 11
RESETRMII: Reset RMII Logic bit(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPEEDRMII: RMII Speed bit(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
Note:
x = Bit is unknown
This bit is only used for the RMII module.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 511
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
TESTBP
TESTPAUSE(1) SHRTQNTA(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2
TESTBP: Test Backpressure bit
1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during backpressure.
0 = Normal operation
bit 1
TESTPAUSE: Test PAUSE bit(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a
non-zero pause time parameter was received
0 = Normal operation
bit 0
SHRTQNTA: Shortcut PAUSE Quanta bit(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time
0 = Normal operation
Note 1:
Note:
This bit is only used for testing purposes.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
DS60001191F-page 512
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT
CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
U-0
31:24
23:16
15:8
Bit
Bit
30/22/14/6 29/21/13/5
U-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RESETMGMT
—
—
—
—
—
—
—
U-0
U-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
NOPRE
SCANINC
7:0
Legend:
R = Readable bit
-n = Value at POR
CLKSEL<3:0>(1)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2
CLKSEL<3:0>: MII Management Clock Select 1 bits(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1
NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppressed preamble
0 = Normal read/write cycles are performed
bit 0
SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start
from address 1 through the value set in EMAC1MADR<PHYADDR>
0 = Continuous reads of the same PHY
Note 1:
Note:
Table 30-7 provides a description of the clock divider encoding.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
TABLE 30-7:
MIIM CLOCK SELECTION
MIIM Clock Select
EMAC1MCFG<5:2>
TPBCLK5 divided by 4
TPBCLK5 divided by 6
TPBCLK5 divided by 8
TPBCLK5 divided by 10
TPBCLK5 divided by 14
TPBCLK5 divided by 20
TPBCLK5 divided by 28
TPBCLK5 divided by 40
TPBCLK5 divided by 48
TPBCLK5 divided by 50
Undefined
000x
0010
0011
0100
0101
0110
0111
1000
1001
1010
Any other combination
 2013-2016 Microchip Technology Inc.
DS60001191F-page 513
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SCAN
READ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2
Unimplemented: Read as ‘0’
bit 1
SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring
the Link Fail)
0 = Normal Operation
bit 0
READ: MII Management Read Command bit
1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register
0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD
register
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
DS60001191F-page 514
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PHYADDR<4:0>
R/W-0
REGADDR<4:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ’0’
bit 12-8
PHYADDR<4:0>: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed
(0 is reserved).
bit 7-5
Unimplemented: Read as ’0’
bit 4-0
REGADDR<4:0>: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 515
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE
DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MWTD<15:8>
R/W-0
R/W-0
MWTD<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ’0’
bit 15-0
MWTD<15:0>: MII Management Write Data bits
When written, a MII Management write cycle is performed using the 16-bit data and the preconfigured PHY
and Register addresses from the EMAC1MADR register.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
REGISTER 30-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MRDD<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MRDD<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
Note:
MRDD<15:0>: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
DS60001191F-page 516
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
LINKFAIL
NOTVALID
SCAN
MIIMBUSY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
LINKFAIL: Link Fail bit
When ‘1’ is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY status
register.
bit 2
NOTVALID: MII Management Read Data Not Valid bit
When ‘1’ is returned - indicates an MII management read cycle has not completed and the Read Data is not
yet valid.
bit 1
SCAN: MII Management Scanning bit
When ‘1’ is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress.
bit 0
MIIMBUSY: MII Management Busy bit
When ‘1’ is returned - indicates MII Management module is currently performing an MII Management Read
or Write cycle.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 517
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR6<7:0>
R/W-P
R/W-P
STNADDR5<7:0>
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
STNADDR6<7:0>: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
bit 7-0
STNADDR5<7:0>: Station Address Octet 5 bits
These bits hold the fifth transmitted octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
DS60001191F-page 518
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR4<7:0>
R/W-P
R/W-P
STNADDR3<7:0>
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
STNADDR4<7:0>: Station Address Octet 4 bits
These bits hold the fourth transmitted octet of the station address.
bit 7-0
STNADDR3<7:0>: Station Address Octet 3 bits
These bits hold the third transmitted octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
 2013-2016 Microchip Technology Inc.
DS60001191F-page 519
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 30-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR2<7:0>
R/W-P
R/W-P
STNADDR1<7:0>
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Reserved: Maintain as ‘0’; ignore read
bit 15-8
STNADDR2<7:0>: Station Address Octet 2 bits
These bits hold the second transmitted octet of the station address.
bit 7-0
STNADDR1<7:0>: Station Address Octet 1 bits
These bits hold the most significant (first transmitted) octet of the station address.
Note 1:
2:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
DS60001191F-page 520
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
31.0
COMPARATOR
Note:
The Analog Comparator module consists of two
comparators that can be configured in a variety of
ways.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 19.
“Comparator” (DS60001110), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
Key features of the Analog Comparator module are:
•
•
•
•
Differential inputs
Rail-to-rail operation
Selectable output polarity
Selectable inputs:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
- Comparator voltage reference (CVREF)
• Selectable interrupt generation
A block diagram of the comparator module is illustrated
in Figure 31-1.
FIGURE 31-1:
COMPARATOR BLOCK DIAGRAM
CCH<1:0> (CM1CON<1:0>)
C1INB
C1INC
COE (CM1CON<14>)
C1IND
CMP1
CREF
(CM1CON<4>)
C1OUT
CPOL
(CM1CON<13>)
COUT (CM1CON<8>)
and Trigger to ADC
C1INA
D
Q
CCH<1:0> (CM2CON<1:0>)
C2INB
C1OUT
(CMSTAT<2>)
PBCLK3
C2INC
COE (CM2CON<14>)
C2IND
CMP2
CREF
(CM2CON<4>)
C2OUT
CPOL
(CM2CON<13>)
COUT (CM2CON<8>) and
Trigger to ADC
C2INA
CVREF(1)
Internal (1.2V)
Note 1:
D
Q
C2OUT
(CMSTAT<1>)
PBCLK3
Internally connected. See Section 32.0 “Comparator Voltage Reference (CVREF)” for more information.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 521
Comparator Control Registers
C000 CM1CON
C010 CM2CON
C060 CMSTAT
Legend:
Note 1:
COMPARATOR REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF84_#)
TABLE 31-1:
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
ON
—
COE
—
CPOL
—
—
—
—
—
—
—
—
—
COUT
—
EVPOL<1:0>
—
—
—
—
CREF
—
—
—
—
—
CCH<1:0>
—
—
00C3
0000
15:0
31:16
ON
—
COE
—
CPOL
—
—
—
—
—
—
—
—
—
COUT
—
EVPOL<1:0>
—
—
—
—
CREF
—
—
—
—
—
CCH<1:0>
—
—
00C3
0000
—
—
—
—
15:0
—
—
SIDL
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
C2OUT
C1OUT
0000
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 522
31.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 31-1:
Bit
Range
31:24
23:16
15:8
7:0
CMxCON: COMPARATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
R/W-0
R/W-0
ON
COE
R/W-1
R/W-1
EVPOL<1:0>
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
—
R/W-0
(1)
CPOL
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
COUT
—
—
—
—
U-0
R/W-0
U-0
U-0
R/W-1
—
CREF
—
—
W = Writable bit
‘1’ = Bit is set
R/W-1
CCH<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator ON bit
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
register
bit 14
COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
bit 13
CPOL: Comparator Output Inversion bit(1)
1 = Output is inverted
0 = Output is not inverted
bit 12-9 Unimplemented: Read as ‘0’
bit 8
COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
bit 7-6
EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXINA pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH<1:0>: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the CxIND pin
01 = Comparator inverting input is connected to the CxINC pin
00 = Comparator inverting input is connected to the CxINB pin
Note 1:
Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 523
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 31-2:
Bit
Range
31:24
23:16
15:8
7:0
CMSTAT: COMPARATOR STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
SIDL
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
C2OUT
C1OUT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in IDLE Control bit
1 = All Comparator modules are disabled in IDLE mode
0 = All Comparator modules continue to operate in the IDLE mode
bit 12-2
Unimplemented: Read as ‘0’
bit 1
C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a ‘1’
0 = Output of Comparator 2 is a ‘0’
bit 0
C1OUT: Comparator Output bit
1 = Output of Comparator 1 is a ‘1’
0 = Output of Comparator 1 is a ‘0’
DS60001191F-page 524
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
32.0
Note:
COMPARATOR VOLTAGE
REFERENCE (CVREF)
The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down
function to conserve power when the reference is not
being used. The module’s supply reference can be provided from either device VDD/VSS or an external
voltage reference. The CVREF output is available for
the comparators and typically available for pin output.
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 20. “Comparator
Voltage
Reference
(CVREF)”
(DS60001109), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
FIGURE 32-1:
VREF+
AVDD
A block diagram of the CVREF module is illustrated in
Figure 32-1.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSRC
8R
CVRSS = 0
CVR<3:0>
CVREF
R
CVREN
R
16-to-1 MUX
R
R
16 Steps
CVREFOUT
CVRCON<CVROE>
R
R
R
CVRR
VREFAVSS
 2013-2016 Microchip Technology Inc.
8R
CVRSS = 1
CVRSS = 0
DS60001191F-page 525
Comparator Voltage Reference Control Registers
Virtual Address
(BF80_#)
TABLE 32-1:
Legend:
1:
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
—
—
—
CVROE
15:0
ON
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CVRR
CVRSS
CVR<3:0>
All Resets
Register
Name(1)
Bit Range
Bits
0E00 CVRCON
Note
COMPARATOR VOLTAGE REFERENCE REGISTER MAP
0000
0000
The register in this table has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 526
32.1
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 32-1:
Bit
Range
31:24
23:16
15:8
7:0
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
ON
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
CVROE
CVRR
CVRSS
CVR<3:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator Voltage Reference On bit
1 = Module is enabled
Setting this bit does not affect other bits in the register.
0 = Module is disabled and does not consume current. 
Clearing this bit does not affect the other bits in the register.
bit 14-7
Unimplemented: Read as ‘0’
bit 6
CVROE: CVREFOUT Enable bit
1 = Voltage level is output on CVREFOUT pin
0 = Voltage level is disconnected from CVREFOUT pin
bit 5
CVRR: CVREF Range Selection bit
1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR<3:0>: CVREF Value Selection 0  CVR<3:0>  15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24)  (CVRSRC)
When CVRR = 0:
CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)
 2013-2016 Microchip Technology Inc.
DS60001191F-page 527
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 528
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
33.0
POWER-SAVING FEATURES
Sleep mode includes the following characteristics:
This section describes power-saving features for the
PIC32MZ EC devices. These devices offer various
methods and modes that allow the user to balance
power consumption with device performance. In all of
the methods and modes described in this section,
power-saving is controlled by software.
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit remains operative during Sleep
mode
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode
• Some peripherals can continue to operate at limited
functionality in Sleep mode. These peripherals
include I/O pins that detect a change in the input
signal, WDT, ADC, UART and peripherals that use
an external clock input or the internal LPRC
oscillator (e.g., RTCC, Timer1 and Input Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep
33.1
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
Note:
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 10. “PowerSaving Features” (DS60001130), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the speed of PBCLK7, or selecting a lower
power clock source (i.e., LPRC or SOSC).
In addition, the Peripheral Bus Scaling mode is available
for each peripheral bus where peripherals are clocked at
reduced speed by selecting a higher divider for the
associated PBCLKx, or by disabling the clock
completely.
33.2
Power-Saving with CPU Halted
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
33.2.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted and the associated clocks
are disabled. Select peripherals can continue to
operate in Sleep mode and can be used to wake the
device from Sleep. See the individual peripheral
module sections for descriptions of behavior in Sleep.
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
peripheral bus clocks will start running and the device
will enter into Idle mode.
33.2.2
IDLE MODE
In Idle mode, the CPU is Halted; however, all clocks are
still enabled. This allows peripherals to continue to
operate. Peripherals can be individually configured to
Halt when entering Idle by setting their respective SIDL
bit. Latency, when exiting Idle mode, is very low due to
the CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt source
is enabled. The priority of the interrupt event must
be greater than the current priority of the CPU. If the
priority of the interrupt event is lower than or equal
to current priority of the CPU, the CPU will remain
Halted and the device will remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
 2013-2016 Microchip Technology Inc.
DS60001191F-page 529
PIC32MZ Embedded Connectivity (EC) Family
33.3
Peripheral Module Disable
To disable a peripheral, the associated PMDx bit must
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default). See Table 33-1 for
more information.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid.
TABLE 33-1:
Note:
Disabling a peripheral module while it’s
ON bit is set, may result in undefined
behavior. The ON bit for the associated
peripheral module must be cleared prior to
disable a module via the PMDx bits.
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS(1)
Peripheral
ADC1
Comparator Voltage Reference
PMDx bit Name
Register Name and Bit Location
AD1MD
PMD1<0>
CVRMD
PMD1<12>
Comparator 1
CMP1MD
PMD2<0>
Comparator 2
CMP2MD
PMD2<1>
Input Capture 1
IC1MD
PMD3<0>
Input Capture 2
IC2MD
PMD3<1>
Input Capture 3
IC3MD
PMD3<2>
Input Capture 4
IC4MD
PMD3<3>
Input Capture 5
IC5MD
PMD3<4>
Input Capture 6
IC6MD
PMD3<5>
Input Capture 7
IC7MD
PMD3<6>
Input Capture 8
IC8MD
PMD3<7>
Input Capture 9
IC9MD
PMD3<8>
Output Compare 1
OC1MD
PMD3<16>
Output Compare 2
OC2MD
PMD3<17>
Output Compare 3
OC3MD
PMD3<18>
Output Compare 4
OC4MD
PMD3<19>
Output Compare 5
OC5MD
PMD3<20>
Output Compare 6
OC6MD
PMD3<21>
Output Compare 7
OC7MD
PMD3<22>
Output Compare 8
OC8MD
PMD3<23>
Output Compare 9
OC9MD
PMD3<24>
Timer1
T1MD
PMD4<0>
Timer2
T2MD
PMD4<1>
Timer3
T3MD
PMD4<2>
Timer4
T4MD
PMD4<3>
Timer5
T5MD
PMD4<4>
Timer6
T6MD
PMD4<5>
Timer7
T7MD
PMD4<6>
Timer8
T8MD
PMD4<7>
Timer9
T9MD
PMD4<8>
UART1
U1MD
PMD5<0>
UART2
U2MD
PMD5<1>
Note 1:
2:
Not all modules and associated PMDx bits are available on all devices. See TABLE 1: “PIC32MZ EC
Family Features” for the lists of available peripherals.
Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit.
DS60001191F-page 530
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
TABLE 33-1:
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS(1) (CONTINUED)
Peripheral
PMDx bit Name
Register Name and Bit Location
UART3
U3MD
PMD5<2>
UART4
U4MD
PMD5<3>
UART5
U5MD
PMD5<4>
UART6
U6MD
PMD5<5>
SPI1
SPI1MD
PMD5<8>
SPI2
SPI2MD
PMD5<9>
SPI3
SPI3MD
PMD5<10>
SPI4
SPI4MD
PMD5<11>
SPI5
SPI5MD
PMD5<12>
SPI6
SPI6MD
PMD5<13>
I2C1
I2C1MD
PMD5<16>
I2C2
I2C2MD
PMD5<17>
I2C3
I2C3MD
PMD5<18>
I2C4
I2C4MD
PMD5<19>
I2C5
I2C5MD
PMD5<20>
USB(2)
USBMD
PMD5<24>
CAN1
CAN1MD
PMD5<28>
CAN2
CAN2MD
PMD5<29>
RTCC
RTCCMD
PMD6<0>
Reference Clock Output 1
REFO1MD
PMD6<8>
Reference Clock Output 2
REFO2MD
PMD6<9>
Reference Clock Output 3
REFO3MD
PMD6<10>
Reference Clock Output 4
REFO4MD
PMD6<11>
PMPMD
PMD6<16>
PMP
EBI
EBIMD
PMD6<17>
SQI1
SQI1MD
PMD6<23>
Ethernet
ETHMD
PMD6<28>
DMA
DMAMD
PMD7<4>
RNGMD
PMD7<20>
CRYPTMD
PMD7<22>
Random Number Generator
Crypto
Note 1:
2:
Not all modules and associated PMDx bits are available on all devices. See TABLE 1: “PIC32MZ EC
Family Features” for the lists of available peripherals.
Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit.
 2013-2016 Microchip Technology Inc.
DS60001191F-page 531
PIC32MZ Embedded Connectivity (EC) Family
33.3.1
CONTROLLING CONFIGURATION
CHANGES
Because peripherals can be disabled during run time,
some restrictions on disabling peripherals are needed
to prevent accidental configuration changes. PIC32MZ
EC devices include two features to prevent alterations
to enabled or disabled peripherals:
• Control register lock sequence
• Configuration bit select lock
33.3.1.1
Control Register Lock
Under normal operation, writes to the PMDx registers
are not allowed. Attempted writes appear to execute
normally, but the contents of the registers remain
unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by
the PMDLOCK Configuration bit (CFGCON<12>). Setting PMDLOCK prevents writes to the control registers; 
clearing PMDLOCK allows writes.
To set or clear PMDLOCK, an unlock sequence must
be executed. Refer to Section 42. “Oscillators with
Enhanced PLL” (DS60001250) in the “PIC32 Family
Reference Manual” for details.
33.3.1.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the PMDx registers. The PMDL1WAY Configuration bit
(DEVCFG3<28>) blocks the PMDLOCK bit from being
cleared after it has been set once. If PMDLOCK
remains set, the register unlock procedure does not
execute, and the PPS control registers cannot be written to. The only way to clear the bit and re-enable PMD
functionality is to perform a device Reset.
DS60001191F-page 532
 2013-2016 Microchip Technology Inc.
Register
Name
PMD1
0050
PMD2
0060
PMD3
0070
PMD4
0080
PMD5
0090
PMD6
00A0
PMD7
Legend:
Note 1:
Bit Range
Bits
31/15
30/14
29/13
31:16
—
—
15:0
—
—
31:16
—
15:0
—
31:16
15:0
16/0
All Resets(1)
Virtual Address
(BF80_#)
0040
PERIPHERAL MODULE DISABLE REGISTER SUMMARY
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
CVRMD
—
—
—
—
—
—
—
—
—
—
—
AD1MD
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
CMP2MD
—
—
—
—
—
—
—
OC9MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
—
—
—
—
—
—
—
IC9MD
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CMP1MD 0000
0000
15:0
—
—
—
—
—
—
—
T9MD
T8MD
T7MD
T6MD
T5MD
T4MD
T3MD
T2MD
T1MD
0000
31:16
—
—
CAN2MD
CAN1MD
—
—
—
USBMD
—
—
—
I2C5MD
I2C4MD
I2C3MD
I2C2MD
I2C1MD
0000
15:0
—
—
SPI6MD
SPI5MD
SPI4MD
SPI3MD
SPI2MD
SPI1MD
—
—
U6MD
U5MD
U4MD
U3MD
U2MD
U1MD
0000
31:16
—
—
—
ETHMD
—
—
—
—
SQI1MD
—
—
—
—
—
EBIMD
PMPMD
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
REFO4MD REFO3MD REFO2MD REFO1MD
—
—
—
—
—
CRYPTMD
—
RNGMD
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
DMAMD
—
—
—
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant.
RTCCMD 0000
DS60001191F-page 533
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 33-2:
PIC32MZ Embedded Connectivity (EC) Family
NOTES:
DS60001191F-page 534
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
34.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MZ Embedded Connectivity
(EC) Family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
32.
“Configuration”
(DS60001124)
and
Section
33.
“Programming
and
Diagnostics”
(DS60001129), which are available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MZ EC devices include several features
intended to maximize application flexibility and reliability and minimize cost through elimination of external
components. These are:
•
•
•
•
Flexible device configuration
Joint Test Action Group (JTAG) interface
In-Circuit Serial Programming™ (ICSP™)
Internal temperature sensor
34.1
Configuration Bits
PIC32MZ EC devices contain two Boot Flash memories (Boot Flash 1 and Boot Flash 2), each with an
associated configuration space. These configuration
spaces can be programmed to contain various device
configurations. Configuration space that is aliased by
the Lower Boot Alias memory region is used to provide
values for Configuration registers listed below. See
4.1.1 “Boot Flash Sequence and Configuration
Spaces” for more information.
• DEVSIGN0/ADEVSIGN0: Device Signature Word
0 Register
• DEVCP0/ADEVCP0: Device Code-Protect 0
Register
• DEVCFG0/ADEVCFG0: Device Configuration
Word 0
• DEVCFG1/ADEVCFG1: Device Configuration
Word 1
• DEVCFG2/ADEVCFG2: Device Configuration
Word 2
• DEVCFG3/ADEVCFG3: Device Configuration
Word 3
The following run-time programmable Configuration
registers provide additional configuration control:
• CFGCON: Configuration Control Register
• CFGEBIA: External Bus Interface Address Pin
Configuration Register
• CFGEBIC: External Bus Interface Control Pin
Configuration Register
• CFGPG: Permission Group Configuration
Register
In addition, the DEVID register (see Register 34-11)
provides device and revision information, the
DEVADC1 through DEVADC5 registers (see
Register 34-12) provide ADC module calibration
data, and the DEVSN0 and DEVSN1 registers
contain a unique serial number of the device (see
Register 34-13).
Note:
 2013-2016 Microchip Technology Inc.
Do not use word program operation
(NVMOP<3:0> = 0001) when programming the device words that are described
in this section.
DS60001191F-page 535
Registers
Virtual Address
(BFC0_#)
Register
Name
TABLE 34-1:
FFC0
DEVCFG3
DEVCFG2
FFC8
DEVCFG1
FFCC
DEVCFG0
FFD0
DEVCP3
FFD4
DEVCP2
FFD8
DEVCP1
FFDC
FFE4
FFE8
DEVCP0
DEVSIGN3
DEVSIGN2
DEVSIGN1
FFEC DEVSIGN0
 2013-2016 Microchip Technology Inc.
Legend:
31:16
31/15
30/14
—
FUSBIDIO
29/13
28/12
27/11
IOL1WAY PMDL1WAY PGL1WAY
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
FETHIO
FMIIEN
—
—
—
—
—
—
—
—
—
—
—
—
FPLLODIV<2:0>
xxxx
—
FPLLIDIV<2:0>
xxxx
15:0
USERID<15:0>
31:16
—
15:0
—
UPLLFSEL
—
—
—
—
—
FPLLMULT<6:0>
31:16 FDMTEN
15:0
—
EJTAGBEN
—
—
—
—
OSCIOFNC
—
—
—
—
—
FSLEEP
FPLLRNG<2:0>
FWDTWINSZ<1:0>
FWDTEN
WINDIS
POSCMOD<1:0>
IESO
FSOSCEN
—
—
—
—
BOOTISA
TRCEN
—
WDTSPGM
WDTPS<4:0>
DMTINTV<2:0>
—
15:0
—
xxxx
DEBUG<1:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
31:16
—
—
—
CP
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
—
ICESEL<1:0>
—
JTAGEN
—
xxxx
—
FECCCON<1:0>
—
xxxx
FNOSC<2:0>
31:16
DBGPER<2:0>
—
xxxx
xxxx
FPLLICLK
DMTCNT<4:0>
FCKSM<1:0>
All Resets
Bit Range
Bits
FFC4
FFE0
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 536
34.2
FF44 ADEVCFG2
FF48 ADEVCFG1
FF4C ADEVCFG0
FF50
ADEVCP3
FF54
ADEVCP2
FF58
ADEVCP1
FF5C
ADEVCP0
FF60 ADEVSIGN3
FF64 ADEVSIGN2
FF68 ADEVSIGN1
FF6C ADEVSIGN0
31:16
31/15
30/14
—
FUSBIDIO
29/13
28/12
27/11
IOL1WAY PMDL1WAY PGL1WAY
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
FETHIO
FMIIEN
—
—
—
—
—
—
—
—
—
—
—
—
15:0
USERID<15:0>
31:16
—
15:0
—
UPLLFSEL
—
—
—
—
—
EJTAGBEN
—
—
—
—
OSCIOFNC
—
—
—
—
FPLLRNG<2:0>
FWDTWINSZ<1:0>
FWDTEN
WINDIS
POSCMOD<1:0>
IESO
FSOSCEN
—
—
—
—
—
xxxx
xxxx
FPLLICLK
DMTCNT<4:0>
FCKSM<1:0>
31:16
—
FPLLMULT<6:0>
31:16 FDMTEN
15:0
—
All Resets
Bit Range
Register
Name
Virtual Address
(BFC0_#)
Bits
FF40 ADEVCFG3
Legend:
ADEVCFG: ALTERNATE DEVICE CONFIGURATION WORD SUMMARY
—
WDTSPGM
FPLLODIV<2:0>
xxxx
FPLLIDIV<2:0>
xxxx
WDTPS<4:0>
DMTINTV<2:0>
—
xxxx
FNOSC<2:0>
—
—
—
xxxx
—
xxxx
15:0
—
—
FSLEEP
—
BOOTISA
TRCEN
DEBUG<1:0>
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
DBGPER<2:0>
FECCCON<1:0>
ICESEL<1:0>
JTAGEN
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
CP
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
DS60001191F-page 537
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 34-2:
Register
Name
CFGCON
0030
DEVID
SYSKEY
31/15
30/14
31:16
—
—
—
15:0
—
—
IOLOCK
31:16
29/13
28/12
27/11
26/10
25/9
—
—
—
—
PMDLOCK PGLOCK
24/8
23/7
22/6
DMAPRI
CPUPRI
—
—
USBSSEN
—
VER<3:0>
15:0
CFGPG
Legend:
Note
1:
2:
Virtual Address
(BFC5_#)
Register
Name
 2013-2016 Microchip Technology Inc.
4000
DEVADC1
4008
400C
4010
—
—
—
ECCCON<1:0>
18/2
17/1
—
—
ICACLK
JTAGEN
TROEN
—
16/0
OCACLK 0000
TDOEN
0000
SYSKEY<31:0>
15:0
31:16
—
EBI
RDYINV3
15:0
—
—
31:16
—
—
15:0
CAN2PG<1:0>
EBI
RDYINV2
EBI
RDYINV1
—
EBI
RDYEN3
EBIWEEN EBIOEEN
EBI
RDYEN2
—
EBIA7EN
EBI
RDYEN1
—
—
—
—
CRYPTPG<1:0>
CAN1PG<1:0>
—
—
USBPG<1:0>
0000
EBIA23EN EBIA22EN EBIA21EN EBIA20EN EBIA19EN EBIA18EN EBIA17EN EBIA16EN 0000
EBIA8EN
—
—
EBIA6EN
—
—
EBIA5EN
—
EBIA4EN
—
EBIBSEN1 EBIBSEN0 EBICSEN3 EBICSEN2 EBICSEN1 EBICSEN0
FCPG<1:0>
—
—
23/7
22/6
EBIA3EN
EBIA2EN
EBIA1EN
EBIA0EN 0000
—
—
EBI
RDYLVL
EBIRPEN 0000
EBIDEN1
EBIDEN0 0000
—
—
SQI1PG<1:0>
—
—
ETHPG<1:0>
0000
DMAPG<1:0>
—
—
CPUPG<1:0>
0000
19/3
18/2
DEVICE ADC CALIBRATION SUMMARY
Bits
DEVADC2
DEVADC3
DEVADC4
DEVADC5
Legend:
Note
1:
000B
xxxx
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant.
This register is not available on 64-pin devices.
TABLE 34-4:
4004
—
19/3
DEVID<15:0>
31:16
Bit Range
00E0
20/4
DEVID<27:16>
31:16 EBIPINEN
—
—
—
—
—
—
00C0 CFGEBIA(2)
15:0 EBIA15EN EBIA14EN EBIA13EN EBIA12EN EBIA11EN EBIA10EN EBIA9EN
00D0 CFGEBIC(2)
21/5
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
21/5
20/4
17/1
16/0
All Resets(1)
0020
Bit Range
Bits
All Resets(2)
Virtual Address
(BF80_#)
0000
DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
31:16
ADC Calibration Data <31:16>
xxxx
15:0
ADC Calibration Data <15:0>
xxxx
31:16
ADC Calibration Data <31:16>
xxxx
15:0
ADC Calibration Data <15:0>
xxxx
31:16
ADC Calibration Data <31:16>
xxxx
15:0
ADC Calibration Data <15:0>
xxxx
31:16
ADC Calibration Data <31:16>
xxxx
15:0
ADC Calibration Data <15:0>
xxxx
31:16
ADC Calibration Data <31:16>
xxxx
15:0
ADC Calibration Data <15:0>
xxxx
x = unknown value on Reset.
Reset values are dependent on the device variant.
PIC32MZ Embedded Connectivity (EC) Family
DS60001191F-page 538
TABLE 34-3:
Register
Name
DEVSN0
4024
DEVSN1
Legend:
Note
1:
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets(1)
Virtual Address
(BFC5_#)
4020
DEVICE SERIAL NUMBER SUMMARY
31:16
Device Serial Number <31:16>
xxxx
15:0
Device Serial Number <15:0>
xxxx
31:16
Device Serial Number <31:16>
xxxx
15:0
Device Serial Number <15:0>
xxxx
x = unknown value on Reset.
Reset values are dependent on the device variant.
DS60001191F-page 539
PIC32MZ Embedded Connectivity (EC) Family
 2013-2016 Microchip Technology Inc.
TABLE 34-5:
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 34-1:
Bit
Range
31:24
23:16
15:8
7:0
DEVSIGN0/ADEVSIGN0: DEVICE SIGNATURE WORD 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Reserved: Write as ‘0’
bit 30-0
Reserved: Write as ‘1’
Note:
The DEVSIGN1 through DEVSIGN3 and ADEVSIGN1 through ADEVSIGN3 registers are used for Quad
Word programming operation when programming the DEVSIGN0/ADESIGN0 registers, and do not contain
any valid information.
REGISTER 34-2:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
DEVCP0/ADEVCP0: DEVICE CODE-PROTECT 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
R/P
r-1
r-1
r-1
r-1
—
—
—
CP
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Reserved: Write as ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-0
Reserved: Write as ‘1’
Note:
The DEVCP1 through DEVCP3 and ADEVCP1 through ADEVCP3 registers are used for Quad Word
programming operation when programming the DEVCP0/ADEVCP0 registers, and do not contain any valid
information.
DS60001191F-page 540
 2013-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity (EC) Family
REGISTER 34-3:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG0/ADEVCFG0: DEVICE CONFIGURATION WORD