INTEGRATED CIRCUITS DATA SHEET UDA1355H Stereo audio codec with SPDIF interface Preliminary specification 2003 Apr 10 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface CONTENTS UDA1355H 11 I2C-BUS DESCRIPTION Characteristics Bit transfer Byte transfer Data transfer Register address Device address Start and stop conditions Acknowledgment Write cycle Read cycle 1 FEATURES 1.1 1.2 1.3 1.4 1.5 1.6 1.7 General Control IEC 60958 input IEC 60958 output Digital I/O interface ADC digital sound processing DAC digital sound processing 2 GENERAL DESCRIPTION 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 3 ORDERING INFORMATION 12 REGISTER MAPPING 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 12.1 12.2 12.3 Address mapping Read/write registers mapping Read registers mapping 7 FUNCTIONAL DESCRIPTION 13 LIMITING VALUES 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 IC control Microcontroller interface Clock systems IEC 60958 decoder IEC 60958 encoder Analog input Analog output Digital audio input and output Power-on reset 14 THERMAL CHARACTERISTICS 15 CHARACTERISTICS 16 TIMING CHARACTERISTICS 17 PACKAGE OUTLINE 18 SOLDERING 18.1 8 APPLICATION MODES 8.1 8.2 8.3 8.4 Static mode pin assignment Static mode basic applications Microcontroller mode pin assignment Microcontroller mode applications Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 9 SPDIF SIGNAL FORMAT 9.1 9.2 9.3 SPDIF channel encoding SPDIF hierarchical layers Timing characteristics 10 L3-BUS DESCRIPTION 10.1 10.2 10.3 10.4 Device addressing Register addressing Data write mode Data read mode 2003 Apr 10 18.2 18.3 18.4 18.5 2 19 DATA SHEET STATUS 20 DISCLAIMERS 21 TRADEMARKS NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 1 1.1 UDA1355H FEATURES General • 2.7 to 3.6 V power supply • Integrated digital interpolator filter and Digital-to-Analog Converter (DAC) • 24-bit data path in interpolator • No analog post filtering required for DAC • Integrated Analog-to-Digital Converter (ADC), Programmable Gain Amplifier (PGA) and digital decimator filter • 32, 44.1 and 48 kHz output frequencies (including double and half of these frequencies) supported in microcontroller mode • 24-bit data path in decimator • Via microcontroller, 40 status bits can be set for left and right channel. • Master or slave mode for digital audio data I/O interface • I2S-bus, MSB-justified, LSB-justified 16, 18, 20, and 24 bits formats supported on digital I/O interface. 1.5 1.2 • Supported static mode: • Supports sampling frequencies from 16 to 100 kHz Control – I2S-bus format • Controlled by means of static pins or microcontroller (L3-bus or I2C-bus) interface. 1.3 Digital I/O interface – LSB-justified 16 and 24 bits format – MSB-justified format. IEC 60958 input • Supported microcontroller mode: • On-chip amplifier for converting IEC 60958 input to CMOS levels – I2S-bus format – LSB-justified 16, 18, 20 or 24 bits format • Supports level I, II and III timing – MSB-justified format. • Selectable IEC 60958 input channel, one of four • BCK and WS signals can be slave or master, depending on application mode. • Supports input frequencies from 28 to 96 kHz • Lock indication signal available on pin LOCK • 40 status bits can be read for left and right channel via L3-bus or I2C-bus 1.6 • Channel status bits available via L3-bus or I2C-bus: lock, pre-emphasis, audio sample frequency, two channel Pulse Code Modulation (PCM) indication and clock accuracy • Analog front-end includes a 0 to +24 dB PGA in steps of 3 dB, selectable via microcontroller interface • Supports sampling frequencies from 16 to 100 kHz • Digital independent left and right volume control of +24 to −63.5 dB in steps of 0.5 dB via microcontroller interface • Pre-emphasis information of incoming IEC 60958 bitstream available in register • Bitstream ADC operating at 64fs • Detection of digital data preamble, such as AC3, available on pin in microcontroller mode. 1.4 • Comb filter decreases sample rate from 64fs to 8fs • Decimator filter (8fs to fs) made of a cascade of three FIR half-band filters. IEC 60958 output • CMOS output level converted to IEC 60958 output signal 1.7 DAC digital sound processing • Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio sampling frequencies • Full-swing digital signal, with level II timing using crystal oscillator clock • Automatic de-emphasis when using IEC 60958 to DAC • 32, 44.1 and 48 kHz output frequencies supported in static mode 2003 Apr 10 ADC digital sound processing • Soft mute made of a cosine roll-off circuit selectable via pin MUTE or L3-bus interface 3 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface • Programmable digital silence detector which can generate level II output signals with CMOS levels. In microcontroller mode the UDA1355H offers a large variety of possibilities for defining signal flows through the IC, offering a flexible analog, digital and SPDIF converter chip with possibilities for off-chip sound processing via the digital input and output interface. • Interpolating filter (fs to 64fs or fs to 128fs) comprising a recursive and a FIR filter in cascade • Selectable fifth-order noise shaper operating at 64fs or third-order noise shaper operating at 128fs (specially for low sampling frequencies, e.g. 16 kHz) generating bitstream for DAC A lock indicator is available on pin LOCK when the IEC 60958 decoder and the clock regeneration mechanism is in lock. By default the DAC output and the digital data interface output are muted when the decoder is not in lock. • Filter Stream DAC (FSDAC) • In microcontroller mode: – Left and right volume control (for balance control) 0 to −78 dB and −∞ The UDA1355H contains two clock systems which can run at independent frequencies, allowing to lock-on to an incoming SPDIF or digital audio signal, and in the mean time generating a stable signal by means of the crystal oscillator for driving, for example, the ADC or SPDIF output signal. – Left and right bass boost and treble control – Optional resonant bass boost control – Mixing possibility of two data streams. 2 UDA1355H GENERAL DESCRIPTION Using the crystal oscillator (which requires a 12.288 MHz crystal) and the on-chip low jitter PLL, all standard audio sampling frequencies (fs = 32, 44.1 and 48 kHz including half and double these frequencies) can be generated. The UDA1355H is a single-chip IEC 60958 decoder and encoder with integrated stereo digital-to-analog converters and analog-to-digital converters employing bitstream conversion techniques. The UDA1355H has a selectable one-of-four SPDIF input (accepting level I, II and III timing) and one SPDIF output 3 ORDERING INFORMATION TYPE NUMBER UDA1355H 2003 Apr 10 PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm 4 VERSION SOT307-2 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 4 UDA1355H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA1 DAC supply voltage 2.7 3.0 3.6 V VDDA2 ADC supply voltage 2.7 3.0 3.6 V VDDX crystal oscillator and PLL supply voltage 2.7 3.0 3.6 V VDDI digital core supply voltage 2.7 3.0 3.6 V VDDE digital pad supply voltage IDDA1 DAC supply current IDDA2 ADC supply current 2.7 3.0 3.6 V fs = 48 kHz; power-on − 4.7 − mA fs = 96 kHz; power-on − 4.7 − mA fs = 48 kHz; power-down − 1.7 − μA fs = 96 kHz; power-down − 1.7 − μA fs = 48 kHz; power-on − 10.2 − mA fs = 96 kHz; power-on − 10.4 − mA fs = 48 kHz; power-down − 0.2 − μA fs = 96 kHz; power-down − 0.2 − μA IDDX crystal oscillator and PLL supply current fs = 48 kHz; power-on − 0.9 − mA fs = 96 kHz; power-on − 1.2 − mA IDDI digital core supply current fs = 48 kHz; all on − 18.2 − mA fs = 96 kHz; all on − 34.7 − mA fs = 48 kHz; all on − 0.5 − mA fs = 96 kHz; all on − 0.7 − mA −40 − +85 °C IDDE Tamb digital pad supply current ambient temperature Digital-to-analog converter; fi = 1 kHz; VDDA1 = 3.0 V Vo(rms) output voltage (RMS value) − 900 − mV ΔVo output voltage unbalance − 0.1 − dB (THD+N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB − −88 − dB at −20 dB − −75 − dB at −60 dB; A-weighted − −37 − dB at 0 dB − −83 − dB at −60 dB; A-weighted − −37 − dB fs = 48 kHz − 98 − dB fs = 96 kHz − 96 − dB − 100 − dB IEC 60958 input; fs = 48 kHz IEC 60958 input; fs = 96 kHz S/N αcs 2003 Apr 10 signal-to-noise ratio IEC 60958 input; code = 0; A-weighted channel separation 5 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER CONDITIONS UDA1355H MIN. TYP. MAX. UNIT Analog-to-digital converter; fi = 1 kHz; VDDA2 = 3.0 V Vi(rms) input voltage (RMS value) ΔVi input voltage unbalance (THD+N)/S total harmonic distortion-plus-noise to signal ratio Vo = −1.16 dBFS digital output − 1.0 − V − 0.1 − dB at 0 dB − −85 − dB at −60 dB; A-weighted − −35 − dB at 0 dB − −85 − dB at −60 dB; A-weighted − −35 − dB fs = 48 kHz − 97 − dB fs = 96 kHz fs = 48 kHz fs = 96 kHz S/N signal-to-noise ratio code = 0; A-weighted − 95 − dB channel separation − 100 − dB fxtal crystal frequency − 12.288 − CL(xtal) crystal load capacitor − 10 − pF reset time − 250 − μs DAC in playback mode − 74 − mW DAC in Power-down mode − 63 − mW αcs External crystal MHz Device reset trst Power consumption Ptot 2003 Apr 10 total power consumption IEC 60958 input; fs = 48 kHz 6 RTCB WSI DATAI BCKI SPDIF0 7 SPDIF1 SPDIF2 SPDIF3 SLICER_SEL0 SLICER_SEL1 LOCK 37 27 38 11 VDDE VDDA1 6 39 13 14 34 36 CLOCK AND TIMING XTAL ADC COMB FILTER AUDIO FEATURE PROCESSOR AUDIO FEATURE PROCESSOR DECIMATOR ADC DAC INTERPOLATOR NOISE SHAPER DAC 40 42 44 16 43 INPUT AND OUTPUT SELECT 2 3 DATA IN 9 8 DATA OUT 10 1 VOUTL VOUTR MUTE WSO DATAO BCKO SLICER 23 24 IEC 60958 DECODER 25 IEC 60958 ENCODER 26 5 NXP Semiconductors RESET 32 VREF Stereo audio codec with SPDIF interface VINR 15 VDDI BLOCK DIAGRAM VINL 12 VADCP VDDA2 CLK_OUT 5 XTALOUT VSSX handbook, full pagewidth 2003 Apr 10 XTALIN VDDX SPDIFOUT 21 22 4 UDA1355H CONTROL INTERFACE 35 28 29 30 31 20 17 18 19 7 41 VSSIS VSSA2 MP0 MODE0 MP2 MP1 SEL_STATIC MODE2 MODE1 Fig.1 Block diagram. VSSE VSSA1 UDA1355H MGU826 VADCN Preliminary specification 33 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 6 UDA1355H PINNING SYMBOL PIN PAD(1) DESCRIPTION BCKI 1 bpt4mtht5v bit clock input (master or slave) WSI 2 bpt4mtht5v word select input (master or slave) DATAI 3 iptht5v digital data input LOCK 4 op4mc PLL lock indicator output SPDIFOUT 5 op4mc SPDIF output VDDE 6 vdde digital pad supply voltage VSSE 7 vsse digital pad ground DATAO 8 ops5c digital data output WSO 9 bpt4mtht5v word select output (master or slave) BCKO 10 bpt4mtht5v bit clock output (master or slave) CLK_OUT 11 op4mc clock output; 256fs or 384fs VDDX 12 vddco crystal oscillator and PLL supply voltage XTALIN 13 apio crystal oscillator input XTALOUT 14 apio crystal oscillator output VSSX 15 vssco crystal oscillator and PLL ground RESET 16 ipthdt5v reset input MODE0 17 apio mode selection input 0 for static mode or microcontroller mode (grounded for I2C-bus) MODE1 18 bpts5tht5v mode selection input 1 for static mode or AO address input and output for microcontroller mode MODE2 19 bpts5tht5v mode selection input 2 for static mode or U_RDY output for microcontroller mode SEL_STATIC 20 apio selection input for static mode, I2C-bus mode or L3-bus mode SLICER_SEL0 21 bpts5tht5v SPDIF slicer selection input 0 for static mode and USER bit output for microcontroller mode SLICER_SEL1 22 bpts5tht5v SPDIF slicer selection input 1 for static mode and AC3 preamble detect output for microcontroller mode SPDIF0 23 apio SPDIF input 0 SPDIF1 24 apio SPDIF input 1 SPDIF2 25 apio SPDIF input 2 SPDIF3 26 apio SPDIF input 3 VDDI 27 vddi digital core supply voltage VSSIS 28 vssis digital core ground MP0 29 apio multi-purpose pin 0: frequency select for static mode, not used for microcontroller mode MP1 30 iptht5v multi-purpose pin 1: SFOR1 for static mode, SCL for I2C-bus mode and L3CLOCK for L3-bus mode MP2 31 iic400kt5v multi-purpose pin 2: SFOR0 for static mode, SDA for I2C-bus mode and L3DATA for L3-bus mode VADCP 32 vddco positive ADC reference voltage VADCN 33 vssco negative ADC reference voltage 2003 Apr 10 8 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL VINL PIN 34 PAD(1) apio UDA1355H DESCRIPTION ADC left channel input VSSA2 35 vssco ADC ground VINR 36 apio ADC right channel input VDDA2 37 vddco ADC supply voltage VREF 38 apio reference voltage for ADC and DAC VDDA1 39 vddco DAC supply voltage VOUTL 40 apio DAC left channel output VSSA1 41 vssco DAC ground VOUTR 42 apio DAC right channel output RTCB 43 ipthdt5v test control input MUTE 44 iipthdt5v DAC mute input Note 1. See Table 1. Table 1 Pad description PAD DESCRIPTION iptht5v input pad; push-pull; TTL with hysteresis; 5 V tolerant ipthdt5v input pad; push-pull; TTL with hysteresis; pull-down; 5 V tolerant op4mc output pad; push-pull; 4 mA output drive; CMOS ops5c output pad; push-pull; 5 ns slew rate control; CMOS bpt4mtht5v bidirectional pad; push-pull input; 3-state output; 4 mA output drive; TTL with hysteresis; 5 V tolerant bpts5tht5v bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL with hysteresis; 5 V tolerant iic400kt5v I2C-bus pad; 400 kHz I2C-bus specification with open drain; 5 V tolerant apio analog pad; analog input or output vddco analog supply pad vssco analog ground pad vdde digital supply pad vsse digital ground pad vddi digital core supply pad vssis digital core ground pad 2003 Apr 10 9 NXP Semiconductors Preliminary specification 34 VINL 36 VINR 35 VSSA2 UDA1355H 37 VDDA2 38 VREF 39 VDDA1 40 VOUTL 41 VSSA1 42 VOUTR 44 MUTE handbook, full pagewidth 43 RTCB Stereo audio codec with SPDIF interface BCKI 1 33 VADCN WSI 2 32 VADCP DATAI 3 31 MP2 LOCK 4 30 MP1 SPDIFOUT 5 29 MP0 VDDE 6 28 VSSIS UDA1355H 27 VDDI VSSE 7 SLICER_SEL1 22 SEL_STATIC 20 SLICER_SEL0 21 MODE2 19 MODE1 18 MODE0 17 23 SPDIF0 RESET 16 24 SPDIF1 VSSX 15 BCKO 10 CLK_OUT 11 XTALOUT 14 25 SPDIF2 XTALIN 13 26 SPDIF3 WSO 9 VDDX 12 DATAO 8 MGU828 Fig.2 Pin configuration. 7 7.1 FUNCTIONAL DESCRIPTION Table 2 IC control Control mode selection via pin SEL_STATIC LEVEL HIGH The UDA1355H can be controlled either via static pins or via the microcontroller serial hardware interface being the I2C-bus with a clock up to 400 kHz or the L3-bus with a clock up to 2 MHz. It is recommended to use the microcontroller interface since this gives full access to all the IC features. 7.2 MODE static mode MID I2C-bus LOW L3-bus mode Microcontroller interface The UDA1355H has a microcontroller interface and all the sound processing features and system settings can be controlled by the microcontroller. The two microcontroller interfaces only differ in interface format. The register addresses and features that can be controlled are identical for L3-bus mode and I2C-bus mode. The controllable settings are: The UDA1355H can operate in three control modes: • Restoring L3-bus defaults • Static mode with limited features • Power-on settings for all blocks • L3-bus mode with full featuring • Digital interface input and output formats • I2C-bus mode with full featuring. • Volume settings for the decimator • PGA gain settings The modes are selected via the 3-level pin SEL_STATIC according to Table 2. 2003 Apr 10 mode 10 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface • Set two times 40 bits of channel status bits of the SPDIF output UDA1355H Table 3 Output frequencies OUTPUT FREQUENCY • Select one of four SPDIF input sources BASIC AUDIO FREQUENCY • Enable digital mixer inside interpolator • Control mute and mixer volumes of digital mixer • Selection of filter mode and settings of treble and bass boost for the interpolator (DAC) section 32 kHz MICROCONTROLLER MODE 256 × 16 kHz 384 × 16 kHz • Volume settings of interpolator 256 × 32 kHz • Selection of soft mute via cosine roll-off (only effective in L3-bus control mode) and bypass of auto mute 256 × 32 kHz 384 × 32 kHz 256 × 64 kHz • Selection of de-emphasis 384 × 64 kHz • Enable and control of digital mixer inside interpolator. 44.1 kHz The readable settings are: 256 × 22.05 kHz 384 × 22.05 kHz • Mute status of interpolator 256 × 44.1 kHz • PLL lock and adaptive lock 384 × 44.1 kHz • Two times 40 bits of channels status bits of the SPDIF input signal. 7.3 STATIC MODE 256 × 44.1 kHz 256 × 88.2 kHz 384 × 88.2 kHz 48 kHz Clock systems 256 × 24 kHz 384 × 24 kHz The UDA1355H has two clock systems. 256 × 48 kHz The first system uses an external crystal of 12.288 MHz to generate the audio related system clocks. Only a crystal with a frequency of 12.288 MHz is allowed. 256 × 48 kHz 384 × 48 kHz 256 × 96 kHz 384 × 96 kHz The second system is a PLL which locks on the SPDIF or incoming digital audio signal (e.g. I2S-bus) and recovers the system clock. Remarks: The crystal oscillator and the on-chip PLL and divider circuit can be used to generate internal and external clock signals related to standard audio sampling frequencies (such as 32, 44.1 and 48 kHz including half and double of these frequencies). • If an application mode is selected which does not need a crystal oscillator, the crystal oscillator cannot be omitted. The reason is that the interpolator switches to the crystal clock when an SPDIF input signal is removed. This switch prevents the noise shaper noise from moving inside the audio band as the PLL gradually decreases in frequency. The audio frequencies supported in either microcontroller mode or static mode are given in Table 3. • If no accurate output frequency is needed, the crystal can be replaced with a resonator. 7.3.1 CRYSTAL OSCILLATOR CLOCK SYSTEM • Instead of the crystal, a 12.288 MHz system clock can be applied to pin XTALIN. The block diagram of the crystal oscillator and the PLL circuit is given in Fig.3. 2003 Apr 10 11 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 7.3.4 The UDA1355H has a clock output pin (pin CLK_OUT), which can be used to drive other audio devices in the system. In microcontroller mode the output clock is 256fs or 384fs. In static mode the output clock is 256 times 32, 44.1 and 48 kHz. 12.288 MHz handbook, halfpage 13 XTALIN 14 CRYSTAL OSCILLATOR PLL MODULE XTALOUT The source of the output clock is either the crystal oscillator or the PLL, depending on the selected application and control mode. 256fs or 384fs clock CLK_OUT 11 PLL clock 7.4 L3-bus or I2C-bus register setting UDA1355H IEC 60958 decoder The UDA1355H IEC 60958 decoder can select one of four SPDIF input channels. An on-chip amplifier with hysteresis amplifies the SPDIF input signal to CMOS level, making it possible to accept both analog and digital SPDIF signals (see Fig.5). MGU830 Fig.3 Crystal oscillator clock system. 7.3.2 CLOCK OUTPUT PLL CLOCK SYSTEM The PLL locks on the incoming digital data of the SPDIF or WS input signal. The PLL recovers the clock from the SPDIF or WSI signal and removes jitter to produce a stable system clock (see Fig.4). handbook, halfpage 10 nF 75 Ω SPDIF1 SPDIF2 SPDIF3 UDA1355H MGU829 23 24 IEC 60958 DECODER 25 Fig.5 IEC 60958 input circuit. 26 7.4.1 SLICER WSI 2 PLL 256fs or 384fs There is a hard mute (not a cosine roll-off mute) if the IEC 60958 decoder is out of lock or detects bi-mark phase encoding violations. The lock indicator and the key channel status bits are accessible in L3-bus mode. Fig.4 PLL clock system. The UDA1355H supports the following sample frequencies and data rates, including half and double of these frequencies: WORD SELECTION DETECTION CIRCUIT This circuit is clocked by the 12.288 MHz crystal oscillator clock and generates a Word Selection (WS) detection signal. If the WS detector does not detect any WS edge, defined as 7 times LOW and 7 times HIGH, then the WS detection signal is LOW. This information can be used to set the clock for the noise shaper in the interpolator. This will prevent noise shaper noise in the audio band. 2003 Apr 10 AUDIO DATA From the incoming SPDIF bitstream 24 bits of data for the left and right channel are extracted. MGU827 7.3.3 23 24 25 26 UDA1355H select SPDIF source SPDIF0 180 pF SPDIF0 SPDIF1 SPDIF2 SPDIF3 • fs = 32 kHz; resulting in a data rate of 2.048 Mbit/s • fs = 44.1 kHz; resulting in a data rate of 2.8224 Mbit/s • fs = 48 kHz; resulting in a data rate of 3.072 Mbit/s. 12 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 7.4.2 CHANNEL STATUS AND USER BITS 7.5 As well as the data bits there are several IEC 60958 key channel status bits: UDA1355H IEC 60958 encoder When using the crystal oscillator clock, the IEC 60958 encoder output is a full-swing digital signal with level II timing. • Pre-emphasis and audio sampling frequency bits • Two channel PCM indicator bits • Clock accuracy bits. When the recovered clock from the PLL is used the IEC 60958 encoder will function correctly but will not meet level II timing requirements. In total 40 status bits per channel are recovered from the incoming IEC 60958 bitstream. These are readable via the microcontroller interface. 7.5.1 All user and channel status bits are set to logic 0. This is default value specified by IEC. User bits, which can contain a large variety of data, such as CD text, are output to pin SLICER_SEL0 (see Table 4). In microcontroller mode this signal contains the raw user bits extracted from the SPDIF bitstream. Signal U_RDY gives a pulse on pin MODE2 each time there is a new user bit available. Both signals can be used by an external microcontroller to grab and decode the user bits. Table 4 SLICER_SEL0 MODE2 7.5.2 SIGNAL NAME The procedure of writing the channel status bits is as follows: USER 1. Set bit SPDO_VALID = 0 to prevent immediately sending the status bits during writing. AC3 2. Set bit l_r_copy = 1 if the right channel needs the same status bits as the left channel or set bit l_r_copy = 0 if the right channel needs different status bits to the left channel. DIGITAL DATA Audio and digital data can be transmitted in the SPDIF bitstream. The PCM channel status bit should be set to logic 1 if the SPDIF bitstream is carrying digital data instead of audio data, but in practice it proves that not all equipment handles these channel status bits properly. 3. Write the left and right channel status bits. 4. Set bit SPDO_VALID = 1 after writing all channel status bits to the register. Starting from the next SPDIF block the IEC 60958 encoder will use the new status bits. In the UDA1355H, digital data is detected via bit PCM, or via the sync bytes as specified by IEC. These sync bytes are two sync words, F872H and 4E1FH (two subframes) preceded by four or more subframes filled with zeros. Signal AC3 is kept HIGH for 4096 frames when the UDA1355H detects this burst preamble. Signal AC3 is present on pin SLICER_SEL1 in microcontroller mode (see Table 4). 2003 Apr 10 MICROCONTROLLER MODE Two times 40 channel status bits can be set. Default value for each status bit is logic 0. When setting the channel status bits, it is possible to set only the left channel status bits and have the bits copied to the right channel. U_RDY SLICER_SEL1 7.4.3 In static mode 0 and 2, the selected SPDIF input channel can be looped through to pin SPDIFOUT (see Fig.6). Signal names in microcontroller mode PIN NAME STATIC MODE In microcontroller modes 2 and 13, the selected SPDIF input channel can be looped through to pin SPDIFOUT (see Fig.6). 13 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface handbook, full pagewidth SPDOUT_SEL1 UDA1355H SPDOUT_SEL0 SPDIF0 SPDIF1 SPDIF2 SPDIF3 23 UDA1355H SPDOUT_SEL2 MODE [3:0] IEC 60958 DECODER 24 25 26 5 SLICER SPDIF OUT select SPDIF source SPDIF source IEC 60958 ENCODER 21, 22 17 to 19 SLICER_SEL [1:0] 20 MODE [2:0] SEL_STATIC MGU833 Fig.6 Selection options for SPDIF output. 7.6 Analog input 7.6.1 7.6.2 The decimation from 64fs is performed in two stages: comb filter and decimation filter. The first stage realizes a sin x fourth-order ------------ characteristic with a decimation factor x of eight. The second stage consists of three half-band filters each decimating by a factor of two. Table 6 shows the characteristics. ADC The analog input is equipped with a Programmable Gain Amplifier (PGA) which can be controlled via the microcontroller interface. The control range is from 0 to 24 dB gain in 3 dB steps independent for the left and right channels. In applications in with a 2 V (RMS) input signal, a 12 kΩ resistor must be used in series with the input of the ADC. The 12 kΩ resistor forms a voltage divider together with the internal ADC resistor and ensures that the voltage, applied to the input of the IC, never exceeds 1 V (RMS). In the application for a 2 V (RMS) input signal, the PGA must be set to 0 dB. When a 1 V (RMS) input signal is applied to the ADC in the same application, the PGA gain must be set to 6 dB. Table 6 Pass-band ripple Stop band Dynamic range Overall gain from ADC input to digital output Present Absent 2003 Apr 10 PGA GAIN SETTING 2 V (RMS) 6 dB 1 V (RMS) 0 dB 1 V (RMS) 6 dB 0.5 V (RMS) VALUE (dB) 0 to 0.45fs ±0.02 >0.55fs −60 0 to 0.45fs 140 DC; VI = 0 dB; note 1 −1.16 1. The output is not 0 dB when VI(rms) = 1 V at VDD = 3 V. This is because the analog components can spread over the process. When there is no external resistor, the −1.16 dB scaling prevents clipping caused by process mismatch. MAXIMUM INPUT VOLTAGE 0 dB CONDITIONS Note Maximum input voltage; VDD = 3 V EXTERNAL RESISTOR (12 kΩ) Decimation filter characteristics ITEM An overview of the maximum input voltages allowed with and without an external resistor and the PGA gain setting is given in Table 5. Table 5 DECIMATION In the ADC path there are left and right independent digital volume controls with a range from +24 to −63.5 dB and −∞ dB. This volume control is also used as a digital linear mute that can be used to prevent plops when powering-up or powering down the ADC front path. 14 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 7.6.3 • Support for 1fs and 2fs input data rate and 192 kHz audio via I2S-bus. DC FILTERING In the decimator there are two digital DC blocking circuits. The stereo interpolator has the following sound features: The first blocking circuit is in front of the volume control to remove DC bias from the ADC output. The DC bias is added in the ADC to prevent audio band Idle tones occurring in the noise shaper. With the DC components removed, a signal gain of 24 dB can be achieved. • Linear volume control using 14-bit coefficients with 0.25 dB steps: range 0 to −78 dB and −∞ dB; hold for master volume and mixing volume control • A cosine roll-off soft mute with 32 coefficients; each coefficient is used for four samples, in total 128 samples are needed to fully mute or de-mute (approximately 3 ms at fs = 44.1 kHz) The second blocking circuit removes the DC components introduced by the decimator stage. 7.6.4 • Independent selectable de-emphasis for 32, 44.1, 48 and 96 kHz for both channels OVERLOAD DETECTION Bit OVERFLOW = 1 when the output data in the left or right channel is larger than −1.16 dB of the maximum possible digital swing. This condition is set for at least 512fs cycles (that is 11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. 7.7 7.7.1 • Treble is the selectable positive gain for high frequencies. The edge frequency of the treble is fixed and depends on the sampling frequency. Treble can be set independently for left and right channel with two settings: – fc = 1.5 kHz; fs = 44.1 kHz; 0 to 6 dB gain range with 2 dB steps Analog output AUDIO FEATURE PROCESSOR – fc = 3 kHz; fs = 44.1 kHz; 0 to 6 dB gain range with 2 dB steps. The audio feature processor provides automatic de-emphasis for the IEC 60958 bitstream. In microcontroller mode all features are available and there is a default mute on start up. 7.7.2 • Normal bass boost is the selectable positive gain for low frequencies. The edge frequency of the bass boost is fixed and depends on the sampling frequency. Normal bass boost can be set independently for the left and right channel with two sets: INTERPOLATING FILTER The digital filter interpolates from 1fs to 64fs, or from 1fs to 128fs, by cascading a half-band filter and a FIR filter. – fc = 250 Hz; fs = 44.1 kHz; 0 to 18 dB gain range with 2 dB steps The stereo interpolator has the following basic features: – fc = 300 Hz; fs = 44.1 kHz; 0 to 24 dB gain range with 2 dB steps. • 24-bit data path • Resonant bass boost optional function is selected if bit BASS_SEL = 1. When selected, the characteristics are determined by six 14-bit coefficients. Resonant bass boost controls the left and right channel with the same characteristics. When resonant bass boost is selected, the treble control also changes to a single control for both channels following the gain setting of the left channel. • Mixing of two channels: – To prevent clipping inside the core, there is an automatic signal level correction of −6 dB scaling before mixing and +6 dB gain after digital volume control – Position of mixing can be set before or after bass boost and treble – Master volume control and mute with independent left and right channel settings for balance control A software program is available for users to generate the required six 14-bit coefficients by entering the desired centre frequency (fc), positive or negative peak gain, sampling frequency (fs) and shape factor (see Figs 7 and 8). – Independently left and right channel de-emphasis, volume control and mute (no left or right) – Output of the mixer is to the I2S-bus or IEC 60958 decoder. • Full FIR filter implementation for all the upsampling filters • Integrated digital silence detection for left and right channels with selectable silence detection time 2003 Apr 10 UDA1355H 15 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 7 Interpolation filter characteristics ITEM CONDITIONS VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.035 >0.55fs −60 0 to 0.4535fs 140 Stop band Dynamic range 7.7.3 mute controls available: for source 1, for source 2 and for the master (sum) signal. All three volume ranges can be controlled in 0.25 dB steps. To prevent clipping inside the mixer, the signals are scaled with −6 dB before mixing, therefore the sum of the two signals is always equal to or lower than 0 dB. After the mixing there is a 6 dB gain in the master volume control. This means that at the analog output the signal can clip, but the clipping can be undone by decreasing the master volume control. DIGITAL MIXER The UDA1355H has a digital mixer inside the interpolator. The digital mixer can be used as a cross over or a selector. A functional block diagram of the mixer mode is shown in Fig.9. This mixer can be used in microcontroller mode only. The output of the mixer is available via the I2S-bus output or via the SPDIF output. The output signal of the mixer is scaled to a maximum of 0 dB, so the digital output can never clip. The UDA1355H can be set to the mixer mode by setting bit MIX = 1. In the mixer mode, there are three volume and MGU832 10 UDA1355H handbook, halfpage gain 8 (dB) gain 8 (dB) 6 6 4 4 2 2 0 0 −2 −2 −4 −4 −6 −6 −8 −8 −10 1 fc = 70 Hz fs = 44.1 kHz 10 102 f (Hz)) −10 103 Peak gain = 10 dB Shape factor = 1.4142 1 fc = 70 Hz fs = 44.1 kHz Fig.7 Resonant bass boost example 1. 2003 Apr 10 MGU831 10 handbook, halfpage 10 102 f (Hz)) 103 Peak gain = 10 dB Shape factor = 1.4142 Fig.8 Resonant bass boost example 2. 16 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H handbook, full pagewidth DE-EMPHASIS mixing after sound features mixing before sound features channel 2 VOLUME AND MUTE 1fs UDA1355H L3/I2C bit DE-EMPHASIS VOLUME AND MUTE BASS-BOOST AND TREBLE INT. FILTER 2fs channel 1 MASTER VOLUME AND MUTE to interpolation filter and DAC output output of mixer MGU834 Fig.9 Digital mixer (DAC) inside the interpolator DSP. 7.7.4 DIGITAL SILENCE DETECTOR 7.7.6 The UDA1355H is equipped with a digital silence detector. This detects whether a certain amount of consecutive samples are 0. The number of samples can be set with bits SD_VALUE[1:0] to 3200, 4800, 9600 or 19600 samples. The FSDAC is a semi digital reconstruction filter that converts the 1-bit data bitstream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the operational amplifier output. In this way, very high signal-to-noise performance and low clock jitter sensitivity are achieved. A post filter is not needed due to the inherent filter function of the FSDAC. On-chip amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the supply voltage. The digital silence detection status can be read via the microcontroller interface. 7.7.5 NOISE SHAPER (DAC) The noise shaper shifts in-band quantization noise to frequencies above the audio band. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). This noise shaping technique enables high signal-to-noise ratios to be achieved. 7.7.7 DAC MUTE The DAC and interpolator can be muted by setting pin MUTE to a HIGH level. The output signal is muted to zero via a cosine roll-off curve and the DAC is powered down. When pin MUTE is at LOW level the signal rise follows the same cosine curve. The UDA1355H is equipped with two noise shapers: • A third-order noise shaper operating at 128fs. Which is used at low sampling frequencies (8 to 16 kHz) to prevent noise shaper noise shifting into the audio band for the fifth-order noise shaper To prevent plops in case of changing inputs, clock to the DAC or application modes, a special mute circuit for the DAC is implemented (see Table 8). • A fifth-order noise shaper operating at 64fs. Which is used at high sampling frequencies (from 32 kHz upwards). In all application modes in which the DAC is active the DAC can be muted by pin MUTE. The microcontroller mute bits and pin MUTE act as an OR function. When the noise shaper changes, the clock to the FSDAC changes and the filter characteristic of the FSDAC also changes. The effect on the roll of is compensated by selecting the filter matching speed and order of the noise shaper. 2003 Apr 10 FILTER STREAM DAC 17 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 8 UDA1355H Muting to prevent plopping BIT OCCASION DE-MUTE CONDITION MT1 MT2 MTM Select channel 1 source x − − no mute after selection Select channel 2 source − x − no mute after selection PLL is source for the DAC − − x wait until PLL is locked again Crystal is source for the DAC − − x no mute after selection Input selection Select chip mode Select between microcontroller mode and static mode PLL is source for the DAC − − x wait until PLL is locked again Crystal is source for the DAC − − x no mute after selection − − x no mute after selection Audio features Select noise shaper order Select FSDAC output polarity − − x no mute after selection Select SPDIF input − − x PLL is locked again Select mixer − − − no mute needed Select mixer position − − − no mute needed Select crystal clock source − − x no mute after selection 7.8 • LSB-justified; 18 bits Digital audio input and output • LSB-justified; 20 bits The selection of the digital audio input and output formats and master or slave modes differ for static and microcontroller mode. • LSB-justified; 24 bits • MSB-justified. In master mode, when 256fs output clock is selected and the digital interface is master, the BCK output clock will be 64fs. In case 384fs output clock is selected, the BCK output clock will be 48fs. 7.9 The UDA1355H has a dedicated reset pin with an internal pull-down resistor. In this way a Power-on reset circuit can be made with a capacitor and a resistor at pin RESET. The external resistor is needed since the pad is 5 V tolerant. This means that there is a transmission gate in series with the input and the resistor inside the pad cannot be seen from the outside world (see Fig.10). In the static mode the digital audio input formats are: • I2S-bus • LSB-justified; 16 bits • LSB-justified; 24 bits • MSB-justified. The reset timing is determined by the external pull-down resistor and the external capacitor which is connected to pin RESET. At Power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the microcontroller mode. Since the bit controlling the clock of the synchronous registers is set to enable, the synchronous registers are also reset. The digital audio output formats are: • I2S-bus • MSB-justified. In the microcontroller mode, the following formats are independently selectable: • I2S-bus • LSB-justified; 16 bits 2003 Apr 10 Power-on reset 18 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 8 handbook, halfpage RESET APPLICATION MODES In this chapter the application modes for static mode and microcontroller mode are described. Transmission gate for 5V tolerance The UDA1355H can be controlled by static pins, the L3-bus or I2C-bus interface. Due to the limitations imposed by the pin count, only basic functions are available in static mode. For optimum use of the UDA1355H features, the microcontroller mode is strongly recommended. 16 UDA1355H UDA1355H VSS There are 11 application modes available in the static mode and 14 application modes in microcontroller mode. The application modes are explained in the two sections: Section 8.2 explains the application modes 0 to 10. Section 8.4 explains the more advanced features of modes 0 to 10 and modes 12 to 14 available in the microcontroller mode. MGU835 Fig.10 5 V tolerant pull-down input pad. The clock should be running during the reset time. When no clock can be guaranteed in microcontroller mode, a soft reset should be given when the system is running by writing to register 7FH. 8.1 Static mode pin assignment The default values for all non-pin controlled settings are identical to the start-up defaults from the microcontroller mode. Whether BCK and WS are master or slave depends on the selected application mode. Table 9 defines the pin functions in static mode. Table 9 Static mode pin assignment STATIC MODE SYMBOL PIN 4 16 17, 18, 19 20 22, 21 29 LOCK RESET MODE0, MODE1, MODE2 SEL_STATIC SLICER_SEL1, SLICER_SEL0 FREQ_SEL 2003 Apr 10 LEVEL DESCRIPTION LOW IEC 60958 decoder out of lock (when SPDIF input) or clock regeneration out of lock (I2S-bus input) HIGH IEC 60958 decoder in lock (when SPDIF input) or clock regeneration in lock (I2S-bus input) LOW normal operation HIGH reset − select application mode; see Table 10 HIGH static pin control LOW microcontroller mode LOW, LOW IEC 60958 input from pin SPDIF0 LOW, HIGH IEC 60958 input from pin SPDIF1 HIGH, LOW IEC 60958 input from pin SPDIF2 HIGH, HIGH IEC 60958 input from pin SPDIF3 LOW select 44.1 kHz sampling frequency for the crystal oscillator, note 1 MID select 32 kHz sampling frequency for the crystal oscillator, note 1 HIGH select 48 kHz sampling frequency for the crystal oscillator, note 1 19 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface STATIC MODE SYMBOL PIN 30, 31 44 UDA1355H LEVEL SFOR1, SFOR0 DESCRIPTION LOW, LOW set I2S-bus format for digital data input and output interface LOW, HIGH set LSB-justified 16 bits format for digital data input interface and MSB-justified format for digital data output interface HIGH, LOW set LSB-justified 24 bits format for digital data input interface and MSB-justified format for digital data output interface HIGH, HIGH set MSB-justified format for digital data input and output interface MUTE LOW normal operation HIGH mute active Note 1. FPLL 256fs is output from pin CLKOUT in PLL locked static mode. 8.2 Static mode basic applications The static application modes are selected with the pins MODE2, MODE1 and MODE0, with pin MODE0 being a 3-level pin. In Table 10, the encoding of the pins MODE[2:0] is given. Table 10 Static mode basic applications MODE SELECTION PINS(1) MODE CLOCK(2) I2S-BUS I2S-BUS PLL LOCKS ON INPUT MODE2 MODE1 MODE0 SPDIF INPUT SPDIF OUTPUT ADC DAC INPUT SLAVE OUTPUT MASTER 0 L L L PLL PLL − PLL − PLL SPDIF 1 L L M − PLL − PLL PLL − I2S-bus 2 L L H PLL PLL − PLL PLL PLL SPDIF 3 L H L − xtal xtal − − xtal − 4 L H M − xtal xtal xtal xtal xtal − 5 L H H − xtal xtal xtal xtal xtal − 6 H L L − PLL xtal PLL PLL xtal I2S-bus 7 H L M PLL xtal xtal PLL − xtal SPDIF 8 H L H − xtal xtal PLL PLL xtal I2S-bus 9 H H L PLL xtal − xtal xtal PLL SPDIF 10 H H M PLL xtal − PLL xtal PLL SPDIF 11 H H H not used Notes 1. In column mode selection pins means: L: pin at 0 V; M: pin at half VDDD; H: pin at VDDD. 2. In column clock means: xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL. 2003 Apr 10 20 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H The first 11 application modes are given in this section. Schematic diagrams of these application modes are given in Table 11. In this table the basic features are mentioned and also the extra features in case of microcontroller mode are given. It should be noted that the blocks running at the crystal clock (XTAL) are marked unshaded while the blocks running at the PLL clock are shaded. Table 11 Overview of static mode basic applications MODE 0 FEATURES SCHEMATIC Data path: • Input SPDIF to outputs DAC, I2S or SPDIFOUT via loop through. Features: PLL SPDIF LOCK • System locks onto the SPDIF input signal MUTE DAC • BCK and WS are master SPDIFOUT • Microcontroller mode: SPDIF IN I2S OUTPUT – DAC sound features can be used – SPDIF input channel status bits (two times 40 bits) can be read. 1 I 2S master MGU836 Data path: • Input I2S to outputs DAC or SPDIF (level II not guaranteed: depends on I2S-bus clock). PLL I 2S LOCK MUTE Features: • System locks onto the WSI signal DAC • BCKI and WSI are slave • Microcontroller mode: – DAC sound features can be used SPDIF OUT I 2S slave – SPDIF output channel status bits (two times 40 bits) setting. 2003 Apr 10 I2S INPUT MGU837 21 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 2 UDA1355H FEATURES SCHEMATIC Data path: • Input SPDIF to outputs I2S or SPDIFOUT via loop through • Input I2S to output DAC. SPDIF LOCK PLL MUTE Features: DAC • Possibility to process input SPDIF via I2S-bus using an external DSP and then to output DAC SPDIFOUT SPDIF IN • System locks onto the SPDIF input signal I2S INPUT I 2S OUTPUT I 2S slave • I2S input and output with BCK and WS are master I 2S master EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) • Microcontroller mode: see Section 8.4. MGU838 3 Data path: • Input ADC to outputs I2S or SPDIF. Features: • Crystal oscillator generates the clocks XTAL • Microcontroller mode: ADC – PGA gain setting – Volume control in decimator setting SPDIF OUT – SPDIF output channel status bits (two times 40 bits) setting. I 2S OUTPUT I 2S master MGU839 4 Data path: • Input ADC to output I2S • Input I2S to outputs DAC or SPDIF. XTAL MUTE Features: ADC • Possibility to process input ADC via I2S-bus using a external DSP and then to outputs DAC or SPDIF DAC SPDIF OUT • Crystal oscillator generates the clocks I 2S INPUT • I2S input and output with BCK and WS are master I 2S OUTPUT I 2S slave • Microcontroller mode: see Section 8.4. I 2S master EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU840 2003 Apr 10 22 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 5 UDA1355H FEATURES SCHEMATIC Data path: • Input ADC to outputs I2S or SPDIF • Input I2S to output DAC. XTAL Features: MUTE • Possibility to process input ADC via I2S-bus using an external DSP and then to output DAC ADC DAC SPDIF OUT • Crystal oscillator generates the clocks I2S INPUT • I2S input and output with BCK and WS are master I 2S OUTPUT I 2S slave • Microcontroller mode: see Section 8.4. I 2S master EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU841 6 Data path: • Input ADC to output I2S • Input I2S to outputs DAC or SPDIF (level II not guaranteed: depends on I2S-bus clock). PLL XTAL ADC Features: • Possibility to process input ADC via I2S-bus using an external DSP and then to outputs DAC or SPDIF I 2S LOCK MUTE DAC SPDIF OUT I2S INPUT • Crystal oscillator generates the clocks for input ADC and output I2S I 2S OUTPUT I 2S slave I 2S master • WSI is slave EXTERNAL DSP (SAA7715) • WSO is master • Microcontroller mode: see Section 8.4. 2003 Apr 10 MGU842 23 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 7 UDA1355H FEATURES SCHEMATIC Data path: • Input SPDIF to output DAC • Input ADC to outputs SPDIF or I2S. Features: • Crystal oscillator generates the clocks for outputs SPDIF and I2S XTAL SPDIF LOCK PLL MUTE • PLL locks onto the SPDIF input signal ADC • WS of I2S output is master DAC • Microcontroller mode: SPDIF IN – Decimator features can be used SPDIF OUT I 2S OUTPUT – DAC sound features can be used – SPDIF input channel status bits (two times 40 bits) can be read I 2S master MGU843 – SPDIF output channel status bits (two times 40 bits) setting. 8 Data path: • Input ADC to outputs SPDIF or I2S • Input I2S to output DAC. Features: XTAL • Possibility to process input ADC, via I2S-bus using an external DSP and then to output DAC PLL I 2S LOCK MUTE ADC DAC • Crystal oscillator generates the clocks for outputs SPDIF and I2S SPDIF OUT • WSI is slave I2S INPUT I 2S OUTPUT • WSO master I 2S slave • Microcontroller mode: EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715) – Decimator features can be used – DAC sound features can be used MGU844 – SPDIF output channel status bits (two times 40 bits) setting. 2003 Apr 10 I 2S master 24 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 9 UDA1355H FEATURES SCHEMATIC Data path: • Input SPDIF to output I2S • Input I2S to outputs DAC or SPDIF. Features: XTAL SPDIF LOCK PLL • Possibility to process input SPDIF, via I2S-bus using an external DSP and then to outputs DAC or SPDIF MUTE DAC SPDIF IN • BCK and WS being master for both I2S input and output (different clocks) SPDIF OUT I2S INPUT • Input I2S to outputs DAC and SPDIF; BCK and WS being master; clocks based on crystal oscillator I 2S OUTPUT I 2S slave I 2S master EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715) • Microcontroller mode: – DAC sound features can be used MGU845 – SPDIF output channel status bits (two times 40) setting. 10 Data path: • Input SPDIF to output DAC or I2S • Input I2S-bus to output SPDIF. Features: • Possibility to process input SPDIF, via I2S-bus using an external DSP and then to output SPDIF XTAL DAC SPDIF IN SPDIF OUT I2S • Input I2S to output SPDIF; BCK and WS being master; clocks are generated by the crystal oscillator – SPDIF input channel status bits (two times 40) can be read 13 See microcontroller mode 14 See microcontroller mode 15 Not used 2003 Apr 10 I 2S master MGU846 – SPDIF output channel status bits (two times 40) setting. See microcontroller mode I 2S OUTPUT EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715) – DAC sound features can be used Not used INPUT I 2S slave • Microcontroller mode: 12 SPDIF LOCK MUTE • Input SPDIF to outputs I2S and DAC; locking onto the SPDIF input signal; BCK and WS being master 11 PLL 25 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 8.3 UDA1355H Microcontroller mode pin assignment In microcontroller mode all features become available, such as volume control, PGA gain and mixing (in some modes). The pin functions are defined in Table 12. Table 12 Microcontroller mode pin assignment PIN 4 SYMBOL L3-BUS LOCK SYMBOL I2C-BUS LOCK 16 RESET RESET 17 no function no function 18 A0 A0 19 U_RDY U_RDY 20 SEL_STATIC SEL_STATIC 21 USER USER 22 AC3 AC3 LEVEL DESCRIPTION LOW FPLL and SPDIF are out of LOCK HIGH FPLL in lock when SPDIF is not used; FPLL or SPDIF in lock when SPDIF is used LOW normal operation HIGH reset LOW connect to ground − A0 address input/output bit (for microcontroller register) LOW user bit stable HIGH new user bit MID I2C-bus mode LOW L3-bus mode HIGH static mode − user bit output (new bit every SPDIF sub-frame) LOW no I2S-bus data preamble detected HIGH I2S-bus data preamble detected 29 L3MODE no function − L3MODE for L3-bus mode; no function for I2C-bus 30 L3CLOCK SCL − L3CLOCK for L3-bus mode or SCL for I2C-bus mode 31 L3DATA SDA − L3DATA for L3-bus mode or SDA for I2C-bus mode 44 MUTE MUTE 2003 Apr 10 LOW no mute HIGH mute active 26 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 8.4 UDA1355H Microcontroller mode applications In Table 13, the encoding of bits MODE[3:0] in the microcontroller mode is given. Table 13 Microcontroller mode applications CLOCK(1) MODE BITS MODE I2S-BUS I2S-BUS PLL LOCKS ON INPUT MODE[3:0] SPDIF INPUT SPDIF OUTPUT ADC DAC INPUT SLAVE OUTPUT MASTER 0 0000 PLL PLL − PLL - PLL 1 0001 − PLL − PLL PLL − 2 0010 PLL PLL PLL PLL PLL PLL SPDIF 3 0011 − xtal xtal − − xtal − SPDIF I2S 4 0100 − xtal xtal xtal xtal xtal − 5 0101 − xtal xtal xtal xtal xtal − 6 0110 − PLL xtal PLL PLL xtal I 2S 7 0111 PLL xtal xtal PLL − xtal SPDIF 8 1000 − xtal xtal PLL PLL xtal I2S 9 1001 PLL xtal xtal xtal xtal PLL SPDIF 10 1010 PLL xtal PLL PLL xtal PLL SPDIF 11 1011 12 1100 PLL xtal xtal not used PLL PLL xtal SPDIF 13 1101 PLL PLL xtal PLL PLL xtal SPDIF 14 1110 − PLL PLL PLL PLL PLL I2S 15 1111 not used Note 1. In column clock means: xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL. 2003 Apr 10 27 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H In the microcontroller mode, more features are available. The application modes are given in Table 14. Some modes are the same in terms of data path as for the static mode. These modes are already explained in Section 8.2. Some modes are combined into one mode (like modes 4 and 5). Table 14 Overview of microcontroller modes MODE FEATURE 0 See static mode 1 See static mode 2 Data path: SCHEMATIC • Inputs ADC, I2S and SPDIF to outputs DAC, I2S or SPDIF. SPDIF LOCK PLL Features: ADC MUTE • All clocks are related to the SPDIF clock DAC • I2S input and output have master BCK and WS SPDIF IN • SPDIF input channel status bits (two times 40) can be read SPDIF OUT SPDIF OUT • Output SPDIF supported but the timing not according to level II: depends on I2S-bus clock I 2S OUTPUT I2S INPUT • Output SPDIFOUT loop through can be selected with independent SPDIF input channel select. I 2S slave I 2S master EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU847 3 4+5 See static mode Data path: • Inputs ADC and I2S to outputs DAC, I2S or SPDIF. XTAL Features: ADC • Mode 4 and 5 are combined in microcontroller mode MUTE DAC • Crystal oscillator generates the clocks • I2S input and output have master BCK and WS SPDIF OUT • SPDIF output channel status bits (two times 40) setting. I2S INPUT I 2S OUTPUT I 2S slave I 2S master EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU848 2003 Apr 10 28 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE UDA1355H FEATURE 6 See static mode 7 See static mode 8 See static mode 9 Data path: SCHEMATIC • Inputs ADC and I2S to outputs DAC or SPDIF • Input SPDIF to output I2S. XTAL PLL SPDIF LOCK Features: MUTE • Input SPDIF to output I2S with BCK and WS being master; the clocks for this are recovered from the SPDIF input signal ADC DAC • The rest of the clocks are generated by the crystal oscillator • SPDIF input channel status bits (two times 40) can be read SPDIF OUT I2S INPUT I 2S OUTPUT I2S slave • SPDIF output channel status bits (two times 40) setting I2S master EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715) • Possibility to process input SPDIF, via I2S-bus using an external DSP and then to outputs DAC or SPDIF. 10 SPDIF IN MGU849 Data path: • Inputs ADC and SPDIF to outputs DAC or I2S XTAL PLL SPDIF LOCK • Input I2S to output SPDIF. MUTE Features: ADC DAC • BCK and WS are master • SPDIF input channel status bits (two times 40) can be read • SPDIF output channel status bits (two times 40) setting • Possibility to process inputs ADC or SPDIF, via I2S-bus using an external DSP and then to output SPDIF. SPDIF IN SPDIF OUT I2S INPUT I 2S OUTPUT I 2S slave I 2S master EXTERNAL DSP (e.g. Sample Rate Convertor) (SAA7715) MGU850 11 Not used 2003 Apr 10 29 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 12 UDA1355H FEATURE SCHEMATIC Data path: • Input ADC to outputs I2S or SPDIF • Inputs I2S and SPDIF to output DAC. Features: XTAL PLL SPDIF LOCK • BCK and WS of I2S output are master MUTE • Inputs SPDIF and I2S to output DAC with mixing/selection possibility; clocks are generated from SPDIF input signal, and BCK and WS are master • SPDIF input channel status bits (two times 40) can be read ADC DAC SPDIF IN SPDIF OUT I 2S slave I 2S OUTPUT I2S INPUT • SPDIF output channel status bits (two times 40) setting. 13 I 2S master MGU851 Data path: • Input ADC to output I2S XTAL and SPDIF to outputs DAC • Inputs or SPDIF. I2S SPDIF LOCK PLL MUTE ADC Features DAC • BCK and WS being master SPDIF IN • SPDIF input channel status bits (two times 40) can be read • Output SPDIF supported but the timing not according to level II • Output SPDIFOUT loop through can be selected with independent SPDIF input channel select. 14 SPDIF OUT SPDIF OUT I 2S slave I 2S OUTPUT I 2S master I2S INPUT MGU852 Data path: • Inputs ADC and I2S to outputs DAC SPDIF and I2S. PLL Features: I 2S LOCK ADC • All clocks are related to WS signal of I2S-bus input MUTE DAC • Master BCK and WS for I2S output; slave BCK and WS for I2S input • SPDIF output channel status bits (two times 40) can be set; level II timing depends on the I2S-bus clocks. SPDIF OUT I 2S slave I2S INPUT I 2S OUTPUT MGU853 15 Not used 2003 Apr 10 30 I 2S master NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 9 9.1 SPDIF SIGNAL FORMAT 9.2 SPDIF channel encoding UDA1355H SPDIF hierarchical layers The SPDIF signal format is shown in Fig.12. A PCM signal is transmitted in sequential blocks. Each block consists of 192 frames. Each frame contains two sub-frames, one for each channel. Each subframe is preceded by a preamble. There are three types of preambles: B, M and W. Preambles can be spotted easily in an SPDIF bitstream because these sequences never occur in the channel parts of a valid SPDIF bitstream. The digital signal is coded using Biphase Mark Code (BMC), which is a kind of phase modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. An example of the encoding is given in Fig.11. The sub-frame format is represented by Fig.13. A sub-frame contains a single audio sample word which may be 24 bits wide, a validity bit which indicates whether the sample is valid, a bit containing user data, a bit indicating the channel status and a parity bit for this sub-frame. handbook, halfpage clock data The data bits 31 to 4 in each sub-frame are encoded using a BMC scheme. The sync preamble contains a violation of the BMC scheme and can be detected. Table 15 indicates the values of the preambles. BMC MGU606 Fig.11 Biphase mark encoding. handbook, full pagewidth M channel 1 W channel 2 B channel 1 sub-frame frame 191 W channel 2 M channel 1 channel 2 M channel 1 W channel 2 sub-frame frame 0 frame 191 block MGU607 Fig.12 SPDIF signal format 0 handbook, full pagewidth sync preamble 3 4 7 8 L S B L S B auxiliary 27 28 M S B audio sample word V 31 U C P validity flag user data channel status parity bit MGU608 Fig.13 Sub-frame format 2003 Apr 10 31 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 15 Preambles 9.3.3 PRECEDING STATE 9.3 9.3.1 UDA1355H DUTY CYCLE CHANNEL CODING The duty cycle (see Fig.14) is defined as: 0 tH Duty cycle = --------------- × 100% tL + tH 1 B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 The duty cycle should be in the range: • 40% to 60% when the data bit is a logic 1 • 45% to 55% when the data bits are two succeeding logic 0. Timing characteristics FREQUENCY REQUIREMENTS The SPDIF specification IEC 60958 supports three levels of clock accuracy: 10 L3-BUS DESCRIPTION The exchange of data and control information between the microcontroller and the UDA1355H is accomplished through a serial hardware L3-bus interface comprising the following pins: • Level I high accuracy: Tolerance of transmitting sampling frequency shall be within 50 × 10−6 • Level II, normal accuracy: All receivers should receive a signal of 1000 × 10−6 of nominal sampling frequency • MP0: mode line with signal L3MODE • Level III, variable pitch shifted clock mode: A deviation of 12.5% of the nominal sampling frequency is possible. • MP1: clock line with signal L3CLOCK • MP2: data line with signal L3DATA. The UDA1355H inputs support level I, II, and III as specified by the IEC 60958 standard. The exchange of bytes in L3-bus mode is LSB first. The L3-bus format has two modes of operation: 9.3.2 RISE AND FALL TIMES • Address mode Rise and fall times (see Fig.14) are defined as: • Data transfer mode. tr Rise time = --------------- × 100% tL + tH Rise and fall times should be in the range: The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.15). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. • 0% to 20% when the data bit is a logic 1 Basically two types of data transfers can be defined: • 0% to 10% when the data bits are two succeeding logic 0. • Write action: data transfer to the device tf Fall time = --------------- × 100% tL + tH • Read action: data transfer from the device. 10.1 The device address consists of one byte with: tL tH handbook, halfpage • Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 16) 90% • Address bits 2 to 7 representing a 6-bit device address. 50% 10% tr tf MGU612 Fig.14 Rise, fall time and duty cycle. 2003 Apr 10 Device addressing 32 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 16 Selection of data transfer 10.3 TRANSFER BIT 0 BIT 1 0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data For writing data to a device, 4 bytes must be sent (see Table 18): • Byte 1 starting with 01 for signalling the write action to the device, followed by the device address • Byte 2 starting with 0 for signalling the write action, followed by 7 bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB The device address of the UDA1355H is given in Table 17, being the first 6 bits of the device address byte. The address can be set one of two by using pin MODE1 (pin A0 in microcontroller mode). • Byte 3 with bit D15 being the MSB • Byte 4 with bit D0 being the LSB. It should be noted that each time a new destination register address needs to be written, the device address must be sent again. Table 17 L3-bus device address 0 ADDRESS 0 0 0 Data write mode The data write mode is explained in the signal diagram of Fig.15. DOM BITS MSB UDA1355H LSB 1 A0 10.4 Data read mode Remark: When using the device address, there is often misunderstanding. This is caused by the fact that the data is sent LSB first. This means that when we use the device address in, for example the NXP L3-bus/I2C-bus bithacker’, we have to use the address like LSB → MSB. For the UDA1355H this means that the device address to be used is either 10H (010000) or 30H (110000). For reading data from the device, first a prepare read must be done and then data read. The data read mode is explained in the signal diagram of Fig.16. 10.2 • Byte 2 is sent with the register address from which data needs to be read. This byte starts with 1, which indicates that there will be a read action from the register, followed again by 7 bits for the destination address in binary format with A6 being the MSB and A0 being the LSB For reading data from a device, the following 6 bytes are involved (see Table 19): • Byte 1 with the device address including 01 for signalling the write action to the device Register addressing After sending the device address, including Data Operating Mode (DOM) bits indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. • Byte 3 with the device address including 11 is sent to the device. The 11 indicates that the device must write data to the microcontroller Basically there are three methods for register addressing: • Byte 4, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) • Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.15) • Addressing for prepare read: bit 0 is logic 1 indicating that data will be read from the register (see Fig.16) • Byte 5, sent by the device to the bus, with the data information in binary format with D15 being the MSB • Addressing for data read action: in this case the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; in case bit 0 is logic 1 the register address is invalid. 2003 Apr 10 • Byte 6, sent by the device to the bus, with the data information in binary format with D0 being the LSB. 33 L3CLOCK L3MODE device address 1 0 L3DATA register address data byte 1 data byte 2 0 MGS753 DOM bits write Fig.15 Data write mode. NXP Semiconductors Stereo audio codec with SPDIF interface 2003 Apr 10 L3 wake-up pulse after power-up 34 L3CLOCK L3MODE register address device address L3DATA 1 DOM bits read 1 1 register address data byte 1 data byte 2 0/1 valid/non-valid send by the device Fig.16 Data read mode. MGS754 UDA1355H prepare read Preliminary specification 0 1 device address NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 18 L3-bus write data FIRST IN TIME BYTE L3-BUS MODE LAST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 0 1 A0 1 0 0 0 0 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Table 19 L3-bus read data FIRST IN TIME BYTE L3-BUS MODE LAST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 0 1 A0 1 0 0 0 0 2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0 3 address device address 1 1 A0 1 0 0 0 0 4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0 5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 11 I2C-BUS DESCRIPTION 11.2 11.1 One data bit is transferred during each clock pulse (see Fig.17). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high speed I2C-bus according the NXP specification. Characteristics The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to the supply voltage (VDD) via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC the recommendation for this type of bus from NXP Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy. Bit transfer handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.17 Bit transfer on the I2C-bus. 2003 Apr 10 35 MBC621 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 11.3 Byte transfer 11.7 Each byte (8 bits) is transferred with the MSB first (see Table 20). 7 11.4 BIT 6 5 4 LSB 3 2 1 0 11.8 A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. Register address The register addresses in the I2C-bus mode are the same as in the L3-bus mode. 11.6 Acknowledgment The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.19). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. Data transfer A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. 11.5 Start and stop conditions Both data and clock line will remain HIGH when the bus in not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P); (see Fig.18). Table 20 Byte transfer MSB UDA1355H Device address The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. I2C-bus, the device Before any data is transmitted on the which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The device address can be one of two, being set by bit A0 which corresponds to pin MODE1. The UDA1355H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1355H slave address is shown in Table 21. Table 21 I2C-bus slave address DEVICE ADDRESS R/W A6 A5 A4 A3 A2 A1 A0 − 0 0 1 1 0 1 A0 0/1 handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition Fig.18 START and STOP conditions on the I2C-bus. 2003 Apr 10 36 MBC622 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.19 Acknowledge on the I2C-bus. 11.9 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1355H must start. Write cycle The write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. It is also possible to read these locations for chip status information. 5. The UDA1355H acknowledges this register address (A). 6. The microcontroller sends two bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1355H. The I2C-bus configuration for a write cycle is shown in Table 22. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a couple of two bytes. 1. The microcontroller starts with a start condition (S). 7. If repeated groups of two bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller. 2. The first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the R/W bit. 8. Finally, the UDA1355H frees the I2C-bus and the microcontroller can generate a stop condition (P). The format of the write cycle is as follows: 3. This is followed by an acknowledge (A) from the UDA1355H. Table 22 Master transmitter writes to the UDA1355H registers in the I2C mode. S DEVICE ADDRESS R/W 0011010 0 REGISTER ADDRESS A ADDR DATA 2(1) DATA 1 A MS1 A LS1 A .... acknowledge from UDA1355H Note 1. Auto increment of register address. 2003 Apr 10 37 A ..... DATA n(1) A MSn A LSn A P The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1355H. 4. After this microcontroller writes the 8-bit register address (ADDR) where the reading of the register content of the UDA1355H must start. 5. The UDA1355H acknowledges this register address (A). 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address 0011010 again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge (A) follows from the UDA1355H. 8. The UDA1355H sends two bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledged follows from the microcontroller. 9. If repeated groups of two bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge follows from the microcontroller. 10. The microcontroller stops this cycle by generating a Negative Acknowledge (NA). 38 11. Finally, the UDA1355H frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 23 Master transmitter reads from the UDA1355H registers in the I2C-bus mode S DEVICE ADDRESS R/W 0011010 0 REGISTER ADDRESS A ADDR A Sr acknowledge from UDA1355H DEVICE ADDRESS R/W 0011010 1 DATA 1 A MS1 A LS1 DATA 2(1) NXP Semiconductors The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 23 Stereo audio codec with SPDIF interface 2003 Apr 10 11.10 Read cycle DATA n(1) A ... A ... A MSn A LSn NA P acknowledge from master Note 1. Auto increment of register address. Preliminary specification UDA1355H NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 12 REGISTER MAPPING In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the mapping of the readable and writable registers is given. The explanation of the register definitions are explained in Sections 12.2 and 12.3. 12.1 Address mapping Table 24 Register map settings ADDRESS R/W DESCRIPTION System settings 00H R/W crystal clock power-on setting; crystal clock and PLL divider settings; MODE and WS detector settings; clock output setting 01H R/W I2S-bus output format settings 02H R/W I2S-bus input format settings 03H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation 04H R/W analog power and clock settings Interpolator 10H R/W master volume control settings 11H R/W mixer volume settings 12H R/W sound feature and bass boost and treble settings 13H R/W gain select; de-emphasis and mute settings 14H R/W DAC polarity; noise shaper selection; mixer; source selection; silence detector and interpolator oversampling settings 18H R mute and silence detector status read-out 19H R/W resonant bass boost coefficient k1 setting 1AH R/W resonant bass boost coefficient km setting 1BH R/W resonant bass boost coefficient a1 setting 1CH R/W resonant bass boost coefficient a2 setting 1DH R/W resonant bass boost coefficient b1 setting 1EH R/W resonant bass boost coefficient b2m setting 20H R/W ADC gain settings 21H R/W ADC mute and PGA gain settings; 22H R/W ADC polarity and DC cancellation settings 28H R Decimator mute status and overflow ADC read-out SPDIF input 30H R/W SPDIF power control and SPDIF input settings 40H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation 59H R SPDIF LOCK; bit error information and SPDIF encoder output status read-out 5AH R SPDIF input status bits 15 to 0 left channel read-out 5BH R SPDIF input status bits 31 to 16 left channel read-out 5CH R SPDIF input status bits 39 to 32 left channel read-out 2003 Apr 10 39 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface ADDRESS R/W UDA1355H DESCRIPTION 5DH R SPDIF input status bits 15 to 0 right channel read-out 5EH R SPDIF input status bits 31 to 16 right channel read-out 5FH R SPDIF input status bits 39 to 32 right channel read-out SPDIF output 50H R/W SPDIF output valid; left to right channel status bit copy; power control and SPDIF output selection setting 51H R/W SPDIF output status bits 39 to 24 left channel setting 52H R/W SPDIF output status bits 23 to 8 left channel setting 53H R/W SPDIF output status bits 7 to 0 left channel setting 54H R/W SPDIF output status bits 39 to 24 right channel setting 55H R/W SPDIF output status bits 23 to 8 right channel setting 56H R/W SPDIF output status bits 7 to 0 right channel setting 60H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation 61H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation 62H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation 63H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation 64H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation Device ID 7EH R device ID; version Software reset 7FH 12.2 R/W restore L3-bus defaults Read/write registers mapping 12.2.1 SYSTEM SETTINGS Table 25 Register address 00H BIT 15 14 Symbol EXPU − Default 0 0 1 BIT 7 6 Symbol MODE3 Default 0 2003 Apr 10 13 12 11 10 9 8 XTL_DIV3 XTL_DIV2 XTL_DIV1 XTL_DIV0 0 1 0 0 0 5 4 3 2 1 0 MODE2 MODE1 MODE0 ws_detct_EN ws_detct_set CLKOUT_ SEL1 CLKOUT_ SEL0 0 1 0 1 0 1 0 PON_XTAL XTL_DIV4 PLL 40 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 26 Description of register bits (address 00H) BIT SYMBOL DESCRIPTION 15 EXPU EXPU. Bit EXPU is reserved for manufacturers evaluation and should be kept untouched for normal operation of UDA1355H. 14 − reserved 13 PON_XTALPLL Power control crystal oscillator and PLL. If this bit is logic 0, then the crystal oscillator and PLL are turned off; if this bit is logic 1, then the crystal oscillator and PLL are running. 12 to 8 XTL_DIV[4:0] Crystal oscillator clock divider setting. Value to select the sampling frequency and the system clock output frequency (256fs or 384fs). When 256fs is selected, the master BCKI and BCKO clock frequency of digital interface running with crystal oscillator clock will be 64fs; when 384fs is selected, it will be 48fs (see Table 27). 7 to 4 MODE[3:0] Microcontroller application mode setting. Value to select the microcontroller application mode (see Table 28). 3 ws_detct_EN Word select detector enable.If this bit is logic 0, then WS detector is disabled; if this bit is logic 1, then WS detector is enabled. 2 ws_detct_set Word select detector limit setting. If this bit is logic 0, then the lower frequency limit of the WS detector is 4095 clock cycles (3 kHz); if this bit is logic 1, then the lower frequency limit of the WS detector is 2047 clock cycles (6 kHz). 1 and 0 CLKOUT_SEL[1:0] Clock output select. If these bits are 00 or 10, then the BCKI and BCKO clock frequency of digital interface running with FPLL clock will be 64fs; otherwise, it will be 48fs. The selection between 256fs and 384fs for the crystal clock output is set via the bits XTL_DIV[4:0]: 00 = FPLL clock 256fs 01 = FPLL clock 384fs 10 = crystal clock 11 = crystal clock Table 27 Crystal oscillator output frequencies XTL_DIV4 XTL_DIV3 XTL_DIV2 XTL_DIV1 XTL_DIV0 OUTPUT RATE Based on 32 kHz 0 0 0 0 0 256 × 16 kHz 0 0 0 0 1 384 × 16 kHz 0 0 0 1 0 256 × 32 kHz 0 0 0 1 1 384 × 32 kHz 0 0 1 0 0 256 × 64 kHz 0 0 1 0 1 384 × 64 kHz 0 0 1 1 0 256 × 22.05 kHz 0 0 1 1 1 384 × 22.05 kHz Based on 44.1 kHz 0 1 0 0 0 256 × 44.1 kHz 0 1 0 0 1 384 × 44.1 kHz 0 1 0 1 0 256 × 88.2 kHz 0 1 0 1 1 384 × 88.2 kHz 2003 Apr 10 41 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface XTL_DIV4 XTL_DIV3 XTL_DIV2 XTL_DIV1 UDA1355H XTL_DIV0 OUTPUT RATE Based on 48 kHz 0 1 1 0 0 256 × 24 kHz 0 1 1 0 1 384 × 24 kHz 0 1 1 1 0 256 × 48 kHz 0 1 1 1 1 384 × 48 kHz 1 0 0 0 0 256 × 96 kHz 1 0 0 0 1 384 × 96 kHz Table 28 Application mode selection MODE3 MODE2 MODE1 MODE0 FUNCTION 0 0 0 0 mode 0 0 0 0 1 mode 1 0 0 1 0 mode 2 0 0 1 1 mode 3 0 1 0 0 mode 4 0 1 0 1 mode 5 0 1 1 0 mode 6 0 1 1 1 mode 7 1 0 0 0 mode 8 1 0 0 1 mode 9 1 0 1 0 mode 10 1 0 1 1 mode 11 1 1 0 0 mode 12 1 1 0 1 mode 13 1 1 1 0 mode 14 1 1 1 1 mode 15 Table 29 Register address 01H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − MUTE_DAO Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol PON_DIGO − DIGOUT1 DIGOUT0 − SFORO2 SFORO1 SFORO0 Default 1 0 1 0 0 0 0 0 2003 Apr 10 42 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 30 Description of register bits (address 01H) BIT SYMBOL DESCRIPTION − reserved 8 MUTE_DAO Digital mute setting. If this bit is logic 0, then the digital output is not muted; if this bit is logic 1, then the digital output is muted. 7 PON_DIGO Power control digital output. If this bit is logic 0, then the digital output is in Power-down mode; if this bit is logic 1, then the digital output is in power-on mode. The registers have their own clock, which means that there cannot be a dead-lock situation. 6 − reserved 15 to 9 5 and 4 DIGOUT[1:0] Input selector for digital output. Value to select the input signal for the digital output. The default input will be chosen if in an application an invalid data signal is selected: 00 = ADC input 01 = digital input 10 = IEC 60958 input 11 = interpolator mixer output 3 2 to 0 − reserved SFORO[2:0] Digital output format. Value to set the digital output format: 000 = I2S-bus 001 = LSB-justified; 16 bits 010 = LSB-justified; 18 bits 011 = LSB-justified; 20 bits 100 = LSB-justified; 24 bits 101 = MSB-justified 110 = not used; output is default value 111 = not used; output is default value Table 31 Register address 02H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − − Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol PON_DIGI − − − − SFORI2 SFORI1 SFORI0 Default 1 0 0 0 0 0 0 0 Table 32 Description of register bits (address 02H) BIT 15 to 8 7 6 to 3 SYMBOL DESCRIPTION − reserved PON_DIGI Power control digital input. If this bit is logic 0, then the digital input is in Power-down mode; if this bit is logic 1, then the digital input is in power-on mode. The registers have their own clock, which means that there cannot be a dead-lock situation. − reserved 2003 Apr 10 43 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT 2 to 0 SYMBOL SFORI[2:0] UDA1355H DESCRIPTION Digital input format. Value to set the digital input format: 000 = I2S-bus 001 = LSB-justified; 16 bits 010 = LSB-justified; 18 bits 011 = LSB-justified; 20 bits 100 = LSB-justified; 24 bits 101 = MSB-justified 110 = not used; input is default value 111 = not used; input is default value Table 33 Register address 04H BIT 15 14 13 12 11 10 9 8 Symbol PON_DAC − − − − Default 1 0 0 0 0 1 1 1 BIT 7 6 5 4 3 2 1 0 Symbol DACLK_OFF DACLK_AUTO − − − EN_DEC − EN_INT Default 0 0 0 0 0 1 0 1 PON_ADCL PON_ADCR PON_ADC_bias Table 34 Description of register bits (address 04H) BIT 15 SYMBOL PON_DAC 14 to 11 − DESCRIPTION Power control DAC. If this bit is logic 0, then the DAC is in Power-down mode; if this bit is logic 1, then the DAC is in power-on mode. This bit is only connected to the DAC input and is not combined with mute status or other signals. reserved 10 PON_ADCL Power control ADC left channel. Value to set power on the ADC left channel (see Table 35). 9 PON_ADCR Power control ADC right channel. Value to set power on the ADC right channel (see Table 35). 8 PON_ADC_bias Power control ADC bias. Value to set power on the ADCs (see Table 35). 7 DACLK_OFF DAC clock enable. If this bit is logic 0, then the DAC clock is disabled; if this bit is logic 1, then the DAC clock is enabled. 6 DACLK_AUTO DAC clock auto function. If this bit is logic 0, then the DAC clock auto function is disabled; if this bit is logic 1, then the DAC clock auto function is enabled. If the FPLL is unlocked, the interpolator will be muted and the DAC clock is automatically disabled. − reserved 2 EN_DEC Decimator and ADC clock enable. If this bit is logic 0, then the clock to decimator and ADC is disabled; if this bit is logic 1, then the clock to decimator and ADC is running. 1 − reserved 0 EN_INT Interpolator clock enable. If this bit is logic 0, then the clock to interpolator and FSDAC is disabled; if this bit is logic 1, then the clock to the interpolator and FSDAC is running. 5 to 3 2003 Apr 10 44 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 35 ADC power control PON_ADC_BIAS PON_ADCR PON_ADCL 0 X X no power on both ADCs 1 0 0 no power on both ADCs 12.2.2 DESCRIPTION 1 1 0 only power on right channel ADC 1 0 1 only power on left channel ADC 1 1 1 power on both ADCs INTERPOLATOR Table 36 Register address 10H BIT 15 14 13 12 11 10 9 8 Symbol MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0 Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0 Default 0 0 0 0 0 0 0 0 Table 37 Description of register bits (address 10H) BIT SYMBOL DESCRIPTION 15 to 8 MVCL_[7:0] Master volume setting left channel. Value to program the left channel master volume attenuation. The range is 0 dB to −78 dB and ∞ dB (see Table 38). 7 to 0 MVCR_[7:0] Master volume setting right channel. Value to program the right channel master volume attenuation. The range is 0 dB to −78 dB and ∞ dB (see Table 38). Table 38 Master volume setting left and right channel MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0 MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 −0.25 0 0 0 0 0 0 1 0 −0.5 0 0 0 0 0 0 1 1 −0.75 0 0 0 0 0 1 0 0 −1 : : : : : : : : : 1 1 0 0 1 1 0 0 −51 1 1 0 0 1 1 0 1 −51.25 1 1 0 0 1 1 1 0 −51.5 1 1 0 0 1 1 1 1 −51.75 1 1 0 1 0 0 0 0 −52 VOLUME (dB) 2003 Apr 10 45 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0 MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0 1 1 0 1 0 1 0 0 −54 1 1 0 1 1 0 0 0 −56 : : : : : : : : : 1 1 1 0 1 1 0 0 −66 1 1 1 1 0 0 0 0 −69 1 1 1 1 0 1 0 0 −72 1 1 1 1 1 0 0 0 −78 1 1 1 1 1 1 0 0 −∞ VOLUME (dB) Table 39 Register address 11H BIT 15 14 13 12 11 10 9 8 Symbol VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0 Default 1 1 1 1 1 1 1 1 BIT 7 6 5 4 3 2 1 0 Symbol VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0 Default 0 0 0 0 0 0 0 0 Table 40 Description of register bits (address 11H) BIT SYMBOL DESCRIPTION 15 to 8 VC2_[7:0] Mixer volume setting channel 2. Value to program channel 2 mixer volume attenuation. The range is 0 dB to −72 dB and ∞ dB (see Table 41). 7 to 0 VC1_[7:0] Mixer volume setting channel 1. Value to program channel 1 mixer volume attenuation. The range is 0 dB to −72 dB and ∞ dB (see Table 41). Table 41 Mixer volume setting channel 1 and 2 VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0 VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0 0 0 0 0 0 0 0 0 0 VOLUME (dB) 0 0 0 0 0 0 0 1 −0.25 0 0 0 0 0 0 1 0 −0.5 0 0 0 0 0 0 1 1 −0.75 0 0 0 0 0 1 0 0 −1 : : : : : : : : : 1 0 1 1 0 1 0 0 −45 1 0 1 1 0 1 0 1 −45.25 1 0 1 1 0 1 1 0 −45.5 1 0 1 1 0 1 1 1 −45.75 1 0 1 1 1 0 0 0 −46 2003 Apr 10 46 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0 VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0 VOLUME (dB) 1 0 1 1 1 1 0 0 −48 1 1 0 0 0 0 0 0 −50 : : : : : : : : : 1 1 0 1 0 1 0 0 −60 1 1 0 1 1 0 0 0 −63 1 1 0 1 1 1 0 0 −66 1 1 1 0 0 0 0 0 −72 1 1 1 0 0 1 0 0 −∞ : : : : : : : : : 1 1 1 1 1 1 0 0 −∞ Table 42 Register address 12H BIT 15 14 13 12 11 10 9 8 Symbol M1 M0 TRL1 TRL0 BBL3 BBL2 BBL1 BBL0 Default 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Symbol BB_OFF BB_FIX TRR1 TRR0 BBR3 BBR2 BBR1 BBR0 Default 0 0 0 0 0 0 0 0 BIT Table 43 Description of register bits (address 12H) BIT 15 and 14 SYMBOL M[1:0] DESCRIPTION Sound feature mode. Value to program the sound processing filter sets (modes) of bass boost and treble: 00 = flat set 01 = minimum set 10 = minimum set 11 = maximum set 13 and 12 TRL[1:0] Treble settings left. Value to program the left channel treble setting. Both left and right channels will follow the left channel setting when bit BASS_SEL = 1. The used filter set is selected with the sound feature mode bits M1 and M2 (see Table 44). 11 to 8 BBL[3:0] Normal bass boost settings left. Value to program the left bass boost settings. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 45). 7 BB_OFF Resonant bass boost. If this bit is logic 0 then the resonant bass boost is enabled; if this bit is logic 1 then the resonant bass boost is disabled. 2003 Apr 10 47 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT SYMBOL UDA1355H DESCRIPTION 6 BB_FIX Resonant bass boost coefficient. If this bit is logic 0 then the resonant bass boost coefficient is finished loading; if this bit is logic 1 then the resonant bass boost coefficient is loading to register. 5 and 4 TRR[1:0] Treble settings right. Value to program the right treble setting. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 44). 3 to 0 BBR[3:0] Normal bass boost settings right. Value to program the right bass boost settings. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 45). Table 44 Treble settings TRL1 TRL0 TRR1 TRR0 0 FLAT SET (dB) MIN. SET (dB) MAX. SET (dB) 0 0 0 0 0 1 0 2 2 1 0 0 4 4 1 1 0 6 6 Table 45 Normal bass boost settings; note 1 BBL3 BBL2 BBL1 BBL0 BBR3 BBR2 BBR1 BBR0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 0 1 0 0 4 4 0 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 0 1 1 0 0 12 12 0 1 1 1 0 14 14 1 0 0 0 0 16 16 1 0 0 1 0 18 18 1 0 1 0 0 18 20 1 0 1 1 0 18 22 1 1 0 0 0 18 24 1 1 0 1 0 18 24 1 1 1 0 0 18 24 1 1 1 1 0 18 24 FLAT SET (dB) Note 1. The bass boost setting is only effective when bit BASS_SEL = 0. 2003 Apr 10 48 MIN SET (dB) MAX SET (dB) NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 46 Register address 13H BIT 15 14 13 12 11 10 9 8 Symbol − MTM GS MIXGAIN MT2 DE2_2 DE2_1 DE2_0 Default 0 0 0 0 1 0 0 0 7 6 5 4 3 2 1 0 Symbol MTNS1 MTNS0 WS_SEL DE_SW MT1 DE1_2 DE1_1 DE1_0 Default 0 0 0 0 0 0 0 0 BIT Table 47 Description of register bits (address 13H) BIT SYMBOL DESCRIPTION 15 - reserved 14 MTM Master mute. If this bit is logic 0 then there is no master mute or the master de-mute is in progress; if this bit is logic 1 then the master mute is in progress or muted. 13 GS Gain select. See Table 48. 12 MIXGAIN Mixer gain select. See Tables 48 and 49. 11 MT2 Channel 2 mute. If this bit is logic 0 then channel 2 is not muted or the de-mute is in progress; if this bit is logic 1 then channel 2 is muted or the muting is in progress. 10 to 8 DE2_[2:0] De-emphasis setting for channel 2. See Table 50. 7 and 6 MTNS[1:0] Interpolator mute. Selection: 00 = no mute 01 = if no WS signal is detected, the noise shaper of the interpolator mute 1x = the noise shaper of the interpolator mute 5 WS_SEL WS signal select. If this bit is logic 0 then WS_DET is selected for the WS detection; if this bit is logic 1 then FPLL is selected for the WS detection. 4 DE_SW De-emphasis select. If this bit is logic 0 then SPDIF pre-emphasis information is selected; if this bit is logic 1 then the de-emphasis setting is selected. 3 MT1 Channel 1 mute. If this bit is logic 0 then channel 1 is not muted or the de-mute is in progress; if this bit is logic 1 then channel 1 is muted or the muting is in progress. DE1_[2:0] De-emphasis setting for channel 1. See Table 50. 2 to 0 Table 48 DAC gain setting GS MIX(1) MIX_GAIN DAC GAIN (dB) 0 X(2) X(2) 0 1 0 0 6 1 1 0 0 1 0 1 6 1 1 1 6 Notes 1. See Table 52. 2. X = don’t care 2003 Apr 10 49 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 49 Mixer gain setting MIX(1) MIX_GAIN 1 0 DAC output gain is set to 0 dB and mixer signal output gain is set −6 dB 1 1 DAC output gain and mixer signal output gain are set to 0 dB MIXER OUTPUT GAIN Note 1. See Table 52. Table 50 De-emphasis setting for the incoming signal DE2_2 DE2_1 DE2_0 DE1_2 DE1_1 DE1_0 0 0 0 0 0 1 32 kHz 0 1 0 44.1 kHz 0 1 1 48 kHz 1 0 0 96 kHz FUNCTION off Table 51 Register address 14H BIT 15 14 13 12 11 10 9 8 Symbol DA_POL_ INV SEL_NS MIX_POS MIX Default 0 1 0 0 1 1 0 1 BIT 7 6 5 4 3 2 1 0 Symbol SILENCE SDET_ON SD_ VALUE1 SD_ VALUE0 BASS_SEL BYPASS OS_IN1 OS_IN0 Default 0 0 0 0 0 0 0 0 DAC_CH2_ DAC_CH2_ DAC_CH1_ DAC_CH1_ SEL1 SEL0 SEL1 SEL0 Table 52 Description of register bits (address 14H) BIT SYMBOL DESCRIPTION 15 DA_POL_INV DAC polarity control. If this bit is logic 0 then the DAC output is not inverted; if this bit is logic 1 then the DAC output is inverted. 14 SEL_NS Select noise shaper. If this bit is logic 0 then the third order noise shaper is selected; if this bit is logic 1 then the fifth order noise shaper is selected. 13 MIX_POS Mixer position. Mixing is done before or after the sound processing unit (see Table 53). 12 MIX Mixer. If this bit is logic 0 then the mixer is disabled; if this bit is logic 1 then the mixer is enabled (see Tables 48, 49 and 53). DAC_CH2_SEL[1:0] DAC channel 2 input selection. Value to select the input mode to channel 2 of the interpolator (see Table 54). 9 and 8 DAC_CH1_SEL[1:0] DAC channel 1 input selection. Value to select the input mode to channel 1 of the interpolator (see Table 54). 11 and 10 2003 Apr 10 50 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT SYMBOL UDA1355H DESCRIPTION 7 SILENCE Silence detector overrule. Value to force the DAC output to silence. This will give a plop at the output of the DAC because of mismatch in offsets and the DC offset added to the signal in the interpolator itself. If this bit is logic 0 then there is no overruling and the FSDAC silence switch setting depends on the silence detector circuit and on the status of bit MTM; if this bit is logic 1 then there is overruling and the FSDAC silence switch is activated independent of the status of the digital silence detector circuit or the status of bit MTM. 6 SDET_ON Silence detector enable. If this bit is logic 0 then the silence detection circuit is disabled; if this bit is logic 1 then the silence detection circuit is enabled. 5 and 4 SD_VALUE[1:0] Silence detector setting. Value to program the silence detector. The number of zero samples counted before the silence detector signals whether there has been digital silence: 00 = 3200 samples 01 = 4800 samples 10 = 9600 samples 11 = 19200 samples 3 BASS_SEL Bass boost select. If this bit is logic 0 then the normal bass boost function is selected; if this bit is logic 1 then the resonant bass boost function is selected. 2 BYPASS Mixer bypass mode. If this bit is logic 0 then the mixer is in mixer mode; if this bit is logic 1 then the mixer is in mixer bypass mode. 1 and 0 OS_IN[1:0] Oversampling ratio select. Value to select the oversampling input mode. This mode is only for I2S-bus input: 00 = single speed input; normal input; mixing possible 01 = double speed input; after first half-band filter; no mixing possible but volume and mute still possible 10 = quad speed input; in front of noise shaper; no mixing possible; no volume control possible 11 = reserved. Table 53 Mixer signal control signals MIX MIX_POS 0 X(1) FUNCTION 1 0 mixing is done before the sound processing; input signals are automatically scaled by 6 dB in order to prevent clipping during adding; after the addition, the 6 dB scaling is compensated 1 1 mixing is done after the sound processing; input signals are automatically scaled in order to prevent clipping during adding this is the default setting: no mixing, volume of channel 1 is forced to 0 dB and volume of channel 2 is forced to −∞ dB Note 1. X = don’t care 2003 Apr 10 51 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 54 Data source selector DAC channel 1 and 2; note 1 DAC_CH2_SEL1 DAC_CH2_SEL0 DATA OUTPUT DAC DAC_CH1_SEL1 DAC_CH1_SEL0 0 0 ADC input 0 1 I2S-bus input 1 0 IEC 60958 input 1 1 I2S-bus input Note 1. The change of the data source will take place only when the mix mode is turned on (bit MIX = 1). The channel 2 input selection is valid only when the channel 1 data source is correct. Table 55 Register addresses 19H, 1AH, 1BH, 1CH, 1DH and 1EH BIT 15 14 Symbol − − Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 BASS_x_5 BASS_x_4 BASS_x_3 BASS_x_2 0 0 0 0 Symbol 13 0 11 10 9 8 BASS_x_13 BASS_x_12 BASS_x_11 BASS_x_10 BASS_x_9 BASS_x_8 BASS_x_7 BASS_x_6 Default 12 0 BASS_x_1 BASS_x_0 0 0 Table 56 Description of register bits (addresses 19H, 1AH, 1BH, 1CH, 1DH and 1EH) BIT SYMBOL DESCRIPTION 15 and 14 − 13 to 0 12.2.3 reserved BASS_x_[13:0] Resonant bass boost coefficient x. Six 14-bit registers are used as the filter coefficients to specify the bass boost characteristics. The six coefficients are k1, km, a1, a2, b1 and b2m. A software program is available for users to generate these six 14-bit coefficients by entering the desired centre frequency, peak gain, sampling frequency and shape factor (default flat response). DECIMATOR SETTINGS Table 57 Register address 20H BIT 15 14 13 12 11 10 9 8 Symbol MA_ DECL7 MA_ DECL6 MA_ DECL5 MA_ DECL4 MA_ DECL3 MA_ DECL2 MA_ DECL1 MA_ DECL0 Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol MA_ DECR7 MA_ DECR6 MA_ DECR5 MA_ DECR4 MA_ DECR3 MA_ DECR2 MA_ DECR1 MA_ DECR0 Default 0 0 0 0 0 0 0 0 2003 Apr 10 52 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 58 Description of register bits (address 20H) BIT SYMBOL DESCRIPTION 15 to 8 MA_DECL[7:0] ADC volume setting left channel. Value to program the ADC gain setting for the left channel. The range is from +24 to −63 dB and −∞ dB (see Table 59). 7 to 0 MA_DECR[7:0] ADC volume setting right channel. Value to program the ADC gain setting for the right channel. The range is from +24 to −63 dB and −∞ dB (see Table 59). Table 59 ADC volume control settings MA_ DECL7 MA_ DECL6 MA_ DECL5 MA_ DECL4 MA_ DECL3 MA_ DECL2 MA_ DECL1 MA_ DECL0 MA_ DECR7 MA_ DECR6 MA_ DECR5 MA_ DECR4 MA_ DECR3 MA_ DECR2 MA_ DECR1 MA_ DECR0 0 0 1 1 0 0 0 0 +24.0 0 0 1 0 1 1 1 1 +23.5 0 0 1 0 1 1 1 0 +23.0 : : : : : : : : : 0 0 0 0 0 0 1 0 +1.0 0 0 0 0 0 0 0 1 +0.5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 −0.5 GAIN (dB) : : : : : : : : : 1 0 0 0 0 1 0 0 −62.0 1 0 0 0 0 0 1 1 −62.5 1 0 0 0 0 0 1 0 −63.0 1 0 0 0 0 0 0 1 −63.5 1 0 0 0 0 0 0 0 −∞ Table 60 Register address 21H BIT 15 14 13 12 Symbol MT_ADC − − − Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol − − − − Default 0 0 0 0 2003 Apr 10 11 10 9 8 PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ CTRLL3 CTRLL2 CTRLL1 CTRLL0 PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ PGA_GAIN_ CTRLR0 CTRLR3 CTRLR2 CTRLR1 0 53 0 0 0 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 61 Description of register bits (address 21H) BIT 15 SYMBOL DESCRIPTION MT_ADC Mute ADC. If this bit is logic 0 then the ADC is not muted; if this bit is logic 1 then the ADC is muted. 14 to 12 − reserved 11 to 8 PGA_GAIN_CTRLL[3:0] PGA gain control left channel. Value to program the gain of the left input amplifier. There are nine settings (see Table 62). 7 to 4 − reserved 3 to 0 PGA_GAIN_CTRLR[3:0] PGA gain control right channel. Value to program the gain of the right input amplifier. There are nine settings (see Table 62). Table 62 ADC input amp PGA gain settings PGA_GAIN_ CTRLL3 PGA_GAIN_ CTRLL2 PGA_GAIN_ CTRLL1 PGA_GAIN_ CTRLL0 PGA_GAIN_ CTRLR3 PGA_GAIN_ CTRLR2 PGA_GAIN_ CTRLR1 PGA_GAIN_ CTRLR0 0 0 0 0 0 0 0 0 1 3 0 0 1 0 6 0 0 1 1 9 0 1 0 0 12 0 1 0 1 15 0 1 1 0 18 0 1 1 1 21 1 0 0 0 24 GAIN (dB) Table 63 Register address 22H BIT 15 14 13 12 11 10 9 8 Symbol − − − ADCPOL_INV − − − − Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol − − − − − − DC_SKIP HP_EN_DEC Default 0 0 0 0 0 0 1 1 Table 64 Description of register bits (address 22H) BIT SYMBOL 15 to 13 − 12 ADCPOL_INV 2003 Apr 10 DESCRIPTION reserved ADC polarity control. If this bit is logic 0 then the ADC input is not inverted; if this bit is logic 1 then the ADC input is inverted. 54 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT UDA1355H SYMBOL DESCRIPTION − reserved 1 DC_SKIP DC filter skip. If this bit is logic 0 then the DC filter is enabled; if this bit is logic 1 then the DC filter is disabled. The DC filter is at the output of the comb filter just before the decimator. This DC filter compensates for the DC offset added in the ADC (to remove idle tones from the audio band). This DC offset must not be amplified in order to prevent clipping. 0 HP_EN_DEC High-pass enable. If this bit is logic 0 then the high-pass is disabled; if this bit is logic 1 then the high-pass is enabled. The high-pass is a DC filter which is at the output of the decimation filter (running at fs). 11 to 2 12.2.4 SPDIF INPUT SETTINGS Table 65 Register address 30H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − − Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol − − − PON_SPDI − − SLICER_SEL1 SLICER_SEL0 Default 0 0 0 1 0 0 0 0 Table 66 Description of register bits (address 30H) BIT 15 to 5 4 SYMBOL DESCRIPTION − reserved PON_SPDI Power control SPDIF input. If this bit is logic 0 then the SPDIF input is switched to Power-down mode; if this bit is logic 1 then the SPDIF input is switched to power-on mode. 3 and 2 − reserved 1 and 0 SLICER_SEL[1:0] SPDIF source select. Value to select an IEC 60958 input channel: 00 = IEC 60958 input from pin SPDIF0 01 = IEC 60958 input from pin SPDIF1 10 = IEC 60958 input from pin SPDIF2 11 = IEC 60958 input from pin SPDIF3 2003 Apr 10 55 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 12.2.5 UDA1355H SPDIF OUTPUT SETTINGS Table 67 Register address 50H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − SPDO_ VALID Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol − L_r_copy − Default 0 1 0 PON_SPDO DIS_SPDO SPDOUT_SEL2 SPDOUT_SEL1 SPDOUT_SEL0 1 0 1 0 0 Table 68 Description of register bits (address 50H) BIT SYMBOL 15 to 9 − DESCRIPTION reserved 8 SPDO_VALID SDPDIF output valid. If this bit is logic 0 then the SPDIF output is invalid; if this bit is logic 1 then the SPDIF output is valid. 7 − reserved 6 L_r_copy SPDIF channel status copy. If this bit is logic 0 then the status bits of the left channel are not copied to the right channel; if this bit is logic 1 then the status bits of the left channel are copied to the right channel. 5 − reserved 4 PON_SPDO Power control of SPDIF output. If this bit is logic 0 then the SPDIF output is switched to Power-down mode; if this bit is logic 1 then the SPDIF output is switched to power-on mode. 3 DIS_SPDO SPDIF encoder enable. If this bit is logic 0 then the SPDIF encoder is enabled; if this bit is logic 1 then the SPDIF encoder is disabled. SPDOUT_SEL[2:0] SPDIF output source selector. Value to select the input source for SPDIF output. The selection option to select the SPDIF input just after the slicer was already there. Added is an independent selection of the input signals SPDIF0 to SPDIF3: 2 to 0 000 = ADC 001 = I2S-bus input 010 = not used 011 = interpolator mix output 100 = SPDIF0 loop through 101 = SPDIF1 loop through 110 = SPDIF2 loop through 111 = SPDIF3 loop through 2003 Apr 10 56 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 69 Register addresses 51H (left) and 54H (right) BIT 15 14 13 12 11 10 9 8 Symbol SPDO_ BIT39 SPDO_ BIT38 SPDO_ BIT37 SPDO_ BIT36 SPDO_ BIT35 SPDO_ BIT34 SPDO_ BIT33 SPDO_ BIT32 Default 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Symbol SPDO_ BIT31 SPDO_ BIT30 SPDO_ BIT29 SPDO_ BIT28 SPDO_ BIT27 SPDO_ BIT26 SPDO_ BIT25 SPDO_ BIT24 Default 0 0 0 0 0 0 0 0 BIT Table 70 Register addresses 52H (left) and 55H (right) BIT 15 14 13 12 11 10 9 8 Symbol SPDO_ BIT23 SPDO_ BIT22 SPDO_ BIT21 SPDO_ BIT20 SPDO_ BIT19 SPDO_ BIT18 SPDO_ BIT17 SPDO_ BIT16 Default 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Symbol SPDO_ BIT15 SPDO_ BIT14 SPDO_ BIT13 SPDO_ BIT12 SPDO_ BIT11 SPDO_ BIT10 SPDO_ BIT9 SPDO_ BIT8 Default 0 0 0 0 0 0 0 0 BIT Table 71 Register addresses 53H (left) and 56H (right) BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − − Default 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Symbol SPDO_ BIT7 SPDO_ BIT6 SPDO_ BIT5 SPDO_ BIT4 SPDO_ BIT3 SPDO_ BIT2 SPDO_ BIT1 SPDO_ BIT0 Default 0 0 0 0 0 0 0 0 BIT Table 72 Description of register bits BIT SYMBOL DESCRIPTION 39 to 36 SPDO_BIT[39:36] reserved 35 to 33 SPDO_BIT[35:33] Word length. Value indicating the word length (see Table 73). SPDO_BIT[32] Audio sample word length. Value to signal the maximum audio sample word length. If bit 32 is logic 0, then the maximum length is 20 bits; if bit 32 is logic 1, then the maximum length is 24 bits (see Table 73). SPDO_BIT[31:30] reserved 32 31 to 30 2003 Apr 10 57 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT SYMBOL 29 to 28 SPDO_BIT[29:28] UDA1355H DESCRIPTION Clock accuracy. Value indicating the clock accuracy: 00 = level II 01 = level I 10 = level III 11 = reserved 27 to 24 SPDO_BIT[27:24] Sample frequency. Value indicating the sampling frequency: 0000 = 44.1 kHz 0001 = 48 kHz 0010 = 32 kHz other states = reserved 23 to 20 SPDO_BIT[23:20] Channel number. Value indicating the channel number (see Table 74). 19 to 16 SPDO_BIT[19:16] Source number. Value indicating the source number (see Table 75). 15 to 8 SPDO_BIT[15:8] General information. Value indicating general information (see Table 76). 7 to 6 SPDO_BIT[7:6] Mode. Value indicating mode 0: 00 = mode 0 other states = reserved 5 to 3 SPDO_BIT[5:3] Audio sampling. Value indicating the type of audio sampling (linear PCM). For bit SPDO_BIT1 = 0: 000 = two audio samples without pre-emphasis 001 = two audio samples with 50/15 μs pre-emphasis 010 = reserved (two audio samples with pre-emphasis) 011 = reserved (two audio samples with pre-emphasis) other states = reserved 2 SPDO_BIT2 Software copyright. Value indicating software for which copyright is asserted or not. If this bit is logic 0, then copyright is asserted; if this bit is logic 1, then no copyright is asserted. 1 SPDO_BIT1 Audio sample word. Value indicating the type of audio sample word. If this bit is logic 0, then the audio sample word represents linear PCM samples; if this bit is logic 1, then the audio sample word is used for other purposes. 0 SPDO_BIT0 Channel status. Value indicating the consumer use of the status block. This bit is logic 0. Table 73 Word length SPDO_BIT32 SPDO_BIT35 SPDO_BIT34 SPDO_BIT33 0 0 0 0 not indicated 0 0 0 1 16 bits 0 0 1 0 18 bits 0 0 1 1 reserved 0 1 0 0 19 bits 0 1 0 1 20 bits 0 1 1 0 17 bits 0 1 1 1 reserved 2003 Apr 10 58 WORD LENGTH NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H SPDO_BIT32 SPDO_BIT35 SPDO_BIT34 SPDO_BIT33 WORD LENGTH 1 0 0 0 indicated 1 0 0 1 20 bits 1 0 1 0 22 bits 1 0 1 1 reserved 1 1 0 0 23 bits 1 1 0 1 24 bits 1 1 1 0 21 bits 1 1 1 1 reserved SPDO_BIT23 SPDO_BIT22 SPDO_BIT21 SPDO_BIT20 0 0 0 0 don’t care 0 0 0 1 A (left for stereo transmission) 0 0 1 0 B (right for stereo transmission) 0 0 1 1 C 0 1 0 0 D 0 1 0 1 E 0 1 1 0 F 0 1 1 1 G 1 0 0 0 H 1 0 0 1 I 1 0 1 0 J 1 0 1 1 K 1 1 0 0 L 1 1 0 1 M 1 1 1 0 N 1 1 1 1 O SPDO_BIT19 SPDO_BIT18 SPDO_BIT17 SPDO_BIT16 0 0 0 0 don’t care 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 Table 74 Channel number CHANNEL NUMBER Table 75 Source number 2003 Apr 10 59 SOURCE NUMBER NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H SPDO_BIT19 SPDO_BIT18 SPDO_BIT17 SPDO_BIT16 SOURCE NUMBER 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Table 76 General information SPDO_BIT[15:8] 12.3 FUNCTION 00000 000 general Lxxxx 001 laser optical products Lxxxx 010 digital-to-digital converters and signal processing products Lxxxx 011 magnetic tape or disc based products Lxxxx 100 broadcast reception of digitally encoded audio signals with video signals Lxxxx 110 broadcast reception of digitally encoded audio signals without video signals Lxxxx 101 musical instruments, microphones and other sources without copyright information Lxx00 110 analog-to-digital converters for analog signals without copyright information Lxx10 110 analog-to-digital converters for analog signals which include copyright information in the form of Cp- and L-bit status Lxxx1 000 solid state memory based products L1000 000 experimental products not for commercial sale Lxxxx 111 reserved Lxxx0 000 reserved, except 000 0000 and 000 0001L Read registers mapping 12.3.1 INTERPOLATOR Table 77 Register address 18H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − − BIT 7 6 5 4 3 2 1 0 Symbol − 2003 Apr 10 SDETR2 SDETL2 SDETR1 SDETL1 MUTE_STATE_M MUTE_STATE_CH2 MUTE_STATE_CH1 60 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 78 Description of register bits (address 18H) BIT SYMBOL DESCRIPTION − reserved 6 SDETR2 Silence detector channel 2 right. If this bit is logic 0 then there is no silence detection for the right input of channel 2; if this bit is logic 1 then there is silence detection for the right input of channel 2. 5 SDETL2 Silence detector channel 2 left. If this bit is logic 0 then there is no silence detection for the left input of channel 2; if this bit is logic 1 then there is silence detection for the left input of channel 2. 4 SDETR1 Silence detector channel 1 right. If this bit is logic 0 then there is no silence detection for the right input of channel 1; if this bit is logic 1 then there is silence detection for the right input of channel 1. 3 SDETL1 Silence detector channel 1 left. If this bit is logic 0 then there is no silence detection for the left input of channel 1; if this bit is logic 1 then there is silence detection for the left input of channel 1. 2 MUTE_STATE_M Mute status interpolator. If this bit is logic 0 then the interpolator is not muted; if this bit is logic 1 then the interpolator is muted. 1 MUTE_STATE_CH2 Mute status channel 2. If this bit is logic 0 then the interpolator channel 2 is not muted; if this bit is logic 1 then the interpolator channel 2 is muted. 0 MUTE_STATE_CH1 Mute status channel 1. If this bit is logic 0 then the interpolator channel 1 is not muted; if this bit is logic 1 then the interpolator channel 1 is muted. 15 to 7 12.3.2 DECIMATOR Table 79 Register address 28H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − − BIT 7 6 5 4 3 2 1 0 Symbol − − − − − MT_ADC_stat − OVERFLOW Table 80 Description of register bits (address 28H) BIT SYMBOL DESCRIPTION − reserved 2 MT_ADC_stat Mute status decimator. If this bit is logic 0 then the decimator is not muted; if this bit is logic 1 then the decimator is muted. 1 − reserved 0 OVERFLOW Overflow decimator. If this bit is logic 0 then there is no overflow in the decimator (digital level above −1.16 dB.); if this bit is logic 1 then there is an overflow in the decimator. 15 to 3 2003 Apr 10 61 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 12.3.3 UDA1355H SPDIF INPUT Table 81 Register address 59H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − SPDO_STATUS BIT 7 6 5 4 3 2 1 0 Symbol − − − − − − B_ERR SPDIF_LOCK Table 82 Description of register bits (address 59H) BIT SYMBOL DESCRIPTION − reserved SPDO_STATUS SPDIF encoder output status. If this bit is logic 0 then the SPDIF encoder output is enabled; if this bit is logic 1 then the SPDIF encoder output is disabled. − reserved 1 B_ERR Bit error detection. If this bit is logic 0 then there is no biphase error; if this bit is logic 1 then there is a biphase error. 0 SPDIF_LOCK SPDIF lock indicator. If this bit is logic 0 then the SPDIF decoder block is not in lock; if this bit is logic 1 then the SPDIF decoder block is in lock. 15 to 9 8 7 to 2 Table 83 Register address 5CH (left) and 5FH (right); note 1 BIT Symbol BIT Symbol 15 14 13 12 11 10 9 8 − − − − − − − − 7 6 5 4 3 2 1 0 SPDI_ BIT39 SPDI_ BIT38 SPDI_ BIT37 SPDI_ BIT36 SPDI_ BIT35 SPDI_ BIT34 SPDI_ BIT33 SPDI_ BIT32 Note 1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72. Table 84 register addresses 5BH (left) and 5EH (right); note 1 BIT Symbol BIT Symbol 15 14 13 12 11 10 9 8 SPDI_ BIT31 SPDI_ BIT30 SPDI_ BIT29 SPDI_ BIT28 SPDI_ BIT27 SPDI_ BIT26 SPDI_ BIT25 SPDI_ BIT24 7 6 5 4 3 2 1 0 SPDI_ BIT23 SPDI_ BIT22 SPDI_ BIT21 SPDI_ BIT20 SPDI_ BIT19 SPDI_ BIT18 SPDI_ BIT17 SPDI_ BIT16 Note 1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72. 2003 Apr 10 62 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 85 register address 5AH (left) and 5DH (right); see note 1 BIT Symbol BIT Symbol 15 14 13 12 11 10 9 8 SPDI_ BIT15 SPDI_ BIT14 SPDI_ BIT13 SPDI_ BIT12 SPDI_ BIT11 SPDI_ BIT10 SPDI_ BIT9 SPDI_ BIT8 7 6 5 4 3 2 1 0 SPDI_ BIT7 SPDI_ BIT6 SPDI_ BIT5 SPDI_ BIT4 SPDI_ BIT3 SPDI_ BIT2 SPDI_ BIT1 SPDI_ BIT0 Note 1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72. 13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all voltage referenced to ground. SYMBOL PARAMETER VDD supply voltage CONDITIONS note 1 MIN. 2.7 MAX. UNIT 5.0 V Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Vesd electrostatic discharge voltage +3000 V Human Body Model (HBM); note 2 −3000 Machine Model (MM); note 3 −250 +250 V − 100 mA output short-circuit to VSSA1 − 20 mA output short-circuit to VDDA1 − 100 mA Ilu(prot) latch-up protection current Tamb = 125 °C; VDD = 3.6 V Isc(DAC) short-circuit current of DAC Tamb = 0 °C;VDD = 3 V; note 4 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant. 4. DAC operation after short-circuiting cannot be guaranteed. 14 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2003 Apr 10 PARAMETER CONDITIONS thermal resistance from junction to ambient 63 in free air VALUE UNIT 70 K/W NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 15 CHARACTERISTICS VDD = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA1 DAC supply voltage VDDA2 ADC supply voltage 2.7 3.0 3.6 V VDDX crystal oscillator and PLL supply voltage 2.7 3.0 3.6 V VDDI digital core supply voltage 2.7 3.0 3.6 V VDDE digital pad supply voltage IDDA1 DAC supply current IDDA2 ADC supply current 2.7 3.0 3.6 V 2.7 3.0 3.6 V fs = 48 kHz; power-on − 4.7 − mA fs = 96 kHz; power-on − 4.7 − mA fs = 48 kHz; power-down − 1.7 − μA fs = 96 kHz; power-down − 1.7 − μA fs = 48 kHz; power-on − 10.2 − mA fs = 96 kHz; power-on − 10.4 − mA fs = 48 kHz; power-down − 0.2 − μA fs = 96 kHz; power-down − 0.2 − μA IDDX crystal oscillator and PLL supply current fs = 48 kHz; power-on − 0.9 − mA fs = 96 kHz; power-on − 1.2 − mA IDDI digital core supply current fs = 48 kHz; all on − 18.2 − mA fs = 96 kHz; all on − 34.7 − mA fs = 48 kHz; all on − 0.5 − mA fs = 96 kHz; all on − 0.7 − mA IDDE digital pad supply current Digital input pins VIH HIGH-level input voltage 0.8VDD − VDD + 0.5 V VIL LOW-level input voltage −0.5 − +0.2VDD V Vhys(RESET) hysteresis on pin RESET − 0.8 − V |ILI| input leakage current − − 2 μA Ci input capacitance − − 10 pF Digital output pins VOH HIGH-level output voltage IOH = −2 mA 0.85VDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V IL(max) maximum output load (nominal) − 3 − mA Rpu pull-up resistance 16 33 78 kΩ Rpd pull-down resistance 16 33 78 kΩ 3-level input pins VIH HIGH-level input voltage 0.9VDD − VDD V VIM MID-level input voltage 0.4VDD − 0.6VDD V VIL LOW-level input voltage 0 − 0.5 V 2003 Apr 10 64 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. TYP. MAX. UNIT Reference voltage VREF reference voltage on pin REF with respect to VSSA 0.45VDD 0.5VDD 0.55VDD V Digital-to-analog converter Vo(rms) output voltage (RMS value) − 900 − mV ΔVo output voltage unbalance − 0.1 − dB (THD+N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB − −88 − dB at −20 dB − −75 − dB at −60 dB; A-weighted − −37 − dB at 0 dB − −83 − dB at −60 dB; A-weighted − −37 − dB fs = 48 kHz − 98 − dB fs = 96 kHz − 96 − dB fi = 1 kHz tone − 100 − dB 3 − − kΩ − − 200 pF − 0.13 3.0 Ω − tbf − mA IEC 60958 input; fs = 48 kHz IEC 60958 input; fs = 96 kHz S/N signal-to-noise ratio αcs channel separation RL load resistance CL load capacitance Ro output resistance Io(max) maximum output current IEC 60958 input; code = 0; A-weighted note 2 (THD + N)/S < 0.1%; RL = 5 kΩ Analog-to-digital converter VADCP positive ADC reference voltage − VDDA2 − V VADCN negative ADC reference voltage − 0.0 − V Vi(rms) input voltage (RMS value) − 1.0 − V − 0.1 − dB at 0 dB − −85 − dB at −60 dB; A-weighted − −35 − dB at 0 dB − −85 − dB at −60 dB; A-weighted − −35 − dB fs = 48 kHz − 97 − dB fs = 96 kHz − 95 − dB − 100 − dB ΔVi input voltage unbalance (THD+N)/S total harmonic distortion-plus-noise to signal ratio Vo = −1.16 dBFS digital output fs = 48 kHz fs = 96 kHz S/N αcs 2003 Apr 10 signal-to-noise ratio code = 0; A-weighted channel separation 65 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. TYP. MAX. UNIT IEC 60958 inputs Vi(p-p) input voltage (peak-to-peak value) 0.2 0.5 3.3 V Ri input resistance − 6 − kΩ Vhys hysteresis voltage − 40 − mV IDD(diff) IDD(DAC,input)/IDD(DAC,no input) − tbf − − − 74 − mW DAC in Power-down mode − 63 − mW Power consumption Ptot total power consumption IEC 60958 input; fs = 48 kHz DAC in playback mode Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 Ω must be used in order to prevent oscillations in the output. 16 TIMING CHARACTERISTICS VDD = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT − 250 − μs fs = 32 kHz − 85.0 − ms fs = 44.1 kHz − 63.0 − ms fs = 48 kHz − 60.0 − ms fs = 96 kHz − 40.0 − ms Device reset trst reset time PLL lock time tlock time-to-lock I2S-bus interface (see Fig.20) Tcy(BCK) bit clock period 1/ 128fs − − ms tBCKH bit clock HIGH time 30 − − ns tBCKL bit clock LOW time 30 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsu(DATAI) data input set-up time 10 − − ns th(DATAI) data input hold time 10 − − ns td(DATAO-BCK) data output to bit clock delay − − 30 ns td(DATAO-WS) data output to word select delay − − 30 ns th(DATAO) data output hold time 0 − − ns tsu(WS) word select set-up time 10 − − ns th(WS) word select hold time 10 − − ns 2003 Apr 10 66 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. TYP. MAX. UNIT L3-bus interface (see Figs 21 and 22) tr rise time note 1 − − 10 ns/V tf fall time note 1 − − 10 ns/V Tcy(CLK)L3 L3CLOCK cycle time note 2 500 − − ns tCLK(L3)H L3CLOCK HIGH time note 2 250 − − ns tCLK(L3)L L3CLOCK LOW time note 2 250 − − ns tsu(L3)A L3MODE set-up time in address mode 190 − − ns th(L3)A L3MODE hold time in address mode 190 − − ns tsu(L3)D L3MODE set-up time in data transfer mode 190 − − ns th(L3)D L3MODE hold time in data transfer mode 190 − − ns tstp(L3) L3MODE stop time in data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time in address and data transfer mode 190 − − ns th(L3)DA L3DATA hold time in address and data transfer mode 30 − − ns td(L3)R L3DATA delay time in data transfer mode 0 − 50 ns tdis(L3)R L3DATA disable time for read data 0 − 50 ns I2C-bus interface (see Fig.23) fSCL SCL clock frequency 0 − 400 kHz tLOW SCL LOW time 1.3 − − μs tHIGH SCL HIGH time 0.6 − − μs tr rise time SDA and SCL note 3 20 + 0.1Cb − 300 ns tf fall time SDA and SCL note 3 20 + 0.1Cb − 300 ns tHD;STA hold time START condition note 4 0.6 − − μs tSU;STA set-up time repeated START 0.6 − − μs tSU;STO set-up time STOP condition 0.6 − − μs tBUF bus free time between a STOP and START 1.3 condition − − μs tSU;DAT data set-up time 100 − − ns 2003 Apr 10 67 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. 0 TYP. MAX. UNIT − − μs tHD;DAT data hold time tSP pulse width of spikes note 5 0 − 50 ns CL load capacitance for each bus line − − 400 pF Notes 1. In order to prevent digital noise interfering with the L3-bus communication, the rise and fall times should be as small as possible. 2. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1⁄64fs cycle. 3. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. 4. After this period, the first clock pulse is generated. 5. To be suppressed by the input filter. handbook, full pagewidth WS tr t BCKH t d(DATAO-BCK) t h(WS) tf t su(WS) BCK t BCKL Tcy(BCK) t d(DATAO-WS) t h(DATAO) DATAO t su(DATAI) t h(DATAI) DATAI MGS756 Fig.20 I2S-bus interface timing. 2003 Apr 10 68 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA th(L3)DA BIT 0 L3DATA BIT 7 MGL723 Fig.21 L3-bus interface timing for address mode. handbook, full pagewidth tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA L3DATA write tsu(L3)DA BIT 0 BIT 7 L3DATA read td(L3)R tdis(L3)R MBL566 Fig.22 L3-bus interface timing for data transfer mode (write and read). 2003 Apr 10 69 t BUF t LOW tr tf t HD;STA t SP 70 SCL S t HD;DAT t HIGH t SU;DAT t SU;STA MBC611 P Preliminary specification Fig.23 I2C-bus interface timing. t SU;STO Sr UDA1355H handbook, full pagewidth t HD;STA P NXP Semiconductors Stereo audio codec with SPDIF interface 2003 Apr 10 SDA NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 detail X 11 1 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.1 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 97-08-01 03-02-25 SOT307-2 2003 Apr 10 EUROPEAN PROJECTION 71 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 18 SOLDERING 18.1 UDA1355H If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. 18.2 The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. • below 220 °C for all the BGA packages and packages with a thickness ≥Š2.5 mm and packages with a thickness <2.5 mm and a volume ≥350 mm3 so called thick/large packages 18.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 235 °C for packages with a thickness <2.5 mm and a volume <350 mm3 so called small/thin packages. 18.3 Wave soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2003 Apr 10 Manual soldering 72 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 18.5 UDA1355H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your NXP Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 Apr 10 73 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 19 DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20 DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Limited warranty and liability ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2003 Apr 10 74 NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products ⎯ Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Terms and conditions of commercial sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 2003 Apr 10 UDA1355H 21 TRADEMARKS I2C-bus ⎯ logo is a trademark of NXP B.V. 75 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/01/pp76 Date of release: 2003 Apr 10 Document order number: 9397 750 09925