BUK7210-55B N-channel TrenchMOS standard level FET Rev. 01 — 11 December 2008 Product data sheet 1. Product profile 1.1 General description Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using NXP High-Performance Automotive (HPA) TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 1.2 Features and benefits 185 °C rated Standard level compatible Q101 compliant Very low on-state resistance 1.3 Applications 12 V and 24 V loads General purpose power switching Automotive systems Motors, lamps and solenoids 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit - - 55 V - - 75 A VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 9 - 8.5 10 mΩ ID = 75 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped inductive load - - 173 mJ VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 185 °C ID drain current VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3; [1] Static characteristics RDSon drain-source on-state resistance Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy [1] Continuous current is limited by package. BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb [1] G mbb076 S 2 1 3 SOT428 (SC-63; DPAK) [1] It is not possible to make connection to pin 2 of the SOT428 package. 3. Ordering information Table 3. Ordering information Type number Package Name Description BUK7210-55B SC-63; plastic single-ended surface-mounted package (DPAK); 3 leads (one DPAK lead cropped) BUK7210-55B_1 Product data sheet Version SOT428 © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 2 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 185 °C - 55 V RGS = 20 kΩ; 25 °C ≤ Tj ≤ 185 °C VDGR drain-gate voltage VGS gate-source voltage ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3; [1] Tmb = 100 °C; VGS = 10 V; see Figure 1 Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3; [2] - 55 V -20 20 V - 89.6 A - 65.5 A - 75 A - 335 A IDM peak drain current Tmb = 25 °C; tp ≤ 10 µs; pulsed Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 167 W Tstg storage temperature -55 185 °C Tj junction temperature -55 185 °C Source-drain diode IS ISM source current peak source current Tmb = 25 °C; [2] - 75 A Tmb = 25 °C; [3] - 89.6 A - 335 A - 173 mJ tp ≤ 10 µs; pulsed; Tmb = 25 °C Avalanche ruggedness EDS(AL)S non-repetitive ID = 75 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 10 V; drain-source avalanche Tj(init) = 25 °C; unclamped inductive load energy [1] Current is limited by power dissipation chip rating. [2] Continuous current is limited by package. [3] Current is limited by power dissipation chip rating. BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 3 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 003aac284 100 ID (A) 03no96 120 Capped at 75A due to package Pder (%) 75 80 50 40 25 0 0 0 Fig 1. 50 100 150 Tmb (°C) 0 200 Fig 2. Normalized continuous drain current as a function of mounting base temperature 50 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature 003aac272 103 Limit RDSon = VDS / ID ID (A) tp = 10 μ s 102 100 μ s Capped at 75 A due to package DC 1 ms 10 10 ms 100 ms 1 1 Fig 3. 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 4 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-mb) Rth(j-a) Conditions Min Typ Max Unit thermal resistance from see Figure 4 junction to mounting base - - 0.95 K/W thermal resistance from Mounted on a printed circuit board; vertical junction to ambient in still air.; minimum footprint - 75 - K/W 003aac273 1 Zth (j-mb) (K/W) d = 0.5 0.2 10 -1 0.1 0.05 0.02 10-2 δ= P single shot tp T t tp T 10-3 1e-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 5 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 7 - 1.75 - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 7; see Figure 8 2 3 4 V ID = 1 mA; VDS = VGS; Tj = 185 °C; see Figure 7 0.9 - - V ID = 1 mA; VDS = VGS; Tj = -40 °C; see Figure 7 - 2.8 - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 7 - - 4.4 V VDS = 55 V; VGS = 0 V; Tj = 175 °C - 1.5 500 µA VDS = 55 V; VGS = 0 V; Tj = 125 °C - 0.1 90 µA VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 55 V; VGS = 0 V; Tj = 185 °C - 3 800 µA VDS = 0 V; VGS = 20 V; Tj = 25 °C - 2 100 nA VDS = 0 V; VGS = -20 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 25 A; Tj = 185 °C; see Figure 9 - - 20.8 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 9 - 8.5 10 mΩ ID = 25 A; VDS = 44 V; VGS = 10 V; Tj = 25 °C; see Figure 12; see Figure 13 - 35 - nC - 9 - nC - 12 - nC - 1840 2453 pF - 379 455 pF - 165 226 pF - 18 - ns - 91 - ns drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 48 - ns tf fall time - 45 - ns LD internal drain inductance measured from drain to center of die; Tj = 25 °C - 2.5 - nH LS internal source inductance measured from source lead to source bond pad; Tj = 25 °C - 7.5 - nH VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 14 VDS = 25 V; RL = 1.2 Ω; VGS = 10 V; RG(ext) = 10 Ω; Tj = 25 °C BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 6 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit IS = 18 A; VGS = 0 V; Tj = 150 °C - 0.76 - V IS = 18 A; VGS = 0 V; Tj = 175 °C - 0.74 - V IS = 18 A; VGS = 0 V; Tj = 100 °C - 0.8 - V IS = 18 A; VGS = 0 V; Tj = 25 °C; see Figure 11 - 0.85 1.2 V IS = 18 A; VGS = 0 V; Tj = 125 °C - 0.78 - V IS = 18 A; VGS = 0 V; Tj = 185 °C; see Figure 11 - 0.73 - V IS = 20 A; dIS/dt = -100 A/µs; VGS = -10 V; VDS = 30 V; Tj = 25 °C - 67 - ns - 65 - nC Source-drain diode source-drain voltage VSD trr reverse recovery time Qr recovered charge 003aac279 100 003aac285 18 RDSon (m Ω) 16 ID (A) 75 14 50 12 10 25 Tj = 185 °C Tj = 25 °C 8 0 6 0 2 4 6 8 5 VGS (V) Fig 5. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 6. 15 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values. BUK7210-55B_1 Product data sheet 10 © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 7 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 003aac282 5 ID (A) VGS(th) (V) 4 max 10−4 min 10−5 1 Fig 7. typ 10−3 typ 2 min 10−2 max 3 0 -60 03aa35 10−1 10−6 10 80 150 Tj (°C) 220 2 4 6 VGS (V) Gate-source threshold voltage as a function of junction temperature 003aac283 2.4 0 Fig 8. Sub-threshold drain current as a function of gate-source voltage 003aac276 25 Lable is VGS (V) 6 RDSon (mΩ ) a 6.5 7 8 10 20 20 1.6 15 0.8 10 0 -60 Fig 9. 5 10 80 150 Tj (°C) 220 Normalized drain-source on-state resistance factor as a function of junction temperature 0 150 225 ID (A) 300 Fig 10. Drain-source on-state resistance as a function of drain current; typical values BUK7210-55B_1 Product data sheet 75 © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 8 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 003aac281 100 VDS IS (A) ID 75 VGS(pl) VGS(th) 50 VGS QGS1 25 Tj = 185 °C QGS2 QGS Tj = 25 °C QGD QG(tot) 003aaa508 0 0.0 0.3 0.6 0.9 VSD (V) 1.2 Fig 12. Gate charge waveform definitions Fig 11. Source current as a function of source-drain voltage; typical values 003aac280 10 VGS (V) 003aac278 3000 C (pF) 7.5 VDD = 14 V 2000 VDD = 44 V Ciss 5 1000 2.5 Coss Crss 0 0 10 20 30 QG (nC) 40 Fig 13. Gate-source voltage as a function of gate charge; typical values 0 10-1 102 10 VDS (V) Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values BUK7210-55B_1 Product data sheet 1 © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 9 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 003aac274 300 ID (A) 250 20 16 Label is VGS (V) 12 10 9.5 200 9 8.5 8 150 7.5 7 100 6.5 6 50 5.5 5 4.5 0 0 2 4 6 8 10 VDS (V) Fig 15. Output characteristics: drain current as a function of drain-source voltage; typical values BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 10 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 7. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E A A A1 b2 E1 mounting base D2 D1 HD 2 L L2 1 L1 3 b1 b w M c A e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D1 D2 min E E1 min e e1 HD L L1 min L2 w y max mm 2.38 2.22 0.93 0.46 0.89 0.71 1.1 0.9 5.46 5.00 0.56 0.20 6.22 5.98 4.0 6.73 6.47 4.45 2.285 4.57 10.4 9.6 2.95 2.55 0.5 0.9 0.5 0.2 0.2 OUTLINE VERSION SOT428 REFERENCES IEC JEDEC JEITA TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 06-02-14 06-03-16 Fig 16. Package outline SOT428 (DPAK) BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 11 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes BUK7210-55B_1 20081211 Product data sheet - - BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 12 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] BUK7210-55B_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 11 December 2008 13 of 14 BUK7210-55B NXP Semiconductors N-channel TrenchMOS standard level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 December 2008 Document identifier: BUK7210-55B_1