XC 8 0 0 Fa m i l y AP 0 8 1 1 0 De s ig n G ui de l in e f o r X C 82 x an d X C 83 x B o ar d L ay o ut Ap p l i c a ti o n No te V 1 . 0, 2 01 0- 06 M i c ro c o n t ro l l e rs Edition 2010-06 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE. 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AP08110 Design Guideline for XC82x and XC83x Board Layout XC82x and XC83x Revision History: V1.0 2010-06 Previous Version(s): Page Subjects (major changes since last revision) – First release. Trademarks TriCore® is a trademark of Infineon Technologies AG. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Application Note 3 V1.0, 2010-06 AP08110 Design Guideline for XC82x and XC83x Board Layout Table of Contents Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Power Supply De-coupling and Improved ADC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 RTC-XTAL Oscillator Pins (XC835 and XC836 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application Note 4 V1.0, 2010-06 AP08110 Design Guideline for XC82x and XC83x Board Layout Overview 1 Overview The XC82x and XC83x are low pin count products of the XC800 Family from Infineon. Because of the minimum number of supply pins, special care with the layout needs to be taken with these products. The correct board layout will help achieve the best ADC performance and EMC behaviour, as well as ensuring the robustness of the RTCXTAL oscillator. This document should be read in conjunction with the Infineon PCB Design Guidelines for Microcontrollers (AP24026), which gives general design rule information for PCB design. This application note discusses product specific recommendations and guidelines for the XC82x and XC83x products. 1.1 General Information The microcontroller has just two supply pins (VDDP and VSSP) to which all internal modules are connected. These are the embedded voltage regulator, the port pins, the ADC module and the RTC-XTAL oscillator in the XC83x. The performance of the ADC and the robustness of the RTC-XTAL oscillator will be reduced, if core supply noise or pin activity noise are not properly de-coupled. Proper de-coupling can be achieved by separating the ground traces in analog, digital and oscillator groups. A star point connection should be considered at the pad of the VSSP pin. The ADC reference voltage can be configured as an internal 1.2 V reference, or it can be connected to the VDDP. In the latter case, supply noise directly influences the ADC performance. The RTC-XTAL oscillator can be disturbed by noise injection from neighboring active pins driving high frequency signals from I2C, PWM or the LED and Touch Sense unit. Proper PCB layout will reduce the capacitance between those traces to a minimum. This application note includes layout recommendations for optimized ADC performance and robust RTC-XTAL oscillator operation. Application Note 5 V1.0, 2010-06 AP08110 Design Guideline for XC82x and XC83x Board Layout Power Supply De-coupling and Improved ADC Performance 2 Power Supply De-coupling and Improved ADC Performance There are two different reasons why microcontrollers can cause noise at the power supply. Firstly the synchronous clocked logic functions lead to peak current at the MCU clock frequency. Secondly, pulse pattern and clock output at any port pin will draw current at the pulse pattern’s frequency. De-coupling capacitors are intended to buffer the charge needed to feed the required current pulses. Of course noise at the power supply lines might also disturb the microcontroller. This noise can be filtered by the same de-coupling capacitor. Figure 1 shows the recommended PCB layout of the de-coupling capacitors. ADC reference GND ADC reference GND XC822 XC824 VDDC XTAL oscillator GND XC835 XC836 C1 VDDC C1 VDDP VDDP Grey areas : keep clear , no GND connection recommended Figure 1 VSSP C2 VSSP C2 VDD VDD GND GND Decoupling .emf Decoupling Capacitor for Power Supply The noise of the power supply (VDD and GND) is filtered by the capacitor C2 and provided at the power supply pins VDDP and VSSP. The core supply pin VDDC is connected to capacitor C1 in order to reduce noise at the ground connection which is caused by the synchronous logic clocked at the MCU frequency. C1 should be set in the range of 220 nF to 470 nF, and C2 in the range of 68 nF to 220 nF. Capacitors with low ESR (type X7R for example) are recommended. A star configuration at the VSSP pin is the least noisy connection for the ADC reference ground. This connection is best coupled to the ADC’s reference voltage ground potential. This is important for minimizing ADC errors. It must be ensured that the de-coupling capacitors C1 and C2 are placed as close to the pins as possible. It is also important to connect the power supply GND and VDD only at those traces shown in Figure 1. Any additional connection will bypass the decoupling capacitor and will therefore reduce it’s effectiveness. The grey areas shown in the figures should be kept clear of any GND connections and GND planes. The ADC reference GND connection is intended to be utilized in common mode with the ADC’s input pins. Any additional connection to the power supply GND will cause supply noise to be injected to the ADC’s reference GND. Application Note 6 V1.0, 2010-06 AP08110 Design Guideline for XC82x and XC83x Board Layout RTC-XTAL Oscillator Pins (XC835 and XC836 only) 3 RTC-XTAL Oscillator Pins (XC835 and XC836 only) The XC83x RTC-XTAL oscillator is designed for low power consumption. As a result, the high impedance input of the crystal oscillator is sensitive to noise. This noise might be caused by port activity from the PWM or I2C data as well as other periodic port signals. The correct PCB layout will help ensure precise operation of this oscillator. The RTC-XTAL oscillator signals RTC-XTAL3 and RTC-XTAL4 should not be routed in parallel to any GPIO signals on the PCB, because of the potential parasitic capacitances between the traces. A star configuration should be used for the GND connection. See Figure 2 for the recommended PCB layout. C3 XTAL XC835 P3.2 XTAL4 P0.7 XTAL3 C4 C4 XTAL XC836 P0.7 P3.2 C3 P2.3 XTAL4 P0.3 XTAL3 P0.3 VDDP VSSP VSSP Grey areas : keep clear , no GND connection recommended Figure 2 XTAL .emf RTC-XTAL and Capacitor Connection The filter capacitors C3 and C4 should connect directly to the VSSP pin without any additional GND connection. In this arrangement, noise at VSSP is in common mode with the crystal circuitry and does not influence the oscillator’s performance or robustness. The recommendations described in Chapter 2 are also valid here. Please refer to Figure 1 for placement of the supply de-coupling capacitor. Application Note 7 V1.0, 2010-06 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG