High-Performance High-!/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing M. Chudzik, B. Doris2, R. Mo, J. Sleight2, E. Cartier2, C. Dewan2, D. Park2, H. Bu2, W. Natzle2, W. Yan, C. Ouyang2, K. Henson, D. Boyd, S. Callegari2, R. Carter3, D. Casarotto, M. Gribelyuk, M. Hargrove3, W. He, Y. Kim2, B. Linder2, N. Moumen, V.K. Paruchuri2, J. Stathis2, M. Steen2, A. Vayshenker, X. Wang2, S. Zafar2, T. Ando4, R. Iijima5, M. Takayanagi5, V. Narayanan2, R. Wise, Y. Zhang2, R. Divakaruni, M.Khare2, T.C. Chen2 2 IBM Semiconductor Research and Development Center (SRDC), IBM Systems and Technology Division, Hopewell Junction, NY 12533, USA, Research Division, T.J. Watson Research Center, Yorktown Heights, NY 10598, USA, 3Advanced Micro Devices, Inc. , 2070 Route 52 Hopewell Jct, NY 12533, 4 Sony Electronics [email protected]. Watson Research Center, Yorktown Heights, NY 10598, USA, 5Toshiba America Electronic Components [email protected]. Watson Research Center, Yorktown Heights, NY 10598, USA E-mail:[email protected] Abstract Gate-first integration of band-edge (BE) high-!/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-!/metal gates (HK/MG) enabled by the thinnest Tinv (<12Å) for BE nFET devices to-date, consistent with simulations showing the need for <14Å Tinv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high!/metal gate pFET’s fabricated with gate-first high thermal budget processing with thin Tinv (<13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-!/metal gate nFET’s into CMOS devices yielded large SRAM arrays. Introduction Scaling the channel length at the 45nm node and beyond has significant performance impact both from intrinsic device and extrinsic improvements [1]. Simulations in Fig. 1 and Fig. 2 show that high performance logic requires dual work-function devices near 110mV to the band-edge (BE) values of silicon and Tinv <14Å to show appreciable performance and short channel benefit over SiON/Poly-Si devices. Many reports exist detailing the thermal instabilities of the high-!/metal (HK/MG) devices as a remaining roadblock to the implementation of dual work-function HK/MG in high-performance CMOS in gate-first processing, in particular the pFET [2,3]. These thermal instabilities lead to threshold voltage shifts and re-growth [4,5] in the gate stack which has prevented the implementation of HK/MG using gate-first processing. The majority of the reported near-BE HK/MG nFET/pFET solutions implement a damascene integration approach which suffers from high overlap capacitance (Cov) due to the high-k material along the spacer sidewall degrading AC performance and reduced mobility due to restricted thermal budgets [6]. This work focuses on utilizing a gate-first approach to overcome these limitations. Device Fabrication and Results Short channel HK/MG devices were fabricated from <20Å HfO2 with thermally stable BE metal gates in a gate-first approach where conventional poly-Si is deposited over the metal gates. Following a lithographic patterning and gate stack etch process, a conventional selfaligned implant process flow with a final S/D spike RTA (T>1080°C) + advanced annealing (AA) and dual stress liner (DSL) with conventional MOL and BEOL was used. Fig. 3 shows a TEM image of the nFET HK/MG stack after full build showing a physical gate length of 33nm. Short channel device properties of the HK/MG nFET devices exhibit superior drive current and short channel control as compared to state-ofthe-art 65nm node 11Å SiON/Poly-Si gate stacks. DIBL improvement of 15mV at fixed Lgate as shown in Fig. 4 supports a 5nm reduction in channel length as predicted from the simulations in Fig 1. The improved short channel control is due to high-!/metal gate process improvements that enable Tinv <12Å as seen in Fig 5 by preventing regrowth that plagues gate-first processing. Fig. 6 shows a DC Idsat of 1240uA/um @ Ioff = 200nA/um with a corresponding AC Idsat 1364uA/um (non-self-heated) in the nFET HK/MG devices at 1.0V. Well controlled Vtlin / Vtsat roll-off to an Lgate of 25nm is shown in Fig. 7, demonstrating excellent short channel control. Fig. 8 shows that Idsat is maintained as Lgate is scaled compared to an 11Å SiON at fixed Ioff and optimal Cov. The flatness of the HK/MG vs. SiON curve again demonstrates the improved short channel control in these HK/MG devices. These stacks are compatible with existing stress adders as shown in Fig 9. There is a 15% change in Ron [7] at a Lgate of 35nm with a stressed liner which results in the expected drive current improvement. HK/MG pFET stacks fabricated using high work-function metals ("m) in a gate-first integration scheme suffer from two problems: (a) >500 meV lower effective "m on HfO2 [2,3] and (b) significant interfacial layer regrowth [5]. The problem is highlighted in Fig. 10 which shows that aggressive stacks (Tinv=14Å) have Vts which are at least 500mV away from pFET BE. These pFET problems can be circumvented and the initially high Vt can be lowered by 720mV by process optimization resulting in a pFET Vt @ BE while simultaneously maintaining aggressive Tinv (<13Å) & high mobility (92% of universal) for BE pFET HK/MG stacks fabricated in a gate-first process as shown in Figs. 11, 12 and 13. The simulations in Fig. 2 show that pFETs and nFETs with Tinv <14Å and "m <110 mV from BE improve performance in RO delay compared to SiON/Poly-Si. Reliability Results The reliability of the HK/MG gate devices was evaluated for TDDB, hot carrier, PBTI and NBTI. The charge trapping characteristics were measured at elevated temperature and voltages for lifetime predictions using a stretched exponential model [8]. The predicted 10yr PBTI shift in Fig. 14 is shown to be acceptable. The hot carrier degradation in the BE HK/MG nFETs is consistent with models for SiON/Poly-Si nFETs. The model projection to use condition was below target with Veff corrected for self-heating effects, demonstrating that hot carrier degradation is acceptable. Breakdown was confirmed to be nonprogressive for metal gates. The voltage acceleration power-law exponent is superior for HfO2 compared to SiON due the steeper current/voltage dependence in high-! versus SiON and the area scaling Weibull slope is better than for SiON in 65nm technology (Fig. 15). The BE HK/MG pFETs threshold voltage stability under negative bias stress (Fig. 16) follows a power law and is projected to be consistent with technology needs [8]. SRAM Results Manufacturability studies of HK/MG integrated using a gate-first approach were performed in a 300mm production line to evaluate the yield. In this study high-performance nFET BE HK/MG devices were first integrated with SiON/Poly-Si pFET’s to form large SRAM arrays. The top-down SEM image in Fig. 17 shows a portion of a large SRAM device array fabricated with HK/MG nFET’s and SiON/Poly-Si pFET’s. Fig. 18 shows the operating window of the SRAM array containing HK/MG devices at different array (Varray) and BL/logic (Vdd BL) voltages, demonstrating that good Vddmin and Vddmax values are obtained. Conclusions By using an integration method that is consistent with traditional high thermal budget gate-first CMOS processing we have demonstrated improved short channel control with high-!/metal gate devices compared to SiON. The aggressive Tinv scaling enables Lgate scaling and results in the highest performing HK/MG nFET devices to-date for the 45nm technology and beyond. BE pFET HK/MG devices are shown with the lowest Tinv to-date providing a gate-first integration path for dual BE HK/MG CMOS technology implementation. Manufacturability evaluations of the nFET high-!/metal gate devices with performance adders successfully yielded large SRAM arrays. 200 175 150 125 160 140 120 100 80 0.025 0.030 0.035 0.040 0.045 0.050 0.055 0.060 Lgate (#m) 100 1.4 1.2 1.0 0.8 0.020 0.025 0.030 0.035 Lgate (#m) 0.040 2 pFET Band-Edge Position After 1000C, 5s process -0.2 Vtlin (V) 2.5 -0.1 2.0 1.5 1.0 -0.3 34 36 38 40 Gate Voltage (V) Figure 5: C-V Plot for the BE Figure 10: Universal pFET Vt vs. HK/MG nFET gate stack. Tinv curve for multiple HfO2/metal stacks after 1000C/5sec. 10 -7 10 2 DC Data -8 DC = 1240uA/um AC = 1364uA/um at Ioff=200nA/um 10 800 1000 1.20 1.10 1.05 1200 Ion (#A/#m) 1400 1600 Figure 6: Ion vs. Ioff plot of HK/MG nFETs. 1.00 0.6 0.95 0.5 0.90 0.4 -250 -200 -150 -100 -50 0 Workfunction From Band-Edge (meV) Figure 2: Simulations showing relative RO delay vs. workfunction from BE for HK/MG. Vt (V) 0.85 -300 Vtlin 0.3 0.2 Vtsat 0.1 0.0 0.02 0.03 0.04 0.05 Lgate (#m) 3.0 10umX0.1um Tinv=13A 2.5 2.0 1.8 2.0 2.2 n = 70.7 & 1.5 10 % = 2.5 & 0.1 2 10 100 -1.5 V 0.01 -1.2 V -1 0 10 1 10 2 10 2 900 HK/MG SiON/poly-Si 0.035 0.04 Lgate (#m) 0.045 0.05 3 10 4 10 5 10 6 10 Stress Time (s) Figure 16: NBTI response for the BE HK/MG pFETs. 1.0 0.5 0.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Figure 11: C-V Plot of HK/MG pFET device. Mobility (cm /Vs) fixed Ioff=100nA/#m 2.35 Figure 15: TDDB voltage acceleration and Weibull slope for band-edge HK/MG nFETs. 10 0.2 0.0 -0.2 -0.4 720 mV -0.6 Figure 17: Top-down SEM of the large SRAM array w/ BE HK/MG nFETs & SiON/PolySi pFETs. -0.8 -1.0 100 1000 800 0.03 2 2.25 2.3 Vgate (V) Gate Voltage (V) 1200 1100 1000 Area (#m ) 1.4 1.3 Figure 12: Vt plot for optimized BE HK/MG pFETs. 1300 Ion (#A/#m) 100 1E-3 1.5 Figure 7: Vt roll off for BE HK/MG nFETs. Figure 3: TEM image of the HK/MG nFET at 33nm Lgate. 1.6 3 -0.5 -0.8 12 14 16 18 20 22 24 26 28 30 Tinv (Å) -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -9 14A Tinv-unloaded 10.3A Tinv-unloaded 14A Tinv-loaded 10.3A Tinv-loaded 1.4 10 2.2 -0.7 0.0 10 1.15 1.2 -0.6 0.5 Ioff (A/#m) Figure 1: Simulations showing DIBL response for HK/MG and SiON/Poly-Si devices as a function of Lgates at various Tinv values. 1.0 -$Vt (V) 32 Lgate (nm) Vt = 0.34 V -0.4 Optimized Process 30 1 Vstress (V) TBD (arb units) 0.0 20umx10um Tinv = 11.9A 3.0 Initial Process 28 Tinv = 14 Å 0.045 -5 26 o T = 125 C 10 4 -6 Relative RO Delay (%) DSL No DSL 1.6 Figure 14: PBTI response of Figure 9: Normalized Ron vs. the HK/MG nFETs. Figure 4: DIBL vs. Lgate for Lgate in HK/MG nFETs w/ and HK/MG vs. SiON/Poly-Si nFETs. w/o DSL. 10 10 0.80 Predicted $VT @ 10 yr. (mV) DIBL (mV) 180 Capacitance Density (#F/cm ) 100 200 Threshold Voltage,Vt (V) DIBL (mV) 225 220 1.8 1.2 1.1 1 17 2 Substrate doping = 5.6x10 /cm 90 80 70 60 Tinv = 13A 0.9 Un ive rsa 0.8 50 lM obil ity 0.7 0.6 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 40 92% universal 30 Vdd BL (V) 20 10 Figure 18: Shmoo plot of a large SRAM array with Figure 8: Ion roll-off plot comparing HK/MG and Figure 13: Mobility vs. inversion HK/MG nFETs (light zone is charge for the HK/MG pFET gate zero fails). SiON/Poly-Si nFETs devices. stack. 0 0.0 0.2 0.4 0.6 0.8 Efield (MV/cm) 1.0 1.2 V Array (V) PG 19A Tinv,Lnom=35nm PG 19A Tinv,Lnom=31nm MG 14A Tinv,Lnom=33nm MG 12A Tinv,Lnom=31nm 240 Capacitance Density (#F/cm ) 300 250 HK/MG SiON/poly-Si 260 [1] J. Sleight et al., International Electron Devices Meeting (IEDM), San Fran., CA, 2006 [2] E. Cartier et al., 2005 Symposium on VLSI Technology, pp. 230-1, 2005 [3] J. K. Schaeffer et al., APL, 85, pg. 1826, 2004 [4] F. Andrieu et al. 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