MCS3142 Memory Programming

MCS3142
MCS3142 Memory Programming Specification
This document includes the
programming specifications for the
following device:
• MCS3142
1.0
OVERVIEW
The MCS3142 contains 128 bytes of nonvolatile
memory. This array is used to store the various
encryption parameters and device configuration
options. Details of the individual Configuration bits is
described in the device data sheet.
The device is programmed serially using a clock input
and bidirectional data signal. A special entry sequence
is used to prevent accidental Program mode entry.
Further, the device can only be programmed
immediately after power-up.
TABLE 1-1:
PIN DESCRIPTION DURING PROGRAMMING
During Programming
Pin Name
2.0
Function
Type
Description
PGC
Programming Clock
I
TTL Input
PGD
Programming Data
I/O
TTL Input/Output
VDD
Power
P
Power
VSS
Ground
P
Ground
DEVICE PINOUTS
FIGURE 2-1:
20-PIN DIAGRAM FOR
MCS3142
TSSOP
1
20
VSS
2
19
SW0
SOSCO
3
18
SW1
SW3
4
17
SW2
PGC
5
16
LED
PGD
6
MCS3142
VDD
SOSCI
15
DATA_OUT
14
CTRL_OUT
VSS
7
VDD
8
13
XTAL
CTRL_IN
9
12
DATA_IN
10
11
VSS
RFOUT
 2013-2014 Microchip Technology Inc.
Preliminary
DS40001682B-page 1
MCS3142
3.0
MEMORY MAP
The program memory map for this device begins at
0x00 and extends as shown in Table 3-1. As the device
is being programmed, the address counter
automatically increments to the next byte location after
receiving a data byte.
Data is sent Least Significant Byte (LSB) first.
TABLE 3-1:
MEMORY MAP
Address
Size (bytes)
Description
KEELOQ®
0x00 - 0x07
8
Classic
0x08 - 0x0F
8
Classic KEELOQ Seed Value
0x10 - 0x13
4
Classic KEELOQ Serial Number
0x14 - 0x15
2
Classic KEELOQ DISC Value
0x16 - 0x17
2
Classic KEELOQ Encoder Configuration
0x18 - 0x19
2
Classic KEELOQ Transmitter Configuration
0x1A
1
Classic KEELOQ Minimum Packet
0x1B - 0x1C
2
Classic KEELOQ Maximum Packet
0x1D
1
Classic KEELOQ TE PR2 Value
0x1E - 0x2D
16
Ultimate KEELOQ Encryption Key
0x2E - 0x3D
16
Ultimate KEELOQ Seed Value
0x3E - 0x41
4
Ultimate KEELOQ Serial Number
0x42 - 0x43
2
Reserved
0x44 - 0x53
16
Ultimate KEELOQ Authorization Key
0x54 - 0x55
2
Ultimate KEELOQ Encoder Configuration
0x56 - 0x57
2
Ultimate KEELOQ Transmitter Configuration
0x58
1
Ultimate KEELOQ Minimum Packet
0x59 - 0x5A
2
Ultimate KEELOQ Maximum Packet
0x5B
1
Ultimate KEELOQ TE PR2 Value
0x5C - 0x5E
3
Encoder Frequency Setting
0x5F - 0x60
2
Encoder Button Configuration
0x61 - 0x62
2
Seed Packet Button Configuration
0x63 - 0x65
3
Ultimate KEELOQ Synchronization Counter, Copy 1
0x66
1
Ultimate KEELOQ Synchronization Counter CRC, Copy 1
0x67 - 0x68
2
Classic KEELOQ Synchronization Counter, Copy 1
0x69
1
Classic KEELOQ Synchronization Counter CRC, Copy 1
0x6A - 0x6B
2
Ultimate KEELOQ Resynchronization Counter, Copy 1
0x6C
1
Ultimate KEELOQ Resynchronization Counter CRC, Copy 1
0x6D - 0x70
4
Ultimate KEELOQ Low-speed Timer, Copy 1
0x71
1
Ultimate KEELOQ Low-speed Timer CRC, Copy 1
0x72 - 0x74
3
Ultimate KEELOQ Synchronization Counter, Copy 2
0x75
1
Reserved
0x76 - 0x77
2
Classic KEELOQ Synchronization Counter, Copy 2
0x78
1
Reserved
0x79 - 0x7A
2
Ultimate KEELOQ Resynchronization Counter, Copy 2
0x7B
1
Reserved
0x7C - 0x7F
4
Ultimate KEELOQ Low-speed Timer, Copy 2
DS40001682B-page 2
Encryption Key
Preliminary
 2013-2014 Microchip Technology Inc.
MCS3142
4.0
PROGRAMMING
4.1
Entering Programming Mode
Programming is initiated by forcing the PGD line high
after the PGC line has been held high for the
appropriate length of time. The programming sequence
must happen immediately after device power-up. See
Figure 4-1 and Table 5-2 for details. A delay must be
provided for the automatic Bulk Erase cycle to
complete after entering the Program mode sequence.
The device can then be programmed by clocking in 8
bits at a time, using PGC as the clock line and PGD as
the data line.
All configurable options are programmed serially via
the PGD and PGC pins of the device. The
programming cycle must include all 888 bits of
programmable data, which is stored in the device’s
nonvolatile memory upon completion.
Device programming must begin within a specific
window after device power-up. The PGD and PGC pins
are configured as inputs upon Reset and, if the
programming sequence is started, will remain as inputs
until the Verify stage is reached.
The device’s memory is only readable during the Verify
stage. There is no procedure to read memory except
immediately after programming.
4.2
Serial Program Mode
Write cycles are performed a byte at a time throughout
the entire programming sequence. A delay after each
8-bit byte is required for the internal program cycle to
complete.
Data bytes are sent Least Significant bit (LSb) first. See
Figure 4-1.
FIGURE 4-1:
PROGRAMMING WAVEFORM
Enter Program
TPBW
Mode
TS
TDS
TCLKH
PGC
TCLKL
TWC
TDH
TPS TPH1
bit 0 bit 1 bit 2 bit 3
PGD
TPH2
 2013-2014 Microchip Technology Inc.
bit 6 bit 7
Data for byte 0
Repeat for each byte
Preliminary
bit 8 bit 9
Data for byte 1
DS40001682B-page 3
MCS3142
4.3
Serial Verify Mode
A verify operation is available immediately following the
programming operation. It must be completed at the
end of the programming sequence, before exiting the
Programming mode.
The programmer must provide a delay time to allow for
write cycle completion. Afterwards, the programmer
can provide clock cycles to begin reading data. See
Figure 4-2.
FIGURE 4-2:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from byte 0
TWC
Data from byte 1
TRC
PGC
PGD
bit n-1 bit n
bit 0
bit 1 bit 2 bit 3
bit 6 bit 7
bit 8
bit 9 bit 10
TDV
DS40001682B-page 4
Preliminary
 2013-2014 Microchip Technology Inc.
MCS3142
5.0
ELECTRICAL SPECIFICATIONS
Refer to the device data sheet for absolute maximum
ratings.
TABLE 5-1:
DC CHARACTERISTICS
Symbol
Item
Min.
Max.
Units
VDD
—
2.1
3.6
V
VIH
Input High Level
0.25 VDD + 0.8
—
V
VIL
Input Low Level
—
0.15 VDD
V
VOH
Output High Level
VDD - 0.7
—
V
VOL
Output Low Level
—
0.6
V
TABLE 5-2:
PROGRAM/VERIFY TIMING REQUIREMENTS
Parameter
Entry Start-up Delay
Program Mode Setup Time
Symbol
Min.
Max.
Units
TS
10
—
ms
TPS
3.5
11.5
ms
Hold time 1
TPH1
3.5
—
ms
Hold time 2
TPH2
3.5
—
ms
Bulk Write Time
TPBW
11
—
ms
Program Cycle Time
TWC
8
—
ms
TRC
5
—
ms
Clock Low Time
TCLKL
50
—
µs
Clock High Time
TCLKH
50
—
µs
Data Setup Time
TDS
0
—
µs
Data Hold Time
TDH
30
—
µs
Data Out Valid Time
TDV
—
30
µs
Program Read Cycle
 2013-2014 Microchip Technology Inc.
Preliminary
DS40001682B-page 5
MCS3142
APPENDIX A:
REVISION HISTORY
Revision A (08/2013)
Initial release.
Revision B (01/2014)
Updated Table 3-1.
DS40001682B-page 6
Preliminary
 2013-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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ISBN: 9781620778371
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Preliminary
DS40001682B-page 7
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