MachXO3™ Family Data Sheet Supplement for LVCMOS10 Inputs and BIDIs DS1047_S_LVCMOS10 Version 1.1, April 2016 MachXO3 Family Data Sheet Supplement April 2016 Data Sheet DS1047 Overview This document is a supplement to the MachXO3 Family Data Sheet and provides the following additions or customizations: • Support for LVCMOS10R33 and LVCMOS10R25 inputs and BIDIs for –6 speed grade devices + Bank VREF LVCMOS10 – VREF © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1047 S_1.1 MachXO3 Family Data Sheet Supplement sysIO Recommended Operating Conditions VCCIO (V) Standard Min. VREF (V) Typ. Max. Min. Typ. Max. LVCMOS10R33 3.135 3.3 3.6 0.35 0.5 0.65 LVCMOS10R25 2.375 2.5 2.625 0.35 0.5 0.65 sysIO Single-Ended DC Electrical Characteristics VIL Input/Output Standard Min. (V) LVCMOS10R33 -0.3 LVCMOS10R25 -0.3 VIH Max. (V) VOL Max. (V) VOH Min. (V) VREF – 0.1 VREF + 0.1 3.465 0.40 VREF – 0.1 VREF + 0.1 3.465 0.40 Max. (V) Min. (V) 2 IOL (mA) IOH1 (mA) N/A Open Drain 16, 12, 8, 4 N/A Open Drain N/A Open Drain 12, 8, 4 N/A Open Drain MachXO3 Family Data Sheet Supplement Revision History Date Version April 2016 1.1 Corrected typo error in Overview section. Change Summary November 2015 1.0 Initial release. 3