Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note TN1309 Version 1.0 May 2016 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note Contents 1. 2. Introduction ..................................................................................................................................................................4 System Bus Interface for CrossLink ...............................................................................................................................4 2.1. System Bus Write Cycle .......................................................................................................................................5 2.2. System Bus Read Cycle ........................................................................................................................................6 2 3. I C Hardened IP Cores ...................................................................................................................................................7 2 4. I C Registers for CrossLink ............................................................................................................................................8 2 4.1. I C Control Register 1 (I2CCR1) ............................................................................................................................9 2 4.2. I C Command Register (I2CCMDR) ......................................................................................................................9 2 4.3. I C Clock Pre-scale Register (I2CBRMSB/I2CBRLSB) ..........................................................................................10 2 4.4. I C Status Register (I2CSR/I2CFIFOSR) ...............................................................................................................11 2 4.5. I C Transmitting Data Register (I2CTXDR/I2CTXFIFO) .......................................................................................13 2 4.6. I C Receiving Data Register (I2CRXDR/I2CRXFIFO) ............................................................................................14 2 4.7. I C General Call Data Register ...........................................................................................................................14 2 4.8. I C Slave Address MSB Register (I2CSADDR/I2CFIFOSADDR) ............................................................................15 2 4.9. I C Interrupt Control Register (I2CINTCR/I2CFIFOINTCR) ..................................................................................15 2 4.10. I C Interrupt Status Register (I2CINTSR/I2CFIFOINTSR) ....................................................................................16 2 4.11. I C FIFO Threshold Register (I2CFIFOTHRESHOLD) ............................................................................................17 2 4.12. I C FIFO TX Byte Counter (I2CFIFOTXCNT) .........................................................................................................17 2 4.13. I C FIFO RX Byte Counter (I2CFIFORXCNT) ........................................................................................................18 2 5. I C Read/Write Flow Chart ..........................................................................................................................................19 2 6. I C Functional Waveforms ..........................................................................................................................................21 References ..........................................................................................................................................................................25 Technical Support Assistance .............................................................................................................................................25 Revision History ..................................................................................................................................................................25 © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note Figures Figure 2.1. System Bus Interface between the FPGA Core and the IP .................................................................................. 4 Figure 2.2. System Bus Write Operation .............................................................................................................................. 5 Figure 2.3. System Bus Read Operation ............................................................................................................................... 6 2 Figure 5.1. I C Master Read/Write Example (via System Bus) ............................................................................................ 19 2 Figure 5.2. I C Slave Read/Write Example (via System Bus) ............................................................................................... 20 2 Figure 6.1. Master – I C Write ............................................................................................................................................ 21 2 Figure 6.2. Master – I C Read ............................................................................................................................................. 22 2 Figure 6.3. Slave – I C Write ............................................................................................................................................... 23 2 Figure 6.4. Slave – I C Read ................................................................................................................................................ 24 Tables Table 2.1. System Bus Slave Interface Signals of the Hardened I2C Module........................................................................ 5 2 Table 4.1. I C Registers Summary ......................................................................................................................................... 8 2 Table 4.2. I C Control Register 1 (I2CCR1) ............................................................................................................................ 9 2 Table 4.3. I C Command Register (I2CCMDR) ..................................................................................................................... 10 2 Table 4.4. I C Clock Pre-scale Register (I2CBRLSB) ............................................................................................................. 10 2 Table 4.5. I C Clock Pre-scale Register (I2CBRMSB) ............................................................................................................ 10 2 Table 4.6. I C Status Register (I2CSR).................................................................................................................................. 11 2 Table 4.7. I C FIFO Status Register (I2CFIFOSR) .................................................................................................................. 12 2 Table 4.8. I C Transmitting Data Register (I2CTXDR) .......................................................................................................... 13 2 Table 4.9. I C Transmitting FIFO Register (I2CTXFIFO) ........................................................................................................ 13 2 Table 4.10. I C Receiving Data Register (I2CRXDR) ............................................................................................................. 14 2 Table 4.11. I C Receiving FIFO Register (I2CRXFIFO)........................................................................................................... 14 2 Table 4.12. I C General Call Data Register (I2CGCDR) ........................................................................................................ 14 2 Table 4.13. I C Slave Address MSB Register (I2CSADDR) .................................................................................................... 15 2 Table 4.14. I C Slave Address MSB Register (I2CFIFOSADDR) ............................................................................................. 15 2 Table 4.15. I C Interrupt Control Register (I2CINTCR) ........................................................................................................ 15 2 Table 4.16. I C Interrupt Control Register (I2CFIFOINTCR) ................................................................................................. 16 2 Table 4.17. I C Interrupt Status Register (I2CINTSR) .......................................................................................................... 16 2 Table 4.18. I C Interrupt Status Register (I2CFIFOINTSR) ................................................................................................... 17 2 Table 4.19. I C FIFO Threshold Register (I2CFIFOTHRESHOLD) .......................................................................................... 17 © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 3 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 1. Introduction 2 This document provides guidance for the advanced usage of the Lattice Semiconductor CrossLink™ I C IP, and supplements TN1308, CrossLink I2C Hardened IP Usage Guide. 2 The recommended flow for initializing the Hard IP I C blocks is the Clarity Designer – GUI flow as described in TN1308. This document includes the following: System Bus Protocol 2 I C Register Mapping 2 I C Timing Diagram Command Sequences Examples 2. System Bus Interface for CrossLink The System Bus in CrossLink provides connectivity between FPGA user logic and the Hardened IP functional blocks. The user can implement a System Bus Master interface to interact with the Hardened IP System Bus Slave interface. The block diagram in Figure 2.1 shows the supported System Bus signals between the FPGA core and the Hardened IP. Table 2.1 on the next page lists the supported signals. Figure 2.1. System Bus Interface between the FPGA Core and the IP © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note Table 2.1. System Bus Slave Interface Signals of the Hardened I2C Module 2 Signal Name I C Wrapper Name* I/O Width Description This chip select signal activates the IP to allow system bus to communicate with the IP. Positive edge clock used by System Bus Interface registers and hardened SBCLKI i2cXclki Input 1 functions. Supports clock speeds up to 133 MHz. Active-high strobe, input signal, indicating the System Bus Slave is the target for the current transaction on the bus. The IP asserts an acknowledgment in SBSTBI i2cXstbi Input 1 response to the assertion of the strobe. Level sensitive Write/Read control signal. Low indicates a Read operation, SBRWI i2cXwei Input 1 and High indicates a Write operation. 4-bit wide address used to select a specific register from the register map of SBADRI i2cXadri[3:0] Input 4 the IP. 8-bit input data path used to write a byte of data to a specific register in the SBDATI i2cXdati[9:0] Input 10 register map of the IP. 10 bits used for FIFO mode. 8-bit output data path used to read a byte of data from a specific register in SBDATO i2cXdato[9:0] Output 10 the register map of the IP. 10 bits used for FIFO mode. Active-high, transfer acknowledge signal asserted by the IP, indicating the SBACKO i2cXacko Output 1 requested transfer is acknowledged. 2 2 2 *Note: X indicates the I C. X = 0 for the Right I C and X = 1 for the Left I C. SBCSI i2cXcsi Input 1 To interface with the IP, you must create a System Bus Master controller in the User Logic. In a multiple-Master configuration, the System Bus Master outputs are multiplexed through a user-defined arbiter. If two Masters request the bus in the same cycle, only the outputs of the arbitration winner reach the Slave interface. 2.1. System Bus Write Cycle Figure 2.2 shows the waveform of a Write cycle from the perspective of the System Bus Slave interface. During a single Write cycle, only one byte of data is written to the IP block from the System Bus Master. A Write operation requires a minimum three clock cycles. Edge 0 Edge 1 Edge 2 SBCLKI SBSTBI SBCSI SBRWI SBADRI[3:0] SBDATI[9:0] VALID ADDRESS VALID DATA SBDATO[9:0] SBACKO Figure 2.2. System Bus Write Operation © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 5 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note On clock Edge 0, the Master updates the address, data and asserts control signals. During this cycle the Master: Updates the address on the SBADRI[3:0] address lines Updates the data that will be written to the IP block, SBDATI[9:0] data lines Asserts the write enable SBRWI signal, indicating a write cycle Asserts the SBSTBI, selecting a specific Slave module On clock Edge 1, the System Bus Slave decodes the input signals presented by the Master. During this cycle: The Slave decodes the address presented on the SBADRI[3:0] address lines The Slave prepares to latch the data presented on the SBDATI[9:0] data lines The Master waits for an active-high level on the SBACKO line and prepares to terminate the cycle on the next clock edge, if an active-high level is detected on the SBACKO line The IP may insert wait states before asserting SBACKO, thereby allowing it to throttle the cycle speed. Any number of wait states may be added The Slave asserts SBACKO signal The following occurs on clock Edge 2: The Slave latches the data presented on the SBDATI[9:0] data lines The Master de-asserts the strobe signal, SBSTBI, and the write enable signal, SBRWI The Slave de-asserts the acknowledge signal, SBACKO, in response to the Master de-assertion of the strobe signal 2.2. System Bus Read Cycle Figure 2.3 shows the waveform of a Read cycle from the perspective of the System Bus Slave interface. During a single Read cycle, only one byte of data is read from the IP block by the System Bus Master. A Read operation requires a minimum three clock cycles. Edge 0 Edge 1 Edge 2 SBCLKI SBSTBI SBCSI SBRWI SBADRI[7:0] VALID ADDRESS SBDATI[7:0] VALID DATA SBDATO[7:0] SBACKO Figure 2.3. System Bus Read Operation © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note On clock Edge 0, the Master updates the address, and asserts control signals. The following occurs during this cycle: 1. The Master updates the address on the SBADRI[3:0] address lines 2. De-asserts the write enable SBRWI signal, indicating a Read cycle 3. Asserts the SBSTBI, selecting a specific Slave module On clock Edge 1, the System Bus Slave decodes the input signals presented by the Master. The following occurs during this cycle: 1. The Slave decodes the address presented on the SBADRI[3:0] address lines 2. The Master prepares to latch the data presented on SBDATO[9:0] data lines from the System Bus Slave on the following clock edge 3. The Master waits for an active-high level on the SBACKO line and prepares to terminate the cycle on the next clock edge, if an active-high level is detected on the SBACKO line 4. The IP may insert wait states before asserting SBACKO, thereby allowing it to throttle the cycle speed. Any number of wait states may be added. 5. The Slave presents valid data on the SBDATO[9:0] data lines 6. The Slave asserts SBACKO signal in response to the strobe, SBSTBI signal The following occurs on clock Edge 2: 1. The Master latches the data presented on the SBDATO[9:0] data lines 2. The Master de-asserts the strobe signal SBSTBI 3. The Slave de-asserts the acknowledge signal, SBACKO, in response to the Master de-assertion of the strobe Signal 3. I2C Hardened IP Cores 2 I C is a widely used two-wire serial bus for communication between devices on the same board. Every CrossLink device 2 2 2 contains two I C hardened IP cores. Either of the two cores can be operated as an I C Master or as an I C Slave. The I2C0 core has dedicated I/O pins, called USER_SCL and USER_SDA, on the CrossLink device. This is in order to support 2 the device sleep mode wakeup over I C function. The SCL and SDA pins from the I2C1 core may be connected to any pin on the device. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 7 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4. I2C Registers for CrossLink 2 Both I C cores communicate with the System Bus interface through a set of control, command, status and data registers. Table 4.1 lists the register names and their functions. 2 Table 4.1. I C Registers Summary Name SB Address [3:0] Register Width Support Modes Access 2 8 8 Both Both RW RW 2 8 8/10 Both Both RW RW 8/10 Both RW 2 10 8 8/10 FIFO mode Reg mode Both RW RW W 2 8/10 8 Both Both R R 8/10 Both R 8/10 Both R 10 FIFO mode R 2 10 FIFO mode R 2 10 FIFO mode R Register Function I2CCR1 I2CBRLSB 0001 0010 I C Control Register 1 2 I C Clock Presale register, LSB I2CBRMSB I2CSADDR/I2CFIFOSADDR 0011 0100 I2CINTCR/I2CFIFOINTCR 0101 I C Clock Presale register, MSB 2 I C Slave address/FIFO Slave Address 2 I C Interrupt Control Register/FIFO interrupt Control register I2CFIFOTHRESHOLD I2CCMDR I2CTXDR/I2CTXFIFO 0110 0111 1000 I C FIFO Threshold Register 2 I C Command Register 2 I C Transmitting Data Register/FIFO I2CRXDR/I2CRXFIFO I2CGCDR 1001 1010 I2CSR/I2CFIFOSR 1011 I C Receiving Data Register/FIFO 2 I C General Call Information Register 2 I C Status Register/FIFO Status Register I2CINTSR/I2CFIFOINTSR 1100 I C Interrupt Status Register/FIFO Interrupt Status Register I2CFIFOSMSR 1101 I C FIFO State Machine Status Register I2CFIFOTXCNT 1110 I C TXFIFO Byte Counter 2 2 I2CFIFORXCNT 1111 I C RXFIFO Byte Counter © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4.1. I2C Control Register 1 (I2CCR1) The I2CCR1 register can be read or written through System Bus. A write operation to this register, through System Bus 2 will cause the I C core to reset. 2 Table 4.2. I C Control Register 1 (I2CCR1) I2CCR1 Bit Name Default Bit7 I2CEN 0 Bit6 GCEN 0 Bit5 WKUPEN 0 Bit4 FIFO_MODE 0 Bit3 Bit2 SDA_DEL_SEL 00 Bit1 CLKSDIS 0 Bit0 Reserved 0 — R/W Yes R/W — — 0 to Disable Yes Yes Yes Yes Access R/W R/W R/W R/W 2 2 Note: A write to I C Control Register 1 will cause the I C core to reset. 2 2 2 I2CEN I C System Enable Bit – This bit enables the I C core functions. If I2CEN is cleared, the I C core is disabled and forced into idle state. 2 0: I C Disable 2 1: I C Enable GCEN Enable bit for General Call Response – Enables the general call response in Slave mode. 0: Disable 1: Enable The General Call address is defined as 0000000 and works with either 7-bit or 10-bit addressing WKUPEN Wake-up from Standby/Sleep (by Slave Address matching) Enable Bit – When this bit is 2 enabled the, I C core can send a wake-up signal to wake the device up from standby/sleep. The wake-up function is activated when the Slave Address is matched during standby/sleep mode. 0: Wakeup by Slave address matching is disabled 1: Wakeup by Slave address matching is enabled FIFO_MODE Choose between using FIFO or Register modes. 0: Register mode (default) 1: FIFO mode SDA_DEL_SEL[1:0] SDA Output Delay Selection. These two bits select the output delay (in Number of system bus clk cycles). The Base Delay is set by MSB of the I2CBRMSB. 00: NDelay = 4 * NBase_Delay + 3 (when NBase_Delay = 0, NDelay = 1) 01: NDelay = 2 * NBase_Delay + 3 (when NBase_Delay = 0, NDelay = 1) 10: NDelay = 1 * NBase_Delay + 3 (when NBase_Delay = 0, NDelay = 1) 11: NDelay = 0 CKSDIS Clock Stretching Disable Option (FIFO Mode) Disable the clock stretching in FIFO mode if desired by user for both Master and Slave mode. Then overflow error flag must be monitored. 0: Clock Stretching is Enabled 1: Clock Stretching is Disabled 4.2. I2C Command Register (I2CCMDR) The I2CCMDR register can be read or written through System Bus in Register mode. The RBUFDIS bit in the I2CCMDR register is always at default value (0) for FIFO mode. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 9 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Table 4.3. I C Command Register (I2CCMDR) I2CCMDR Bit Name Default Bit7 STA 0 Bit6 STO 0 Bit5 RD 0 Bit4 WR 0 Bit3 ACK 0 Bit2 CKSDIS 0 Bit1 RBUFDIS 0 Bit0 Reserved 0 0 to Disable Access Yes R/W Yes R/W Yes R/W — R/W — R/W No R/W No R/W — — STA Generate START (or Repeated START) condition (Master operation) STO Generate STOP condition (Master operation) RD Indicate Read from Slave (Master operation) WR Indicate Write to Slave (Master operation) ACK Acknowledge Option – when receiving, ACK transmission selection 0: Send ACK 1: Send NACK CKSDIS Clock Stretching Disable (Register Mode) – Disables the clock stretching if desired by the user for both Master and Slave mode. 0: Enable Clock Stretching 1: Disable Clock Stretching RBUFDIS Read Command with Buffer Disable – Read from Slave in Master mode with the double buffering disabled for easier control over single byte data communication scenario. 0: Read with buffer enabled as default 1: Read with buffer disabled 4.3. I2C Clock Pre-scale Register (I2CBRMSB/I2CBRLSB) The I2CBR register can be read or written through System Bus. Two System Bus writes or reads are required to access the I2CBR at different System Bus address. One address is for I2CBRLSB [7:0] and second address is for I2CBRMSB [7:0]. 2 A write operation through System Bus to either I2CBRLSB or I2CBRMSB will cause the I C core to reset. 2 Table 4.4. I C Clock Pre-scale Register (I2CBRLSB) I2CBRLSB Bit Name Bit7 Bit6 Bit5 Default Access Bit4 Bit3 I2C_PRESCALE[7:0] Bit2 Bit1 Bit0 00000000 R/W 2 Table 4.5. I C Clock Pre-scale Register (I2CBRMSB) I2CBRMSB Bit Name Default Access Bit7 Bit6 Bit5 Base_Delay[3:0] Bit4 Bit3 Bit2 Reserved Bit1 Bit0 I2C_PRESCALE[9:8] 00000000 R/W If the I2C_PRESCALE[9:0] value is ZERO, then a default value (specified inside the i2c_defines.v) will be taken to set the FSCL to 400 kHz. The default value should be set according to a default fabric clock frequency. The System Bus clock 2 2 frequency is divided by (4*(I2C_PRESCALE+1)) to produce the Master I C clock frequency supported by the I C bus. The I2CBRMSB [7:4] is utilized for trimming the Base Delay which is combined with I2CCR1[3:2] to achieve the SDA 2 output delay to meet the I C Specification requirement (300 ns). © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4.4. I2C Status Register (I2CSR/I2CFIFOSR) This address is shared by both Register mode and FIFO mode. However, the definition of each status bit is different for each mode. 2 Table 4.6. I C Status Register (I2CSR) I2CSR (Register Mode) Bit Name Default Bit7 TIP — Bit6 BUSY — Bit5 RARC — Bit4 SRW — Bit3 ARBL — Bit2 TRRDY — Bit1 TROE — Bit0 HGC — Access R R R R R R R R TIP Transmitting In Progress - This bit indicates that current data byte is being transferred for both Master and Slave mode. Note that the TIP flag will suffer half SCL cycle latency right after the start condition because of the signal synchronization. Note also that this bit could be high 2 after configuration wake-up and before the first valid I C transfer start (when BUSY is low), and it is not indicating byte in transfer, but an invalid indicator. 0: Byte transfer completed 1: Byte transfer in progress BUSY Bus Busy – This bit indicates the bus is involved in transaction. This will be set at start condition and cleared at stop. Therefore, only when this bit is high, should all other status bits be treated as valid indicators for a valid transfer. RARC Received Acknowledge – This flag represents acknowledge response from the addressed Slave during Master write or from receiving Master during Master read. 0: No Acknowledge received 1: Acknowledge received SRW Slave RW 0: Master transmitting/Slave receiving 1: Master receiving/Slave transmitting ARBL Arbitration Lost – This bit goes high if Master has lost its arbitration in Master mode. It will cause an interrupt to System Bus Host if system bus interrupts are enabled. 0: Normal 1: Arbitration Lost TRRDY Transmitter or Receiver Ready Bit – This flag indicate that a Transmit Register ready to receive data or Receiver Register if ready for read depend on the mode (Master or Slave) and SRW bit. It will cause an interrupt to System Bus Host if system bus interrupts are enabled. 0: Transmitter or Receiver is not ready 1: Transmitter or Receiver is ready TROE Transmitter/Receiver Overrun or NACK Received Bit – This flag indicate that a Transmit or Receive Overrun Errors happened depend on the mode (Master or Slave) and SRW bit, or a noacknowledges response is received after transmitting a byte. If RARC bit is high, it is a NACK bit, otherwise, it is overrun bit. It will cause an interrupt to System Bus Host if system bus interrupts are enabled. 0: Transmitter or Receiver Normal or Acknowledge Received for Transmitting 1: Transmitter or Receiver Overrun or No-Acknowledge Received for Transmitting HGC Hardware General Call Received – This flag indicate that a hardware general call is received from the Slave port. It will cause an interrupt to System Bus Host if system bus interrupts are enabled. 0: No Hardware General Call Received in Slave Mode 1: Hardware General Call Received in Slave Mode © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 11 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Table 4.7. I C FIFO Status Register (I2CFIFOSR) I2CFIFOSR (FIFO Mode) Bit Name Default Bit9 Access HGC Bit7 — Bit8 Reserved — — Bit6 HGC — Bit5 RNACK — Bit4 MRDCMPL — Bit3 ARBL — Bit2 TXSERR — Bit1 TXUNDERF — Bit0 RXOVERF — R R R R R R R R R R Hardware General Call Received – This flag indicate that a hardware general call is received from the Slave port. It will cause an interrupt to System Bus Host if SCI setup is allowed. 0: No Hardware General Call Received in Slave Mode 1: Hardware General Call Received in Slave Mode RNACK Received NACK – This flag represents acknowledge response from the addressed Slave during Master write. 0: Acknowledge received 1: No Acknowledge (NACK) is received, FIFO state machine issues a STOP and go to idle state. MRDCMPL Master Read Complete – This is only valid for Master Read mode. 0: Transaction is not completed. 1: Transaction is completed. In Master read mode, it means 1) the number of bytes read equals to the expected number, 2) Master terminates the read earlier but there is data in the RX FIFO. ARBL Arbitration Lost – This bit goes high if the Master has lost its arbitration in Master mode. 0: Normal 1: Arbitration Lost, FIFO state machine goes to idle state. TXSERR TX FIFO synchronization error. This happens when there are back-to-back commands in the FIFO. 0: No synchronization error 1: Synchronization error, the previous command is overwritten, then continues with the next data entry in the FIFO. TXUNDERF TX FIFO underflow – This indicates an error condition, mutually exclusive with clock stretching function. 0: No underflow 1: FIFO underflow, data is not valid RXOVERF RX FIFO overflow – This indicates an error condition, mutually exclusive with clock stretching function. 0: No overflow 1: FIFO overflow, data is not valid © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4.5. I2C Transmitting Data Register (I2CTXDR/I2CTXFIFO) This address is shared by both Register mode and FIFO mode. However, the definition of each status bit is different for each mode. 2 Table 4.8. I C Transmitting Data Register (I2CTXDR) I2CTXDR (Register Mode) Bit Name Default Bit7 Bit6 Bit5 Bit4 Bit3 I2C_Transmit_Data[7:0] 00000000 Access Bit2 Bit1 Bit0 W 2 I2C_Transmit_Data[7:0] 2 I C Transmit Data – This register holds the byte that will be transmitted on the I C bus during the Write Data phase. Bit 0 is the LSB and will be transmitted last. When transmitting the Slave address, Bit 0 represents the Read/Write bit. 2 Table 4.9. I C Transmitting FIFO Register (I2CTXFIFO) I2CTXFIFO (FIFO Mode) Bit Name Bit9 CMD Bit8 RSTAEN/LTXBYTE Bit7 Bit6 Bit5 0 W 0 W 0 W 0 W 0 W Default Access Bit4 Bit3 RXBYTE 0 W 0 W Bit2 Bit1 Bit0 0 W 0 W 0 W The I2CTXFIFO is write only. However a read to this location during FIFO mode will cause the I2CTXFIFO to be reset (reset the pointers). The 2 MSBs are the command bits, while the 8 LSBs are for data or Slave address. The 8-bit data can be interpreted differently depending on the value of Bit9. The CMD bit and the RSTAEN/LTXBYTE bit are used when the IP is in Master mode. When CMD=1, the range of Bits[4:0] is 0 to 31, where a “0” indicates receiving 1 byte, a “1” receiving 2 bytes, and a “31” receiving 32 bytes,. Therefore, an 2 I C Read must receive at least 1 byte. 10: Bits [4:0] of this byte is the number of bytes to be received (in Master mode). CMD, RSTAEN Following data transaction should be sent using a STOP then a START. 11: Bits [4:0] of this byte is the number of bytes to be received (in Master mode). st Following data transaction should be sent using a START/ReSTART. The 1 data byte should always have RSTAEN bit set to 1. 00: Bits [7:0] of this byte are data bits. If this is the last data byte in the TXFIFO, then CMD, LTXBYTE depending on the CKSDIS bit, Master Write will either go into clock stretching (CKSDIS=0), or TXFIFO will underflow (CKSDIS=1). 01: Bits [7:0] of this byte are data bits. If this is the last data byte in TXFIFO, this indicates the last byte to be transferred and a STOP will be issued. If this is not the last byte in TXFIFO, then this bit is ignored. RXBYTE[7:5] Not used when CMD=1 Data byte when CMD=0 RXBYTE[4:0] RXBYTE value when CMD=1 Data byte when CMD=0 In Master mode, if users want to abort the current transaction, they should reset the TXFIFO (by issuing a read to TXFIFO or use FIFO_RST signal). When the TXFIFO is reset while the state machine is in transmit mode, it will issue a STOP after the current byte is transmitted. When the TXFIFO is reset and the state machine is in receive mode, it will issue a NACK+STOP. This is to make sure the 2 I C bus is appropriately released. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 13 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4.6. I2C Receiving Data Register (I2CRXDR/I2CRXFIFO) This address is shared by both Register mode and FIFO mode. However, the definition of each status bit is different for each mode. 2 Table 4.10. I C Receiving Data Register (I2CRXDR) I2CRXDR (Register Mode) Bit Name Default Bit7 Bit6 Bit5 Bit4 Bit3 I2C_Receive_Data[7:0] — Access Bit2 Bit1 Bit0 R 2 I2C_Receive_Data[7:0] 2 I C Receive Data – This register holds the byte captured from the I C bus during the Read Data phase. Bit 0 is LSB and received last. 2 Table 4.11. I C Receiving FIFO Register (I2CRXFIFO) Bit Name Bit9 Reserved Bit8 DFIRST Bit7 — R — R — R Default Access I2CRXFIFO (FIFO Mode) Bit6 Bit5 Bit4 Bit3 DATA[7:0] — R — R — R — R Bit2 Bit1 Bit0 — R — R — R The I2CRXFIFO register is read only. However a write to this location during FIFO mode will cause the I2CRXFIFO to reset (reset the pointers). DFIRST Last byte of data DATA[7:0] 0: Normal data 1: First byte received after a Start or a ReStart is detected Data received 4.7. I2C General Call Data Register 2 Table 4.12. I C General Call Data Register (I2CGCDR) I2CGCDR Bit Name Bit7 Bit6 Default Access I2C_GC_Data[7:0] Bit5 Bit4 Bit3 I2C_GC_Data[7:0] Bit2 Bit1 Bit0 — R 2 I C General Call Data – This register holds the second (command) byte of the General Call 2 transaction on the I C bus. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4.8. I2C Slave Address MSB Register (I2CSADDR/I2CFIFOSADDR) This address is shared by both Register mode and FIFO mode. However, the definition of each status bit is different for each mode. 2 Table 4.13. I C Slave Address MSB Register (I2CSADDR) I2CSADDR (Register Mode) Bit 7 Bits Addressing 10 Bits Addressing Bit7 — A9 Bit6 — A8 Bit5 — A7 Bit4 A6 A6 Default Access Bit3 A5 A5 Bit2 A4 A4 Bit1 A3 A3 Bit0 A2 A2 00000000 R/W 2 Table 4.14. I C Slave Address MSB Register (I2CFIFOSADDR) I2CFIFOSADDR (FIFO mode) Bit 7 Bits Addressing Bit9 — Bit8 — Bit7 — Bit6 A6 Bit5 A5 Bit4 A4 Bit3 A3 Bit2 A2 Bit1 A1 Bit0 A0 10 Bits Addressing Default A9 A8 A7 A6 A5 A4 00000000 A3 A2 A1 A0 Access 4.9. R/W I2C Interrupt Control Register (I2CINTCR/I2CFIFOINTCR) This address is shared by both Register mode and FIFO mode. However, the definition of each status bit is different for each mode. 2 Table 4.15. I C Interrupt Control Register (I2CINTCR) Bit Name Default 0 to Disable Access I2CINTCR (Register Mode) Bit5 Bit4 Bit7 Bit6 Bit3 Bit2 Bit1 Bit0 INTCLREN 0 YES INTFRC 0 YES Reserved — — Reserved — — ARBLEN 0 YES TRRDYEN 0 YES TROEEN 0 YES HGCEN 0 YES R/W R/W — — R/W R/W R/W R/W INTCLREN Auto Interrupt Clear Enable – Enable the interrupt flag auto clear when the I2CINTSR has been read. INTFRC Force Interrupt Request On – Force the Interrupt Flag set to improve testability. 0: Normal operation 1: Force the Interrupt Request ARBLEN Arbitration Lost Interrupt Enable –Enable Arbitration Lost interrupt TRRDYEN Transmit/Receive Register Ready Interrupt Enable – Enable TRRDY interrupt TROEEN Transmit/Receive Register Overrun Interrupt Enable – Enable TROE interrupt HGCEN General Call Interrupt Enable – Enable General Call interrupt © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 15 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Table 4.16. I C Interrupt Control Register (I2CFIFOINTCR) I2CFIFOINTCR (FIFO Mode) Bit Name Default 0 to Disable Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTCLREN INTFRC Reserved HGCEN RNACKEN MRDCMPLEN ARBLEN TXSERREN TXUNDERFEN RXOVERFEN 0 0 0 0 0 0 0 0 0 0 YES YES YES YES YES YES YES YES YES YES R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Access INTCLREN Auto Interrupt Clear Enable – Enable the interrupt flag auto clear when the I2CINTSR been read. INTFRC Force Interrupt Request On – Force the Interrupt Flag set to improve testability. 0: Normal operation 1: Force the Interrupt Request HGCEN General Call Interrupt Enable – Enable General Call interrupt RNACKEN Receive NACK Interrupt Enable MRDCMPLEN Master Read Complete Enable ARBLEN Arbitration Lost Interrupt Enable — Enable Arbitration Lost Interrupt TXSERREN TX FIFO Synchronization Error Interrupt Enable TXUNDERFEN TXFIFO Underflow Interrupt Enable RXOVERFEN RXFIFO Overflow Interrupt Enable 4.10. I2C Interrupt Status Register (I2CINTSR/I2CFIFOINTSR) This address is shared by both Register mode and FIFO mode. However, the definition of each status bit is different for each mode. A System Bus write to this register with a particular bit set will cause the corresponding interrupt request flags cleared. If Bit7 of I2CINTCR, or Bit9 of I2CFIFOINTCR is set, then a read operation on the Interrupt Status Register will clear all the interrupt status flags. 2 Table 4.17. I C Interrupt Status Register (I2CINTSR) Bit Name Default Access Bit7 Bit6 — — — — Bit5 Reserved — — I2CINTSR (Register Mode) Bit4 Bit3 ARBL — — Bit2 TRRDY Bit1 TROE Bit0 HGC — R/W — R/W — R/W — R/W ARBL Arbitration Lost Interrupt Status Flag TRRDY Transmit/Receive Register Ready Interrupt Status Flag TROE Transmit/Receive Register Overrun Interrupt Status Flag HGC General Call Interrupt Status Flag © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Table 4.18. I C Interrupt Status Register (I2CFIFOINTSR) I2CFIFOINTSR (FIFO Mode) Bit Name Default Bit9 Access R/W — Bit8 Bit7 Reserved — — R/W R/W Bit6 HGC — Bit5 RNACK — Bit4 MRDCMPL — Bit3 ARBL — Bit2 TXSERR — Bit1 TXUNDERF — Bit0 RXOVERF — R/W R/W R/W R/W R/W R/W R/W HGC General Call Interrupt Status Flag RNACK NACK Interrupt Status Flag MRDCMPL Master Read Completion Interrupt Status Flag ARBL Arbitration Lost Interrupt Status Flag TXSERR TXFIFO Synchronization Error Interrupt Status Flag TXUNDERF TXFIFO Underflow Interrupt Status Flag RXOVERF RXFIFO Overflow Interrupt Status Flag 4.11. I2C FIFO Threshold Register (I2CFIFOTHRESHOLD) This register stores the FIFO threshold values. This is a read and write register used in FIFO mode only. 2 Table 4.19. I C FIFO Threshold Register (I2CFIFOTHRESHOLD) Bit Name Bit9 Bit8 — — Default Access I2CFIFOTHRESHOLD (FIFO mode) Bit7 Bit6 Bit5 Bit4 RXFIFO_AF_VAL — R/W — — — RXFIFO_AF_VAL 5-bit Almost Full value for the RX FIFO. TXFIFO_AE_VAL 5-bit Almost Empty value for the TX FIFO. Bit3 Bit2 TXFIFO_AE_VAL Bit1 Bit0 — — R/W — — 4.12. I2C FIFO TX Byte Counter (I2CFIFOTXCNT) 2 This is a read only register. It stores the current count of data bytes that have been transmitted to the I C port. The number of bytes is accumulative until the counter is cleared. A write to this register or assertion of FIFO_RST signal will cause the counter to be cleared. 2 Table 4.20. I C FIFO TX Byte Counter (I2CFIFOTXCNT) Bit Name Default Access Bit9 Bit8 Reserved — TX_BYTE_CNT — Bit7 — I2CFIFOTXCNT (FIFO mode) Bit6 Bit5 Bit4 Bit3 TX_BYTE_CNT — — — — Bit2 Bit1 Bit0 — — — R/W 2 The number of data bytes that have been transmitted to the I C port. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 17 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 4.13. I2C FIFO RX Byte Counter (I2CFIFORXCNT) This is a read only register. It stores the current count of data bytes that have been received at the RXFIFO. The number of bytes is accumulative until the counter is cleared. A write to this register or assertion of FIFO_RST signal will cause the counter to be cleared. 2 Table 4.20. I C FIFO RX Byte Counter (I2CFIFORXCNT) Bit Name Default Bit9 Bit8 Reserved — — Access RX_BYTE_CNT Bit7 — I2CFIFORXCNT (FIFO mode) Bit6 Bit5 Bit4 — Bit3 RX_BYTE_CNT — — — Bit2 Bit1 Bit0 — — — R/W The number of data bytes that have been received at the RX FIFO. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 5. I2C Read/Write Flow Chart 2 Figure 5.1 shows a flow diagram for controlling Master I C reads and writes initiated via the System Bus interface. Start TXDR <= I 2 C addr + ‘R’ CMDR <= 0x94 (STA+WR) TXDR <= I 2 C addr + ‘W’ CMDR <= 0x94 (STA+WR) Wait for TRRDY Write more data? Wait for SRW N CMDR <= 0x24 (RD) Y TXDR <= WRITE_DATA CMDR <=0x14 (WR) Last Read? Y N Read data? Y Wait for TRRDY N CMDR <= 0x44 (STOP) READ_DATA <= RXDR Wait * CMDR <= 0x6C (RD+NACK+STOP) Wait for TRRDY READ_DATA <= RXDR *Real-Time Delay Requirement Read only 1 byte: min < wait < max Read last of 2+ bytes: 0 < wait < max Done where: min = 2 * (1/f SCL ) max = 7 * (1/f SCL ) 2 Figure 5.1. I C Master Read/Write Example (via System Bus) © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 19 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Figure 5.2 shows a flow diagram for reading and writing from an I C Slave device via the System Bus interface. Start CMDR <=0x04 (CKSDIS) IRQEN <= 0x00 N wait for not BUSY Write reply data? Y discard <= RXDR discard <= RXDR IRQEN <= 0x04 (TRRDY)* wait for SRW Idle TXDR <= OUT_DATA wait for TRRDY Write more data? N Y IN_DATA <= RXDR IRQ <= 0x04* wait for TRRDY N Read more data? TXDR <= OUT_DATA IRQ <= 0x04* Y * Required only for IRQ driven algorithms 2 Figure 5.2. I C Slave Read/Write Example (via System Bus) © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 0x44(STOP) 0x14(WR) Write IRQTRRDY Write IRQTRRDY Write I2C_1_TXDR D[7:0] I2C_1_SR[RARC] I2C_1_IRQ[IRQTRRDY] I2C_1_SR[TRRDY] I2C_1_SR[SRW] I2C_1_SR[BUSY] 0x94(Start+WR) I2C_1_CMDR AD[(6:0),W] I2C_1_TXDR SDA SCL Master Start 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0x14(WR) Write 9 Ack from Slave 1 D7 D6 D5 D4 D3 D2 Write I2C_1_TXDR D1 D[7:0] D0 9 Ack from Slave 1 D7 D6 D5 D4 D3 Write IRQTRRDY D2 D1 D0 9 Ack from Slave Master Stop Idle 6. I2C Functional Waveforms 2 Figure 6.1. Master – I C Write © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 21 Write IRQTRRDY Write IRQTRRDY I2C_1_IRQ[IRQTRRDY] I2C_1_SR[SRW] I2C_1_SR[TRRDY] 0x94 (START+WR) I2C_1_CMDR I2C_1_SR[BUSY] I2C_1_RXDR AD[(6:0),W] I2C_1_TXDR SDA SCL Master Start/ Restart 1 AD6 AD5 AD4 AD3 Write IRQTRRDY AD2 AD1 AD0 Read 9 Ack from Slave 1 D7 0x24 (RD) D6 D5 D4 D3 D2 D1 D0 9 Ack from Master 1 D7 D[7:0] D6 D5 D4 D3 D2 D1 Read I2C1_RXDR 0x6C (RD+NACK+STOP) D0 9 Nack from Master D[7:0] Stop from Master Read I2C1_RXDR Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Figure 6.2. Master – I C Read © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 TN1309-1.0 Write IRQTRRDY Write IRQTRRDY I2C_1_IRQ[IRQTRRDY] I2C_1_SR[TRRDY] I2C_1_SR[SRW] I2C_1_SR[BUSY] I2C_1_RXDR I2C_1_TXDR SDA SCL Start from Master 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write 9 Ack from Slave 1 D7 D6 D5 D4 D3 D2 D1 D0 9 Ack from Slave 1 D7 D[7:0] D6 D5 D4 D3 D2 D1 Read I2C_1_RXDR D0 9 Ack from Slave D[7:0] Stop from Master Read I2C_1_RXDR Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Figure 6.3. Slave – I C Write © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 23 Write IRQTRRDY Write I2C_1_TXDR Write IRQTRRDY Write I2C_1_TXDR D[7:0] I2C_1_SR[RARC] I2C_1_IRQ[IRQTRRDY] I2C_1_SR[TRRDY] I2C_1_SR[SRW] I2C_1_SR[BUSY] I2C_1_RXDR I2C_1_TXDR SDA SCL Start from Master 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Read 9 Ack from Slave 1 D7 D6 D5 D4 D3 D2 D1 D[7:0] D0 9 Ack from Master 1 D7 D6 D5 D4 D3 D2 Write IRQTRRDY D1 D0 9 No Ack from Master Stop from Master Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note 2 Figure 6.4. Slave – I C Read © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 TN1309-1.0 Advanced CrossLink I2C Hardened IP Reference Guide Preliminary Technical Note References For more information, refer to the following documents: DS1055, CrossLink Family Data Sheet TN1301, CrossLink High-Speed I/O Interface TN1302, CrossLink Hardware Checklist TN1303, CrossLink Programming and Configuration Usage Guide TN1304, CrossLink sysCLOCK PLL/DLL Design and Usage Guide TN1305, CrossLink sysI/O Usage Guide TN1306, CrossLink Memory Usage Guide TN1307, Power Management and Calculation for CrossLink Devices TN1308, CrossLink I2C Hardened IP Usage Guide Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. Revision History Date May 2016 Version 1.0 Change Summary First preliminary release. © 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. TN1309-1.0 25 th th 7 Floor, 111 SW 5 Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com