Fujitsu Microelectronics Europe
Application Note
MCU-AN-390034-E-V19
F²MC-16LX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
EXTERNAL BUSINTERFACE
APPLICATION NOTE
External Businterface
Revision History
Revision History
Date
25 April 00
26th April 00
Issue
th
V1.0 (TKa/MEn) started
V1.1 (TKa/MEn) Data line Timing with additional 22pF load capacitance
added
th
10 Mai 00
V1.2 (TKa) Some comments added at the end of chapter 1. Usage of
upper address lines A16-A23 as IO ports explained.
27th June 00
V1.3 (TKa) Some minor comments modified
18th Sept. 00
V1.4 (MSt) Schematics improved
th
18 Mai. 01
V1.5 (HWe) Software added
11th April. 02
V1.6 (HWe) Bus-Access-table added
19 th March 03 V1.7 (HWe) new format, Type errors corrected
10th June 2003 V1.8 (MSt) Ressource overview added
4th June 2004
V1.9 (HWe) chapter 2.5, chapter 3.1 and Appendix D updated
This document contains 33 pages.
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© Fujitsu Microelectronics Europe GmbH
External Businterface
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (eg. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu
Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer´s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
injury, assets of substantial value, loss of profits, interruption of business operation,
loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
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External Businterface
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION ............................................................................................................... 5
2 USING THE EXTERNAL BUS INTERFACE – THE HARDWARE..................................... 6
2.1 Introduction................................................................................................................. 6
2.2 Connecting a SRAM directly to the external bus interface .......................................... 6
2.2.1 Schematic....................................................................................................... 7
2.2.2 Bus-Timing ..................................................................................................... 8
2.2.3 Increasing Bus Load....................................................................................... 9
2.2.4 Using pull up resistors for the data lines ....................................................... 12
2.2.5 Input High level............................................................................................. 13
2.2.6 Summary...................................................................................................... 13
2.3 Connecting a SRAM to the external bus interface using a bus transceiver ............... 14
2.3.1 Schematic..................................................................................................... 15
2.4 Using x16 organised SRAMs .................................................................................... 16
2.4.1 Schematic..................................................................................................... 17
2.5 Using A16-A23 as general I/O ports ......................................................................... 18
3 USING THE EXTERNAL BUS INTERFACE – THE SOFTWARE.................................... 19
3.1 Introduction............................................................................................................... 19
3.2 8-Bit Memory-Access................................................................................................ 21
3.3 16-Bit Memory-Access.............................................................................................. 22
3.4 Bus-Access-Modes and Bus-Control-Signals: 8 Bit mode......................................... 23
3.5 Bus-Access-Modes and Bus-Control-Signals: 16 Bit mode....................................... 24
4 APPENDIX A: METHOD 4............................................................................................... 25
5 APPENDIX B: METHOD 5............................................................................................... 26
6 APPENDIX C: TIMING-DIAGRAMS ................................................................................ 27
7 APPENDIX D: RESOURCE OVERVIEW......................................................................... 29
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© Fujitsu Microelectronics Europe GmbH
External Businterface
Chapter 1 Introduction
1 Introduction
This application note reflects the external businterface that can be found on some devices of
the Fujitsu 16LX-series, e.g. MB90495, MB90540 etc.
Both hardware and software hints are given.
© Fujitsu Microelectronics Europe GmbH
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External Businterface
Chapter 2 Using the external bus interface – The Hardware
2 Using the external bus interface – The Hardware
In the following description, the external bus interface of Fujitsu microcontrollers will be
discussed. It describes how external devices can be connected to the external bus interface
(e.g. SRAM) and offers some suggestions. Timing calculations and estimations are made as
well to have a better understanding of the design. The data measured in the following
described tests are just example measurements, the measured timings are no data which
are specified in the DS of the microcontroller series.
2.1 Introduction
The external bus interface of the Fujitsu 16LX microcontroller series, is mostly a multiplexed
8/16 bit address/data bus. The address/data lines are AD00 to AD15, the upper 8Bit
addresses are A16-A24. The used control signals of the external bus are RDY, WRL, WRH,
HRQ, HAK, CLK , RD and ALE. During internal access cycles, the AD00 - AD15 are tristate,
the control signals are switched to inactive state. The upper address lines A16-A23 are
driven with the value used for the last external bus cycle (so it can happen, that if a higher
address line is used for CE of the SRAM, the SRAM is still enabled after the last cycle). In
general, all signals of the microcontroller are specified for CMOS level. This means that the
minimum input high voltage is 0.8Vcc, the maximum input low voltage is 0.2Vcc. These
restrictions must be considered if an external device is connected to the bus. The following
description is based on the MB90F549, but the same situation exist for all current series of
the 16LX family, with an external bus interface.
2.2 Connecting a SRAM directly to the external bus interface
If e.g. an additional SRAM is connected to the external bus interface, the easiest method can
be found in Figure 1.1 on the next page. An address latch is used to latch the address of the
multiplexed address data bus. The latch used in this example is CD74ACT573 from Texas
Instruments, which has a max. propagation delay time of 9.4ns. The output enable
propagation delay time of the latch must not be considered, because the latch is always
enabled (OE connected to GND).
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Chapter 2 Using the external bus interface – The Hardware
2.2.1 Schematic
Figure 2-1: Example schematic how to connect directly a SRAM to the external bus interface
© Fujitsu Microelectronics Europe GmbH
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Chapter 2 Using the external bus interface – The Hardware
2.2.2 Bus-Timing
Figure 1.2 reflects the timing diagram of a read-cylcle of the MB90F549. This diagram shows
the timing in case of 0 wait states. To guarantee that the CPU is reading correct data, it must
be ensured that the data on the bus are valid after tRLDV ( (3*tcp/2 -60) ns ) after RD
becoming Low. Assuming that the internal operating frequency is 16MHz, tRLDV = 33,75ns.
This means e.g., that during the time tRLDV, the data signals must rise up to the level 0.8Vcc,
to read a logic 1 if a read cycle from the SRAM is performed. This time depends on tOE output enable time of the SRAM data bus-, the capacitive load of the data bus and the
output drive capability of the SRAM. Normally also SRAMs supply CMOS compatible output
level, but high bus load will influence the rise time of the data signals and so the total access
time. Additionally, most SRAM suppliers specify TTL output level only (e.g. 2.5V@1mA.).
Some SRAM suppliers specify also higher output levels (e.g. 4.5V@ 100MA). So the
datasheet of the corresponding device must be checked in detail.
Additional wait states
can be inserted here
Figure 2-2: Bus Timing of external bus interface, 0 Wait states
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External Businterface
Chapter 2 Using the external bus interface – The Hardware
2.2.3 Increasing Bus Load
Some test have been done using the DevKit16 starterkit to examine the behaviour of the bus
interface in more detail.. On the DevKit16, SRAMs of HY628100A-LG55 are used, which are
connected directly to the external bus interface. The maximum tOE of the SRAM is specified
to 25ns On the starterkit, the final measured high level on all data lines AD00-AD15 was
>4.8V. The following table shows the measured rise time (0.2Vcc to 0.8Vcc) of the different
data lines and the total access time tRLDV .(RD = 0.2Vcc to data line = 0.8Vcc) for an SRAM
read cycle.
The table shows an average rise time of 10.875ns and a total average access time tRLDV of
22.575ns. In the DS of the MB90F549, less than 33.75ns @16MHz is requested for read
cycles with 0 wait states. The measured signal waveforms and access times have shown,
that on the DevKit16 all signals meet the requirements, and no heavy bus load exist.
For further detailed tests, the capacitive load of the data bus has been increased. The
results are shown in the next table. It can be seen, that the rise time increases with
increasing load capacitance. The table shows that an additional capacitive bus load of about
22pF increases the rise time for about 10ns. The total data access time is increased by
about 15ns.
data rise time (0.2Vcc to 0.8Vcc) in ns
Total data access time tRLDV
(RD=0.2Vcc to ADXX=0.8Vcc) in ns
AD01
12.2
25
AD03
11.2
23.6
AD05
14
27.6
AD07
15.4
25.6
AD09
8.2
16.6
AD11
8.4
21.2
AD13
9
18.2
AD15
8.6
17.8
Average
10.875
22.575
data rise time (0.2Vcc to 0.8Vcc) in ns
Total data access time tRLDV
(RD=0.2Vcc to ADXX=0.8Vcc) in ns
AD05
22
39
AD09
16.8
31.4
AD11
20.2
34.4
Average
19.67
34.93
data rise time (0.2Vcc to 0.8Vcc) in ns
Total data access time tRLDV
(RD=0.2Vcc to ADXX=0.8Vcc) in ns
AD05
32.8
48.4
AD09
27.6
42.2
AD11
27
42.2
Average
29.13
44.27
With 22pF capacitive Load:
With 48pF capacitive Load:
Table 1: Example measurements for signal rise time and data access time
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Chapter 2 Using the external bus interface – The Hardware
The maximum specified input capacitance of the Fujitsu microcontroller is 80pF, the typical
value is specified to 10pF. Due to the specified maximum input capacitance of the
microcontroller and regarding a worst case scenario, additional wait state for external bus
accesses would be necessary. During the test no errors occurred using 0 wait states up to
22pF additional bus load. Errors occured with 48pF bus load, which could be removed by the
insertion of one wait state.
The following figures 1-3 to 1-6 show the rise time of AD03 and AD13 as an example of the
measured timing. The figure 3, 4 show the normal timing. The figures 5, 6 show the timing
with an additional bus load of 22pF.
Figure 2-3: AD03 via RD timing diagram
Figure 2-4: AD13 via RD timing diagram
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Chapter 2 Using the external bus interface – The Hardware
Figure 2-5: AD03 via RD timing diagram with additional capacitive load of 22pF
Figure 2-6: AD13 via RD timing diagram with additional capacitive load of 22pF
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Chapter 2 Using the external bus interface – The Hardware
2.2.4 Using pull up resistors for the data lines
The tests have also been performed using additional pull up resistors. But even 1K Ohm pull
up resistors had no impact on the timing itself. The output level of the SRAM was always >
0.8Vcc even without pullups, as shown in the two figures for ASD03 and AD13 above. This
may be due to the low output resistance of the SRAM output, so the pull up resistor did not
influence the bus timing.
So additional pull up resistors can only help to increase the output level, if the supplied
output level of the SRAM is not sufficient (<0.8Vcc). The following calculations try to make
an approximation of the pull up resistance which should be used.
The specified output level of the used SRAM is 2.4V @1mA. Assuming a worst case, the
pull up resistance must pull the output voltage level to at least 0.8Vcc starting from 2.4V. The
time needed to rise from 2.4V to 0.8Vcc can be calculated by:
V(t) = Vcc - [ (Vcc-Vi) e-t/RC]
V(t) - voltage at specified time
Vi - voltage at t=0 (initial voltage)
R - active resistance for capacitive load mechanism
C capacitive load (bus load)
Therefore the pull-up resistance can be calculated with Vi = 2.4V, V(t) = 0.8Vcc by:
R = -tRC/[ C*ln{(Vcc - 0.8Vcc)/(Vcc -2.4V)} ]; tRC - rise time from 2.4V to 0.8Vcc
Now tRC must be approximated. This can be done via the equation:
tRLDV < tOE + tRC
tOE is the SRAM output enable time, specified in the Datasheet of the SRAM,
assumed, that this time is needed to achieve at least TTL level (2.4V).
So R can be calculated with:
R = -(tRLDV - tOE)/[ C*ln{(Vcc - 0.8Vcc)/(Vcc -2.4V)} ]
To achieve a 0 Wait state data access, the following calculation is done. A tOE time of about
25ns is assumed, for C a value of 30pF was assumed. With tRLDV.= 33.75ns this leads to R =
279Ohm. This resistance would be necessary to have an output voltage of 0.8Vcc available
33.75ns after RD Low. With this low resistance it is critical to achieve an accurate low level,
additionally this will increase the power consumption. So a higher pull up resistance must be
used, with the disadvantage that the access time will increase. So additional wait states can
not be avoided in that case.
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External Businterface
Chapter 2 Using the external bus interface – The Hardware
2.2.5 Input High level
Additional tests have been performed to measure the input high level of some
microcontrollers. The following table 1-2 and 1-3 shows the results of these example
measurements. Nevertheless, the specified min. input high level is 0.8Vcc.
Device 1
Device 2
Device 3
Device 4
Device 5
Average
Input High level in V
2.96
2.98
2.96
2.9
2.9
2.94
Input Low level in V
1.93
1.84
1.91
1.94
1.85
1.894
Table 2: MB90F543 voltage level @Vcc = 5V, at about 25 degree
Device 1
Device 2
Device 3
Device 4
Device 5
Average
Input High level in V
2.97
2.91
2.98
2.9
3
2.952
Input Low level in V
1.86
1.92
1.94
1.94
1.85
1.902
Table 3: MB90F543 voltage level @Vcc = 5V, at about 60 degree
The table shows that the measured average minimum input high level is about 3V, which
would improve the above timing considerations. The DS specifies worst case 0.8Vcc!
2.2.6 Summary
The approximations above show that the capacitive load has an influence on the bus timing
which is on the other side quite hard to estimate. Assuming worst case scenarios will lead to
additional wait states, and/or using faster SRAMs.
For calculations for the external bus interface at least the following electrical specifications of
the used SRAM and microcontroller are important:
•
Output Drive Level of the SRAM at a specified output current (must be >0.8*Vcc to meet
the requirements of the microcontroller). The input leakage current of the controller and
the additional input current of other devices connected to the external businterface must
be considered for this calculation.
•
Access time at a specified capacitive load (must be <33.75ns @16MHz internal
operating frequency of the microcontroller, to achieve 0 wait states). The input
capacitance of all devices connected to the businterface must be considered for this
calculation.
The following data can be found in the corresponding SRAM Datasheets:
•
M5M5256DP-45, [email protected], tOE=25ns@30pF
•
M5M5256DP-70, [email protected], tOE=35ns@30pF
•
K6R1016C1C-C20, [email protected], tOE=9ns@30pF
•
K6E0808C1E-C15, [email protected], tOE=7ns@30pF
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External Businterface
Chapter 2 Using the external bus interface – The Hardware
Using e.g. M5M5256DP-45 will lead to 0 wait states, if the typical input capacity of the
microcontroller is assumed of 10pF and the total capacitive bus load is below 30pF. For
worst case calculations, the max. specified input capacity of 80pF of the microcontroller must
be considered, so 0 wait states could not be used in this case, except the SRAM can be
specified for higher busloads. In this case, the usage of faster SRAMs can help to
workaraound this problem.
Pull-up resistors for the data lines can bring the data lines to the requested input voltage of
0.8Vcc, but the value of the resistor must be approximated, but it is quite likely that in this
case additional wait states are necessary. So for heavy bus loads, an additional external bus
transceiver should be considered for fast access cycles, which will be discussed in the next
chapter.
2.3 Connecting a SRAM to the external bus interface using a bus transceiver
A further method to connect a SRAM to the external bus interface is to use an additional bus
line transceivers. In the example shown in figure 1-7 a Texas Instruments driver
SN74ACT16245 has been used.
Also an address latch is necessary to latch the address of the multiplexed address/data bus.
The pull-ups on the data bus are assigned to avoid floating inputs for the bus transceiver.
The latch used in this example is CD74ACT573 from Texas instruments, which has a max.
propagation delay time of 9.4ns. The output enable propagation delay time of the latch must
not be considered, because the latch is always enabled (OE connected to GND). The valid
time of the ALE signal must fit to the timing requirements of the latch. Example
measurements have shown, that the ALE signal is active for about 25ns.
Based on this and the read timing of the CPU, the following calculation can be done:
tRLDV < tOE + tpd
tRLDV - Read low to data valid time, after this time data must be valid at data inputs of the
CPU
tOE - output enable time of the SRAM
tpd - propagation delay of SN74ACT16245
The propagation delay time of the SN74ACT16245 is about max 10ns. This results in a
required tOE time for the used SRAM of about max. 23ns.
The advantage of using a bus transceiver in ACT technology is that this device have CMOS
output level and TTL compatible input levels. On the other hand an additional transceiver
increases costs and needs more PCB layout space. Instead of ACT bus transceivers, also
HCT logic can be used. But due to the higher propagation delay of this technology,
additional wait states or faster SRAMs could be necessary. For worst case calculations, it
can also happen that the line transceiver and the SRAM are driving the same data lines.
This is because the transceiver needs some time to switch the data direction and the SRAM
to disable its outputs, at the end of each read cycle. On the other hand, at the end of a cycle,
new data can be present on the bus tcp/2 -10ns after RD high. This time should be sufficient
for the transceiver to switch the direction, so that the CPU and the transceiver are not driving
the same bus.
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External Businterface
Chapter 2 Using the external bus interface – The Hardware
2.3.1 Schematic
Figure 2-7 : Example schematic how to connect a SRAM to the external bus interface using bus drivers
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Chapter 2 Using the external bus interface – The Hardware
2.4 Using x16 organised SRAMs
If a x16 organised SRAM is used, like it is shown in figure 1-8, the timing calculations must
consider additional propagation delays.. This delay is due to additional logic for the RD, WR
control signals for the SRAM. Due to the bus transceiver and the additional logic, also the
hold time of the data for the SRAM is influenced.
In this example a Toshiba SRAM TC551664-15 has been used.
Due to the propagation delay of the AND logic gates, the required access time for 0 wait
states read cycles, can be calculated by
tRLDV < tOE + tRC + tpd gate, if no bus transceiver is used.
If a bus transceiver is used, the read access time can be calculated with: tRLDV < tOE + tpd gate +
tpd transceiver
So the usage of x16 organised SRAMs lead to higher timing restrictions, especially if 0 wait
states are required. So very fast SRAMs should be used to meet these requirements.
The following schematic shows an example.
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External Businterface
Chapter 2 Using the external bus interface – The Hardware
2.4.1 Schematic
Figure 2-8 : Example schematic how to connect a SRAM to the external bus interface using bus drivers
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Chapter 2 Using the external bus interface – The Hardware
2.5 Using A16-A23 as general I/O ports
The upper address lines A16-A23 of the external bus interface can also be used as general
I/O ports. For that reason the register HACR is used. By default, if an external bus interface
is used, after power-on reset, these lines are used as address lines! For that reason, care
must be taken, if these port lines are intended to be used as I/O ports.
After power-on, these port lines are used as address lines if the Internal ROM / External bus
mode is used or if the External ROM / External bus mode is used. So the port lines will drive
high or low level, which level cannot be predicted. If some of these port lines should be used
as I/O ports, it must be considered that a high or low pulse is output on these lines, until the
lines are set to I/O ports by initialising the HACR register. If e.g. a 4MHz crystal is used, and
the HACR register is initialised right at the beginning in the startup code, this pulse will take
about 1Ms High or Low.
There is no workaround without using additional external logic around, because of the
default setting of the HACR register after power-on.
Take care that some 16LX microcontroller will not allow using the output of peripheral
resources other than simple I/O for A16-A23, if BUSMODE INTROM_EXTBUS is selected.
See also Appendix D.
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External Businterface
Chapter 3 Using the external bus interface – The Software
3 Using the external bus interface – The Software
3.1 Introduction
The following description will investigate the external bus interface from the software side.
Although there are many different methods to access to external addresses, some major
methods will be discussed to see advantages and disadvantages. In addition, some tips will
be given.
Note:
All examples are based on ‚FFMC-16 Family Softune Workbench V30L26‘ and the MB90F540, but the same
situation exists for all current series of the 16LX family, with an external bus interface.
In order to use the external bus interface some settings has to be done within the
‚start.asm‘- file:
;====================================================================
; 4.8
External Bus Interface
;====================================================================
#set
SINGLE_CHIP
0
; all internal
#set
INTROM_EXTBUS
1
; mask ROM, FLASH, or OTP ROM used
#set
EXTROM_EXTBUS
2
; full external bus (INROM not used)
#set
BUSMODE INTROM_EXTBUS
; <<< set bus mode (see mode pins)
; If BUSMODE is "SINGLE_CHIP", ignore remaining bus settings.
#set
AUTOWAIT_IO
0
; <<< 0..3 waitstates for IO area
#set
AUTOWAIT_LO
0
; <<< 0..3 for lower external area
#set
AUTOWAIT_HI
0
; <<< 0..3 for higher external area
#set
ADDR_PINS B'00000000
; <<< select used address lines
;
A23..A16 to be output.
; This is the value to be set in HACR-register. "1" means: pin used as
; IO-port. (B'10000000 => A23 not used, B'00000001 => A16 not used)
#set
BUS_SIGNAL B'00000100
; <<< enable bus control signals
;
|||||||+-- ignored
;
||||||+--- bus width lower memory (0:16, 1:8Bit)
;
|||||+---- output WR signal(s)
;
||||+----- bus width upper memory (0:16, 1:8Bit)
;
|||+------ bus width ext IO area
(0:16, 1:8Bit)
;
||+------- enable HRQ input
(1: enabled
)
;
|+-------- enable RDY input
(1: enabled
)
;
+--------- output CLK signal
(1:enabled
)
(1: enabled
#set
iARSR
((AUTOWAIT_IO<<6)|((AUTOWAIT_HI&3)<<4)|(AUTOWAIT_LO&3))
#set
MODEBYTE
( ((BUSMODE&3)<<6) | ((~BUS_SIGNAL)&8) )
)
Please refer to the ‚start.asm‘- file where more remarks are given !
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Chapter 3 Using the external bus interface – The Software
BUS_SIGNAL defines the value that will be written to register ECSR (sometimes also called
EPCR). Contradictory to the MODEBYTE this value can be changed also at all time in the
application program.
The MODEBYTE is part of the Reset-Vector and will only be read once. When at least one
external bus area will use 16Bit transfer, then bit 3 (S0) of the MODEBYTE should be set to
indicate 16Bit-datatransfer. As mentioned before the actual bus-width will be controlled by
ECSR (BUS_SIGNAL).
Please refer always to chapter “Memory Access Modes” of the Hardware-Manual.
ADDR_PINS allows defining which of the higher address-lines shall participate the businterface. In case that the corresponding bit is set to ‘0’ the address-line is active, otherwise,
in case of ‘1’, the pin can be used as simple I/O-pin.
Note:
Some 16LX microcontroller might share some pins of the external bus-interface with
peripheral resources other than simple I/O. In this case the resource output pins shared on
the external bus cannot be used even if the corresponding pin is configured to be a outputport pin not participating the external bus. This concerns only to the output of resources
shared with the external bus-interface. The input of resources shared with the external businterface will operate, if the corresponding pin is configured to be an input-port pin.
See also Appendix D for detailed information.
For the following examples the total 16MB-address-space (A23…16 = ‘00000000) will be
used with 16Bit Bus-width (MODEBYTE, S0 = 1).
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External Businterface
Chapter 3 Using the external bus interface – The Software
3.2 8-Bit Memory-Access
The five following examples will show an 8-Bit Memory-Write.
The value 0x81 will be written to Memory-Adress 0x10000 respective 0x10001.
Of course all examples will work the other way round for read-operation !
In case of Memory-Address is
Even: /WRH = 1
/WRL = 0
ALE = 0x10000
AD07..AD00 = 0x81
Odd : /WRH = 0
/WRL = 1
ALE = 0x10001
AD15..AD08 = 0x81
Please see Appendix C for timing charts.
Method 1:
__far unsigned char *ptr_char = (__far unsigned char*)0x10000;
*ptr_char = 0x81;
Assembler-result:
719F0A01
71A0
4281
6F3000
MOVL
MOVL
MOV
MOV
A,010A
RL0,A
A,#81
@RL0+00,A
Method 2:
CTRL_BASE = 0x10000;
*(volatile unsigned char __far*)(CTRL_BASE + 0x00L) = 0x81;
Assembler-result:
4B00000100
71A0
4281
6F3000
MOVL
MOVL
MOV
MOV
A,#00010000
RL0,A
A,#81
@RL0+00,A
Method 3:
unsigned long adress_var;
adress_var = 0x10000;
*(volatile unsigned char __far*)adress_var = 0x81;
Assembler-result:
719F0A01
71A0
4281
6F3000
MOVL
MOVL
MOV
MOV
A,010A
RL0,A
A,#81
@RL0+00,A
Method 4: (see appendix A) and Method 5:
__far volatile extern char ext_var_char;
method.reg.reg0 = 0x81;
Assembler-result:
4B00000100
71A0
4281
6F3000
MOVL
MOVL
MOV
MOV
//
variable
located
// in other c-module
// e.g. method4.c
// (see appendix A and B)
A,#00010000
RL0,A
A,#81
@RL0+00,A
© Fujitsu Microelectronics Europe GmbH
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External Businterface
Chapter 3 Using the external bus interface – The Software
3.3 16-Bit Memory-Access
The five following examples will show a 16-Bit Memory-Write.
The value 0x8421 will be written to Memory-Adress 0x10000 respective 0x10001.
Of course all examples will work the other way round for read-operation !
In case of Memory-Adress is
Even (e.g. 0x10000) :
/WRH = 0
/WRL = 0
ALE = 0x10001 AD15..AD00 = 0x8421;
Odd (e.g. 0x10001) :
two memory-accesses will be done:
/WRH = 0
/WRL = 1
ALE = 0x10001 AD15..AD00 = 0x2184;
/WRH = 1
/WRL = 0
ALE = 0x10002 AD15..AD00 = 0x2184;
Method 1:
__far unsigned int *ptr_int = (__far unsigned int*)0x10000;
*ptr_int = 0x8421;
Assembler-result:
719F0601
MOVL
71A0
MOVL
4A2184
MOVW
6F3800
MOVW
A,0106
RL0,A
A,#8421
@RL0+00,A
Method 2:
CTRL_BASE = 0x10000;
*(volatile unsigned int __far*)(CTRL_BASE + 0x00L) = 0x8421;
Assembler-result:
4B01000100
MOVL
71A0
MOVL
4A2184
MOVW
6F3800
MOVW
A,#00010001
RL0,A
A,#8421
@RL0+00,A
Method 3:
unsigned long adress_var;
adress_var = 0x10000;
*(volatile unsigned int __far*)adress_var = 0x8421;
Assembler-result:
4B01000100
MOVL
71BF0201
MOVL
719F0201
MOVL
71A0
MOVL
4A2184
MOVW
6F3800
MOVW
A,#00010001
0102,A
A,0102
RL0,A
A,#8421
@RL0+00,A
Method 4: (see appendix A) and Method 5 (see appendix B)
__far volatile extern int ext_var_int;
ext_var_int = 0x81;
Assembler-result:
4201
MOV
6F11
MOV
06
ADB
73DF00002184
MOVW
MCU-AN-390034-E-V19
//
variable
located
// in other c-module
// e.g. ext_bus_var.c
// (see appendix A and B)
A,#01
ADB,A
0000,#8421
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© Fujitsu Microelectronics Europe GmbH
External Businterface
Chapter 3 Using the external bus interface – The Software
3.4 Bus-Access-Modes and Bus-Control-Signals: 8 Bit mode
Reflection of which Bus-Control-Signal is active while 8-Bit Bus-access:
8-Bit Mode: byte-access to even address
Write: (volatile unsigned char __far) even_address = 0xFF;
Read: char_var = (volatile unsigned char __far) even_address;
Buscontroll (write):
Buscontroll (read):
ALE(even address), WRL(D0..D7=0xFF)
ALE(even address), RD(D0..D7)
8-Bit Mode: byte-access to odd address
Write: (volatile unsigned char __far) odd_address = 0xFF;
Read: char_var = (volatile unsigned char __far) odd_address;
Buscontroll (write):
Buscontroll (read):
ALE(odd address), WRL(D0..D7=0xFF)
ALE(odd address), RD(D0..D7)
8-Bit Mode: word-access to even address
Write: (volatile unsigned int __far) even_address = 0x8421;
Read: int_var = (volatile unsigned int __far) even_address;
Buscontroll (write):
1. ALE(even address), WRL(D0..D7=0x21)
2. ALE(even address+1), WRL(D0..D7=0x84)
Buscontroll (read):
1. ALE(even address),RD(D0..D7)
2. ALE(even address+1), RD(D0..D7)
8-Bit Mode: word-access to odd address
Write: (volatile unsigned int __far) odd_address = 0x8421;
Read: int_var = (volatile unsigned int __far) odd_address;
Buscontroll (write):
1. ALE(odd address), WRL(D0..D7=0x21)
2. ALE(odd address+1), WRL(D0..D7=0x84)
Buscontroll (read):
1. ALE(odd address),RD(D0..D7)
2. ALE(odd address+1), RD(D0..D7)
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-390034-E-V19
External Businterface
Chapter 3 Using the external bus interface – The Software
3.5 Bus-Access-Modes and Bus-Control-Signals: 16 Bit mode
Reflection of which Bus-Control-Signal is active while 16-Bit Bus-access:
16-Bit Mode: byte-access to even address
Write: (volatile unsigned char __far) even_address = 0xFF;
Read: char_var = (volatile unsigned char __far) even_address
Buscontroll (write):
Buscontroll (read):
ALE(even address), WRL(D0..D7=0xFF)
ALE(even address), RD(D0..D7)
16-Bit Mode: byte-access to odd address
Write: (volatile unsigned char __far) odd_address = 0xFF;
Read: char_var = (volatile unsigned char __far) odd_address
Buscontroll (write):
Buscontroll (read):
ALE(odd address), WRH(D8..D15=0xFF)
ALE(odd address), RD(D8..D15)
16-Bit Mode: word-access to even address
Write: (volatile unsigned int __far) even_address = 0x8421;
Read: int_var = (volatile unsigned int __far) even_address;
Buscontroll (write):
Buscontroll (read):
ALE(even address), WRL(D0..D7=0x21), WRH(D8..D15=0x84)
ALE(even address),RD(D0..D15)
16-Bit Mode: word-access to odd address
Write: (volatile unsigned int __far) odd_address = 0x8421;
Read: int_var = (volatile unsigned int __far) odd_address;
Buscontroll (write):
1. ALE(odd address), WRH(D8..D15=0x21)
2. ALE(odd address+1), WRL(D0..D7=0x84)
Buscontroll (read):
1. ALE(odd address),RD(D8..D15)
2. ALE(odd address+1), RD(D0..D7)
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External Businterface
Appendix A: Method 4
Appendix A: Method 4
When using method 4 some hints have to be known to define the external variables.
Possibly, those variables will be registers of an external device. Therefore, they have to be
located at a fixed address.
For example: method4.c
// Definition of external Memory-Addresses,
// e.g. to define some registers of an external device
// starting at adress 0x10000
#pragma section FAR_DATA=Ext_Bus_data,attr=DATA,locate=0x10000
__far volatile union
{
unsigned int word0;
struct
{
char reg0;
char reg1;
}reg;
}method4;
__far
__far
__far
__far
volatile
volatile
volatile
volatile
unsigned
unsigned
unsigned
unsigned
// Address-offset +0 => e.g. 0x10000
// Address-offset +0 => e.g. 0x10000
// Address-offset +1 => e.g. 0x10001
int
char
char
int
method4_word1;
method4_reg4;
method4_reg5;
method4_word3;
//
//
//
//
Address
Address
Address
Address
0x10002
0x10004
0x10005
0x10006
Hint
Generally the Compiler will make an
optimisation with a reorder of variables of
different sizes.
In order to prevent this reordering an
individual Setup option has to added:
‘- varorder NORMAL’
(right mouse-click at filename within sourcewindow, Setup-Tool-Option)
Caution:
Unfortunately all project-setup-settings will
not be valid anymore for modules with
individual settings like it was done in this
module.
This disadvantage will be covered by defining the external-registers as a struct/unionexpression like shown in Appendix B.
© Fujitsu Microelectronics Europe GmbH
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External Businterface
Appendix B: Method 5
Appendix B: Method 5
Method 5 uses the possibility to define a structure that will not be reordered by the compiler.
For example: method5.h
struct ext_device0_struct
{
union
{
unsigned int word;
struct
{
char reg0;
char reg1;
}reg;
}word0;
// Address-offset +0 => e.g. 0x20000
// Address-offset +0 => e.g. 0x20000
// Address-offset +1 => e.g. 0x20001
union
{
unsigned int word;
struct
{
char reg2;
char reg3;
}reg;
}word1;
unsigned int
unsigned char
unsigned char
};
word3;
reg4;
reg5;
// Address-offset +2 => e.g. 0x20002
// Address-offset +2 => e.g. 0x20002
// Address-offset +3 => e.g. 0x20003
// Address-offset +4 => e.g. 0x20004
// Address-offset +5 => e.g. 0x20005
// Address-offset +6 => e.g. 0x20006
For example: method5.c
// Definition of external Memory-Addresses,
// e.g. to define some registers of an external device
// starting at adress 0x20000
#pragma section FAR_DATA=Ext_Bus_data2,attr=DATA,locate=0x20000
#include "method5.h"
__far volatile struct ext_device0_struct method5;
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External Businterface
Appendix C: Timing-Diagrams
Appendix C: Timing-Diagrams
external 16-Bit Bus Mode: 8-Bit Write-access
Address
Addres
undefined
Addres
8 Bit-data
8-Bit Memory-Write-Access to even address, e.g. 0x10000
Address
Address
8 Bit-data
Address
undefined
8-Bit Memory-Write-Access to odd address, e.g. 0x10001
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-390034-E-V19
External Businterface
Appendix C: Timing-Diagrams
external 16-Bit Bus Mode: 16-Bit Write-access
Address
Address
Address
Data (Highbyte)
Data (Lowbyte)
16-Bit Memory-Write-Access to even address, e.g. 0x10000
Address + 1
Addres
Address
Address
Data (Highbyte)
undefined
Addr + 1
undefined
Addr + 1
Data (Lowbyte)
16-Bit Memory-Write-Access to odd address, e.g. 0x10001
Please refer to the Hardware-Manual chapter „Memory-Access-Modes“
and to the Datasheet for more informations !
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External Businterface
Appendix D: Resource Overview
Appendix D: Resource Overview
Following table shows the resources using same pins as external Bus interface.
Note: Address lines AD00-15 cannot be used at all neither for simple I/O- nor other
peripheral resource functionality, when the bus-Interface is in use. All other Pins (A16-23,
ALE; RDX, WRLX/WRX, WRHX, HRQ, HAKX, RDY; CLK) and be used individually as
simple I/O, when not be used as external Bus interface pin. Take care that some 16LX
microcontroller will not allow using the output of peripheral resources other than simple I/O,
in this case.
The following tables will give an overview about the pin-sharing for some microcontrollers
with external bus-interface:
•
MB90340series, MB90860series
•
MB90350series
•
MB90495series
•
MB90540series, MB90435series, MB90440series
Note:
Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is
selected in “start.asm”.
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MCU-AN-390034-E-V19
External Businterface
Appendix D: Resource Overview
MB90340series, MB90860series:
Pin No.
QFP
LQFP
77
75
78
External
Bus
Interface
Ressource
I/O Port
Resource pin
AD00
P01
INT8
76
AD01
P02
INT9
79
77
AD02
P03
INT10
80
78
AD03
P04
INT11
81
79
AD04
P05
INT12
82
80
AD05
P06
INT13
83
81
AD06
P07
INT14
84
82
AD07
P08
INT15
85
83
AD08
P10
TIN1
86
84
AD09
P11
TOT1 (*)
87
85
AD10
P12
SIN3; INT11R
88
86
AD11
P13
SOT3 (*)
89
87
AD12
P14
SCK3 (*)
94
92
AD13
P15
SIN4
95
93
AD14
P16
SOT4
96
94
AD15
P17
SCK4
97
95
A16
P20
PPG9 (*)
98
96
A17
P21
PPGB (*)
99
97
A18
P22
PPBD (*)
100
98
A19
P23
PPGF (*)
1
99
A20
P24
IN0
2
100
A21
P25
IN1
3
1
A22
P26
IN2
4
2
A23
P27
IN3
5
3
ALE
P30
IN4
6
4
RDX
P31
IN5
7
5
WRLX/WRX
P32
RX2; INT10R
8
6
WRHX
P33
TX2
9
7
HRQ
P34
OUT4 (*)
10
8
HAKX
P35
OUT5 (*)
11
9
RDY
P36
OUT6 (*)
12
10
CLK
P37
OUT7 (*)
Note:
Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is
selected in “start.asm”.
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External Businterface
Appendix D: Resource Overview
MB90350 series:
Pin No.
External
Bus
Interface
QFP (M09)
Ressource
I/O Port
Resource pin
24
AD00
P01
INT8
25
AD01
P02
INT9
26
AD02
P03
INT10
27
AD03
P04
INT11
28
AD04
P05
INT12
29
AD05
P06
INT13
30
AD06
P07
INT14
31
AD07
P08
INT15
32
AD08
P10
TIN1
33
AD09
P11
TOT1 (*)
34
AD10
P12
SIN3; INT11R
35
AD11
P13
SOT3 (*)
36
AD12
P14
SCK3 (*)
37
AD13
P15
--
38
AD14
P16
--
39
AD15
P17
--
40
A16
P20
PPG9 (*)
41
A17
P21
PPGB (*)
42
A18
P22
PPBD (*)
43
A19
P23
PPGF (*)
44
A20
P24
IN0
51
A21
P25
IN1; ADTG
--
A22
P26
--
--
A23
P27
--
54
ALE
P30
IN4
55
RDX
P31
IN5
56
WRLX/WRX
P32
INT10R
57
WRHX
P33
--
58
HRQ
P34
OUT4 (*)
59
HAKX
P35
OUT5 (*)
60
RDY
P36
OUT6 (*)
61
CLK
P37
OUT7 (*)
Note:
Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is
selected in “start.asm”.
© Fujitsu Microelectronics Europe GmbH
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External Businterface
Appendix D: Resource Overview
MB90495 series:
Pin No.
M06
M09
26
25
27
External
Bus
Interface
Ressource
I/O Port
Resource pin
AD00
P01
--
26
AD01
P02
--
28
27
AD02
P03
--
29
28
AD03
P04
--
30
29
AD04
P05
--
31
30
AD05
P06
--
32
31
AD06
P07
--
33
32
AD07
P08
--
34
33
AD08
P10
IN0
35
34
AD09
P11
IN1
36
35
AD10
P12
IN2
37
36
AD11
P13
IN3
38
37
AD12
P14
PPG0 (*)
39
38
AD13
P15
PPG1 (*)
40
39
AD14
P16
PPG2 (*)
41
40
AD15
P17
PPG3 (*)
42
41
A16
P20
TIN0
43
42
A17
P21
TOUT0 (*)
44
43
A18
P22
TIN1
45
44
A19
P23
TOUT1 (*)
46
45
A20
P24
INT4
47
46
A21
P25
INT5
48
47
A22
P26
INT6
49
48
A23
P27
INT7
51
50
ALE
P30
SOT0 (*)
52
51
RDX
P31
SCK0 (*)
53
52
WRLX/WRX
P32
--
54
53
WRHX
P33
--
55
54
HRQ
P34
--
56
55
HAKX
P35
--
59
58
RDY
P36
FRCK
60
59
CLK
P37
ADTG
Note:
Signals marked with an asterisk (*) will not work at all, if BUSMODE INTROM_EXTBUS is
selected in “start.asm”.
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External Businterface
Appendix D: Resource Overview
MB90540/545series, MB90435series, MB90440series:
Pin No.
QFP
LQFP
85
83
86
External
Bus
Interface
Ressource
I/O Port
Resource pin
AD00
P01
--
84
AD01
P02
--
87
85
AD02
P03
--
88
86
AD03
P04
--
89
87
AD04
P05
--
90
88
AD05
P06
--
91
89
AD06
P07
--
92
90
AD07
P08
--
93
91
AD08
P10
--
94
92
AD09
P11
--
95
93
AD10
P12
--
96
94
AD11
P13
--
97
95
AD12
P14
--
98
96
AD13
P15
--
99
97
AD14
P16
--
100
98
AD15
P17
--
1
99
A16
P20
--
2
100
A17
P21
--
3
1
A18
P22
--
4
2
A19
P23
--
5
3
A20
P24
--
6
4
A21
P25
--
7
5
A22
P26
--
8
6
A23
P27
--
9
7
ALE
P30
--
10
8
RD
P31
--
11
9
WRL/WR
P32
--
12
10
WRH
P33
--
94
92
HRQ
P34
--
95
93
HAK
P35
--
96
94
RDY
P36
--
97
95
CLK
P37
--
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