WD R NE08 O ® F 1 D N D E , E L5 MME EL5106 O C RE SE E NOT Data Sheet ESIG Single 200MHz Fixed Gain Amplifier with Enable The EL5197 and EL5197A are fixed gain amplifiers with a bandwidth of 200MHz, making these amplifiers ideal for today’s high speed video and monitor applications. These amplifiers feature internal gain setting resistors and can be configured in a gain of +1, -1 or +2. The same bandwidth is seen in both gain-of-1 and gain-of-2 applications. With a supply current of just 4mA and the ability to run from a single supply voltage from 5V to 10V, these amplifiers are also ideal for hand held, portable or battery powered equipment. The EL5197A also incorporates an enable and disable function to reduce the supply current to 100µA typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. The EL5197 is offered in the 5 Ld SOT-23 package and the EL5197A is available in the 6 Ld SOT-23 as well as the industry-standard 8 Ld SOIC packages. Both operate over the industrial temperature range of -40°C to +85°C. NS EL5197, EL5197A May 16, 2007 FN7184.2 Features • Gain selectable (+1, -1, +2) • 200MHz -3dB BW (AV = 1, 2) • 4mA supply current • Fast enable/disable (EL5197A only) • Single and dual supply operation, from 5V to 10V or ±2.5V to ±5V • Available in SOT-23 packages • Triple (EL5397) available • 400MHz, 9mA products available (EL5197 and EL5396) • Pb-Free plus anneal available (RoHS compliant) Applications • Battery powered equipment • Hand held, portable devices • Video amplifiers • Cable drivers • RGB amplifiers • Test equipment • Instrumentation • Current to voltage converters Pinouts EL5197A (8 LD SOIC) TOP VIEW NC 1 IN- 2 8 CE + 7 VS+ IN+ 3 6 OUT VS- 4 5 NC EL5197A (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 IN+ 3 + - EL5197 (5 LD SOT-23) TOP VIEW 6 VS+ OUT 1 5 CE VS- 2 4 IN- IN+ 3 5 VS+ + 4 IN- . 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5197, EL5197A Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5197CW-T7 S 7” (3k pcs) 5 Ld SOT-23 MDP0038 EL5197CW-T7A S 7” (250 pcs) 5 Ld SOT-23 MDP0038 EL5197ACW-T7 S 7” 6 Ld SOT-23 MDP0038 EL5197ACS 5197ACS - 8 Ld SOIC (150 mil) MDP0027 EL5197ACS-T7 5197ACS 7” 8 Ld SOIC (150 mil) MDP0027 EL5197ACS-T13 5197ACS 13” 8 Ld SOIC (150 mil) MDP0027 EL5197ACSZ (Note) 5197ACS Z - 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5197ACSZ-T7 (Note) 5197ACS Z 7” 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5197ACSZ-T13 (Note) 5197ACS Z 13” 8 Ld SOIC (150 mil) (Pb-free) MDP0027 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7184.2 May 16, 2007 EL5197, EL5197A Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . 11V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = +1 200 MHz AV = -1 200 MHz AV = +2 200 MHz 20 MHz 2200 V/µs 12 ns BW1 0.1dB Bandwidth SR Slew Rate VO = -2.5V to +2.5V, AV = +2 tS 0.1% Settling Time VOUT = -2.5V to +2.5V, AV = -1 eN Input Voltage Noise 4.4 nV/√Hz iN- IN- Input Current Noise 17 pA/√Hz iN+ IN+ Input Current Noise 50 pA/√Hz dG Differential Gain Error (Note 1) AV = +2 0.03 % dP Differential Phase Error (Note 1) AV = +2 0.04 ° 1800 DC PERFORMANCE VOS Offset Voltage TCVOS Input Offset Voltage Temperature Coefficient Measured from TMIN to TMAX AE Gain Error VO = -3V to +3V RF, RG Internal RF and RG -10 1 10 5 mV µV/°C -2 1.3 2 % 320 400 480 Ω INPUT CHARACTERISTICS CMIR Common Mode Input Range ±3V ±3.3V +IIN + Input Current -60 1 60 µA -IIN - Input Current -30 1 30 µA RIN Input Resistance CIN Input Capacitance at IN+ V 45 kΩ 0.5 pF OUTPUT CHARACTERISTICS VO RL = 150Ω to GND ±3.4V ±3.7V V RL = 1kΩ to GND ±3.8V ±4.0V V Output Current RL = 10Ω to GND 95 120 mA ISON Supply Current - Enabled No load, VIN = 0V 3 4 5 mA ISOFF Supply Current - Disabled No load, VIN = 0V 100 150 µA IOUT Output Voltage Swing SUPPLY 3 FN7184.2 May 16, 2007 EL5197, EL5197A Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP 75 PSRR Power Supply Rejection Ratio DC, VS = ±4.75V to ±5.25V 55 -IPSR - Input Current Power Supply Rejection DC, VS = ±4.75V to ±5.25V -2 MAX UNIT dB 2 µA/V ENABLE (EL5197A ONLY) tEN Enable Time 40 ns tDIS Disable Time (Note 2) 600 ns IIHCE CE Pin Input High Current CE = VS+ 0.8 6 µA IILCE CE Pin Input Low Current CE = VS- 0 -0.1 µA VIHCE CE Input High Voltage for Disable VILCE CE Input Low Voltage for Enable VS+ -1 V VS+ -3 V NOTES: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz 2. Measured from the application of CE logic until the output voltage is at the 50% point between initial and final values 4 FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves Frequency Response (Gain) Frequency Response (Phase), All Gains 90 AV = -1 AV = 2 0 2 -2 Phase (°) AV = 1 -6 -90 -180 -270 -10 -14 1M RL = 150Ω 10M 100M -360 1M 1G RL = 150Ω 10M Frequency (Hz) Frequency Response for Various CL Group Delay vs Frequency AV = 2 RL = 150Ω 10 AV = 2 3 22pF added 2.5 6 10pF added 2 2 1.5 AV = 1 1 0pF added -2 0.5 -6 1M 10M 100M 0 1M 1G RL = 150Ω 10M Frequency (Hz) 6 Frequency Response for Various Common-Mode Input Voltages 3V 1G Transimpedance (ROL) vs Frequency 10M 0 Phase -3V 1M 2 0V -2 -6 -10 -14 1M 100M Frequency (Hz) Magnitude (Ω) Normalized Magnitude (dB) 1G 3.5 Delay (ns) Normalized Magnitude (dB) 14 100M Frequency (Hz) -90 100k -180 10k Phase (°) Normalized Magnitude (dB) 6 -270 ROL 1k AV = 2 RL = 150Ω -360 10M 100M Frequency (Hz) 5 1G 100 1k 10k 100k 1M 10M Frequency (Hz) 100M 1G FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves (Continued) PSRR and CMRR vs Frequency -3dB Bandwidth vs Supply Voltage 20 250 PSRR/CMRR (dB) 0 -20 -3dB Bandwidth (MHz) PSRR+ PSRR- -40 CMRR -60 -80 10k 100k 1M 10M 100M 200 AV = 2 150 100 1G RL = 150Ω AV = 1 AV = -1 5 6 Peaking vs Supply Voltage -3dB Bandwidth vs Temperature 250 AV = -1 -3dB Bandwidth (MHz) Peaking (dB) 10 300 4 AV = 1 3 AV = 2 2 1 200 150 100 50 RL = 150Ω 5 6 7 8 9 0 -40 10 RL = 150Ω 10 Total Supply Voltage (V) Peaking vs Temperature 110 160 Voltage and Current Noise vs Frequency 1k Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 0.8 0.6 0.4 0.2 0 -40 60 Ambient Temperature (°C) 1 Peaking (dB) 9 Total Supply Voltage (V) 5 0 8 7 Frequency (Hz) RL = 150Ω 10 60 110 Ambient Temperature (°C) 6 160 100 iN+ iN- 10 1 100 eN 1k 10k 100k Frequency (Hz) 1M 10M FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves (Continued) Supply Current vs Supply Voltage 10 10 8 Supply Current (mA) Output Impedance (Ω) Closed Loop Output Impedance vs Frequency 100 1 0.1 0.01 0.001 100 6 4 2 0 10k 1k 1M 10M 100k Frequency (Hz) 100M 1G 0 2nd and 3rd Harmonic Distortion vs Frequency 25 AV = +2 VOUT = 2VP-P RL = 100Ω -30 Input Power Intercept (dBm) Harmonic Distortion (dBc) -20 -40 2nd Order Distortion -50 -60 3rd Order Distortion -70 -80 -90 1 0.03 10 Frequency (MHz) AV = 2 RL = 150Ω dP 15 10 5 0 -5 AV = +2 RL = 100Ω 100 Differential Gain/Phase vs DC Input Voltage at 3.58MHz 0.03 AV = 1 RL = 500Ω dP 0.02 0 dG (%) or dP (°) dG (%) or dP (°) 12 AV = +2 RL = 150Ω 20 0.04 0.01 dG -0.01 -0.02 0.01 -0.01 -0.02 -0.04 -0.03 -0.5 0 DC Input Voltage (V) 7 0.5 1 dG 0 -0.03 -0.05 -1 10 Frequency (MHz) Differential Gain/Phase vs DC Input Voltage at 3.58MHz 0.02 4 6 8 Supply Voltage (V) Two-Tone 3rd Order Input Referred Intermodulation Intercept (IIP3) -10 10 100 2 -0.04 -1 -0.5 0 0.5 1 DC Input Voltage (V) FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves Output Voltage Swing vs Frequency THD < 1% 10 RL = 500Ω Output Voltage Swing (VPP) Output Voltage Swing (VPP) 10 (Continued) 8 RL = 150Ω 6 4 2 0 8 RL = 500Ω 6 RL = 150Ω 4 2 AV = 2 1 10 Frequency (MHz) Output Voltage Swing vs Frequency THD < 0.1% 0 100 Small Signal Step Response AV = 2 1 10 Frequency (MHz) 100 Large Signal Step Response VS = ±5V RL = 150Ω AV = 2 VS = ±5V RL = 150Ω AV = 2 200mV/div 1V/div 10ns/div 10ns/div Settling Time vs Settling Accuracy Transimpedance (RoI) vs Temperature 25 625 AV = 2 RL = 150Ω VSTEP = 5VP-P output 600 15 RoI (kΩ) Settling Time (ns) 20 10 575 550 5 0 0.01 0.1 Settling Accuracy (%) 8 1 525 -40 10 60 110 160 Die Temperature (°C) FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves Frequency Response (Gain) SO8 Package 90 AV = -1 2 AV = 2 AV = 1 -2 Frequency Response (Phase) SO8 Package 0 Phase (°) Normalized Magnitude (dB) 6 (Continued) -6 -10 -90 -180 -270 -14 1M RL = 150Ω 10M 100M -360 1M 1G RL = 150Ω 10M Frequency (Hz) 100M 1G Frequency (Hz) PSRR and CMRR vs Temperature ICMR and IPSR vs Temperature 90 2 80 1.5 PSRR ICMR/IPSR (µA/V) PSRR/CMRR (dB) 70 60 50 CMRR 40 30 ICMR+ 1 IPSR 0.5 ICMR- 0 20 10 -40 10 60 110 -0.5 -40 160 10 Die Temperature (°C) 60 110 160 Die Temperature (°C) Offset Voltage vs Temperature Input Current vs Temperature 2 60 40 Input Current (µA) VOS (mV) 1 0 -1 20 IB0 IB+ -20 -40 -2 -40 10 60 Die Temperature (°C) 9 110 160 -60 -40 10 60 110 160 Die Temperature (°C) FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves (Continued) Supply Current vs Temperature Positive Input Resistance vs Temperature 5 60 50 Supply Current (mA) 4 RIN+ (kΩ) 40 30 20 10 0 -40 60 10 110 3 2 1 0 -40 160 10 4.2 Positive Output Swing vs Temperature for Various Loads -3.5 4.1 110 160 Negative Output Swing vs Temperature for Various Loads 150Ω -3.6 1kΩ 4 -3.7 3.9 VOUT (V) VOUT (V) 60 Die Temperature (°C) Die Temperature (°C) 3.8 3.7 150Ω -3.8 -3.9 -4 3.6 1kΩ -4.1 3.5 -40 10 60 110 -4.2 -40 160 10 Die Temperature (°C) 60 110 160 Die Temperature (°C) Output Current vs Temperature Slew Rate vs Temperature 130 4000 Slew Rate (V/µS) Sink IOUT (mA) 125 120 115 -40 Source 10 60 Die Temperature (°C) 10 110 160 3500 3000 2500 -40 AV = 2 RL = 150Ω 10 60 110 160 Die Temperature (°C) FN7184.2 May 16, 2007 EL5197, EL5197A Typical Performance Curves (Continued) Enable Response Disable Response 500mV/div 500mV/div 5V/div 5V/div 20ns/div 625mW /W °C 60 =1 0.5 0.4 391mW SO T -23 JA = 25 6° C/ W θ 0.3 0.2 0.1 0 -50-40 -25 0.8 Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 909mW 8 /W SO 0°C 1 =1 θ JA A 8 θJ Power Dissipation (W) 1 0.9 SO 0.6 Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board Power Dissipation (W) 0.7 400ns/div 0.7 0.6 0.5 0.4 435mW 0.3 θJ SO T-2 A =2 0.2 30 3 °C / W 0.1 0 25 50 75 85 100 Ambient Temperature (°C) 11 125 0 -50-40 -25 0 25 50 75 85 100 125 Ambient Temperature (°C) FN7184.2 May 16, 2007 EL5197, EL5197A Pin Descriptions 8 Ld SOIC 5 Ld SOT-23 6 Ld SOT-23 1, 5 2 4 4 PIN NAME FUNCTION NC Not connected IN- Inverting input EQUIVALENT CIRCUIT RG IN+ IN- RF Circuit 1 3 3 3 IN+ Non-inverting input 4 2 2 VS- Negative supply 6 1 1 OUT Output (See circuit 1) OUT RF Circuit 2 7 5 8 6 VS+ Positive supply 5 CE Chip enable VS+ CE VSCircuit 3 12 FN7184.2 May 16, 2007 EL5197, EL5197A Applications Information Product Description The EL5197 is a fixed gain amplifier that offers a wide -3dB bandwidth of 200MHz and a low supply current of 4mA. The EL5197 works with supply voltages ranging from a single 5V to 10V and they are also capable of swinging to within 1V of either supply on the output. This combination of high bandwidth and low power, together with aggressive pricing make the EL5197 the ideal choice for many low-power/highbandwidth applications such as portable, handheld, or battery-powered equipment. For varying bandwidth and higher gains, consider the EL5191 with 1GHz on a 9mA supply current or the EL5193 with 300MHz on a 4mA supply current. Versions include single, dual, and triple amp packages with 5 Ld SOT-23, 16 Ld QSOP, and 8 Ld or 16 Ld SOIC outlines. temperature and process, external resistor should not be used to adjust the gain settings. 400 400 - IN- + IN+ FIGURE 1. AV = +2 400 400 IN- IN+ + FIGURE 2. AV = -1 Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a 4.7µF tantalum capacitor in parallel with a 0.01µF capacitor has been shown to work well when placed at each supply pin. Disable/Power-Down The EL5197A amplifier can be disabled placing its output in a high impedance state. When disabled, the amplifier supply current is reduced to < 150µA. The EL5197A is disabled when its CE pin is pulled up to within 1V of the positive supply. Similarly, the amplifier is enabled by floating or pulling its CE pin to at least 3V below the positive supply. For ±5V supply, this means that an EL5197A amplifier will be enabled when CE is 2V or less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allows the EL5197A to be enabled by tying CE to ground, even in 5V single supply applications. The CE pin can be driven from CMOS outputs. Gain Setting The EL5197A is built with internal feedback and gain resistors. The internal feedback resistors have equal value; as a result, the amplifier can be configured into gain of +1, -1, and +2 without any external resistors. Figure 1 shows the amplifier in gain of +2 configuration. The gain error is ±2% maximum. Figure 2 shows the amplifier in gain of -1 configuration. For gain of +1, IN+ and IN- should be connected together as shown in Figure 3. This configuration avoids the effects of any parasitic capacitance on the IN- pin. Since the internal feedback and gain resistors change with 13 400 IN- 400 + IN+ FIGURE 3. AV = +1 Supply Voltage Range and Single-Supply Operation The EL5197 has been designed to operate with supply voltages having a span of greater than or equal to 5V and less than 11V. In practical terms, this means that the EL5197 will operate on dual supplies ranging from ±2.5V to ±5V. With single-supply, the EL5197 will operate from 5V to 10V. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5197 has an input range which extends to within 2V of either supply. So, for example, on ±5V supplies, the EL5197 has an input range which spans ±3V. The output range of the EL5197 is also quite large, extending to within 1V of the supply rail. On a ±5V supply, the output is therefore capable of swinging from -4V to +4V. Single-supply output range is larger because of the increased negative swing due to the FN7184.2 May 16, 2007 EL5197, EL5197A external pull-down resistor to ground. Figure 4 shows an ACcoupled, gain of +2, +5V single supply circuit configuration. 400 +5 Current Limiting The EL5197 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation 400 +5 0.1µF + VOUT 1k 0.1µF VIN 1k With the high output drive capability of the EL5197, it is possible to exceed the 125°C Absolute Maximum junction temperature under certain very high load current conditions. Generally speaking when RL falls below about 25Ω, it is important to calculate the maximum junction temperature (TJMAX) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the EL5197 to remain in the safe operating area. These parameters are calculated as follows: T JMAX = T MAX + ( θ JA × n × PD MAX ) FIGURE 4. where: Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω, because of the change in output current with DC level. Previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variations in output impedance.) These currents were typically comparable to the entire 4mA supply current of each EL5197 amplifier. Special circuitry has been incorporated in the EL5197 to reduce the variation of output impedance with current output. This results in dG and dP specifications of 0.03% and 0.04°, while driving 150Ω at a gain of 2. TMAX = Maximum ambient temperature θJA = Thermal resistance of the package n = Number of amplifiers in the package PDMAX = Maximum power dissipation of each amplifier in the package PDMAX for each amplifier can be calculated as follows: V OUTMAX PD MAX = ( 2 × V S × I SMAX ) + ( V S - V OUTMAX ) × ---------------------------R L where: VS = Supply voltage Video performance has also been measured with a 500Ω load at a gain of +1. Under these conditions, the EL5197 has dG and dP specifications of 0.03% and 0.04°, respectively. ISMAX = Maximum supply current of 1A Output Drive Capability VOUTMAX = Maximum output voltage (required) In spite of its low 4mA of supply current, the EL5197 is capable of providing a minimum of ±95mA of output current with a minimum of ±95mA of output drive. RL = Load resistance Driving Cables and Capacitive Loads When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, the back-termination series resistor will decouple the EL5197 from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. In these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output to eliminate most peaking. 14 FN7184.2 May 16, 2007 EL5197, EL5197A Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 15 FN7184.2 May 16, 2007 EL5197, EL5197A SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 0.25 0° +3° -0° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7184.2 May 16, 2007