HT9B92G RAM Mapping 40×4 LCD Driver Feature Applications • Logic Operating Voltage:2.4V ~ 5.5V • Leisure products • Integrated oscillator circuitry • Games • Bias: 1/2 or 1/3; Duty:1/4 • Telephone display. • Internal LCD bias generation with voltage-follower buffers • Audio Combo display • External VLCD pin to supply LCD operating voltage • Kitchen Appliance display • Video Player display • Measurement equipment display • Support I2C-bus serial interface • Household appliance • Selectable LCD Frame Frequencies • Consumer electronics • Up to 40x4 bits RAM for display data storage • Maximum Display patterns: 40x4 patterns - 40 segments and 4 commons General Description The device is a memory mapping and multi-function LCD controller driver. The maximum display segments of the device are 160 patterns (40 segments and 4commons) display. The software configuration feature of the HT9B92G device makes it suitable for multiple LCD applications including LCD modules and display subsystems. The device communicates with most microprocessors / microcontrollers via a two-wire bidirectional I2C-bus interface. • Versatile blinking modes: off, 0.5Hz, 1Hz, 2Hz • Write address auto-increment • Support Power Save Mode for low power consumption • Manufactured in silicon gate CMOS process • Package Type: COG and chip Rev. 1.00 1 April 18, 2014 HT9B92G Block Diagram TEST2 Power_on reset VSS SEG0 SDA SCL 8 Display RAM I2C Controller Segment driver output OSCIN Internal Oscillator Timing generator SEG39 VDD COM0 - OP1 + LCD Voltage Selector Column driver output COM3 - OP0 + VLCD LCD bias generator TEST1 Rev. 1.00 2 April 18, 2014 HT9B92G Pad Assignment 1 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 2 Y 29 3 4 28 X 5 27 6 26 7 25 8 9 24 10 ALIGN_A 11 13 14 15 16 17 18 19 ALIGN_B 20 12 21 23 22 Pad Dimensions Item Size Number. X Unit Y Chip size — Chip thickness — 508 μm 1~9, 30~66 60 μm 24~29 80 μm 11~22 85 Pad pitch 2402 Output pad Bump size Input pad Dummy pad Bump height 1100 μm μm 2~9 67 47 μm 31~66 47 67 μm μm 13~20 74 74 11, 12, 21, 22 74 74 μm 1, 24~30 47 67 μm All pad 18±3 μm Alignment mark Dimensions Item Number Size Unit (X, Y) 10mm 10mm ALIGN_A 10 20mm 40mm μm 10mm 10mm 20mm 40mm (X, Y) 10mm 10mm ALIGN_B 23 Rev. 1.00 3 40mm 10mm 10mm 20mm 20mm 20mm μm 20mm April 18, 2014 HT9B92G Pad Coordinates Unit: μm No Name X Y No Name X Y 1 DUMMY 2 SEG36 -1117 455.5 34 SEG3 870.05 455.5 -1106.5 155.66 35 SEG4 810.05 455.5 3 SEG37 -1106.5 95.66 36 SEG5 750.05 455.5 4 SEG38 -1106.5 5 SEG39 -1106.5 35.66 37 SEG6 690.05 455.5 -24.34 38 SEG7 630.05 455.5 6 COM0 -1106.5 7 COM1 -1106.5 -84.34 39 SEG8 570.05 455.5 -144.34 40 SEG9 510.05 455.5 8 COM2 -1106.5 9 COM3 -1106.5 -204.34 41 SEG10 450.05 455.5 -264.34 42 SEG11 390.05 455.5 10 ALIGN_A 11 DUMMY -1124 -340 43 SEG12 330.05 455.5 -1104 -452 44 SEG13 270.05 455.5 12 13 DUMMY -966.45 -452 45 SEG14 210.05 455.5 VLCD -406.8 -452 46 SEG15 150.05 455.5 14 VDD -319.8 -452 47 SEG16 90.05 455.5 15 VSS -234.8 -452 48 SEG17 30.05 455.5 16 TEST1 -12.8 -446.4 49 SEG18 -29.95 455.5 17 OSCIN 72.2 -446.4 50 SEG19 -89.95 455.5 18 SCL 160.9 -446.4 51 SEG20 -149.95 455.5 19 SDA 245.9 -446.4 52 SEG21 -209.95 455.5 20 TEST2 334.6 -446.4 53 SEG22 -269.95 455.5 21 DUMMY 910 -452 54 SEG23 -329.95 455.5 22 DUMMY 1104 -452 55 SEG24 -389.95 455.5 23 ALIGN_B 1104 -340 56 SEG25 -449.95 455.5 24 DUMMY 1117 -278.292 57 SEG26 -509.95 455.5 25 DUMMY 1117 -198.292 58 SEG27 -569.95 455.5 26 DUMMY 1117 -118.292 59 SEG28 -629.95 455.5 27 DUMMY 1117 -38.292 60 SEG29 -689.95 455.5 28 DUMMY 1117 41.708 61 SEG30 -749.95 455.5 29 DUMMY 1117 121.708 62 SEG31 -809.95 455.5 30 DUMMY 1117 455.5 63 SEG32 -869.95 455.5 31 SEG0 1050.05 455.5 64 SEG33 -929.95 455.5 32 SEG1 990.05 455.5 65 SEG34 -989.95 455.5 33 SEG2 930.05 455.5 66 SEG35 -1049.95 455.5 Rev. 1.00 4 April 18, 2014 HT9B92G Pad Description Pin Name Type Description SDA I/O Serial Data Input/Output pin Serial Data (SDA) Input/Output for 2-wire I2C interface is an NMOS open drain structure. SCL I Serial Clock Input pin Serial Data (SCL) is a clock input for 2-wire I2C interface. OSCIN I External Clock Input pin The external and internal clock mode can be selected by the command. When the internal oscillator circuitry is used, this pin must be connected to VSS. TEST1 I Test mode input pin When this pin is connected to VDD, the device will enter the test mode. TEST2 I Power on reset control pin The internal power on reset circuitry will be enabled if this pin is connected to VSS. If this pin is connected to VDD, the internal power on reset circuitry will be disabled and the reset function will be performed by executing the software reset command. COM0~COM3 O LCD Common outputs. SEG0~SEG39 O LCD Segment outputs. VDD — Positive power supply. VSS — Negative power supply, ground. VLCD — LCD power supply pin Approximate Internal Connections SCL, SDA (for Schmitt trigger type) COM0~COM3; SEG0~SEG39 OSCIN VDD VDD VLCD VSS VLCD VSS VSS VSS TEST1, TEST2 VDD VSS Rev. 1.00 5 April 18, 2014 HT9B92G Absolute Maximum Ratings SupplyVoltage .......................... VSS-0.3V to VDD+6.5V Storage Temperature ........................... -55°C to 150°C Input Voltage ............................ VSS-0.3V to VDD+0.3V Operating Temperature.......................... -40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics VSS = 0V; VDD =2.4V to 5.5V; Ta = -40 to +85°C Symbol Parameter Test Condition VDD Condition Min. Typ. Max. Unit VDD Operating Voltage — — 2.4 — 5.5 V VLCD LCD Operating Voltage — — 0 — VDD-2.4 V VIH Input High Voltage — SCL, SDA, TEST1, TEST2 0.7VDD — VDD V VIL Input Low Voltage — SCL, SDA, TEST1, TEST2 0 — 0.3VDD V IIL Input Leakage Current — VIN = VSS or VDD −1 — 1 mA 6 — — mA 9 — — mA — 7.5 15 mA — 12 20 mA — — 1 mA — — 2 mA 2 4 6.5 1.5 3 4.5 250 400 — IOL Low Level Output Current 3.3V 5.0V VOL=0.4V for SDA pin No load, 1/3bias, B type inversion, Ta=25°C, LCD display on, fLCD=80Hz, VLCD pin is connected to VSS, Power save mode = Low 5.0V Current2 mode 3.3V IDD Operating Current No load, 1/3bias, B type inversion, Ta = 25°C, LCD display off, fLCD=80Hz, VLCD pin is connected to VSS, Power save mode = Low 5.0V Current2 mode 3.3V ISTB1 Standby Current RPL Pull-Low Resistance IOL1 LCD Common Sink Current IOH1 LCD Common Source Current 3.3V 5.0V — — IOL2 LCD Segment Sink Current — IOH2 LCD Segment Source Current — Rev. 1.00 For OSCIN pin VDD-VLCD=3.30V, VOL=0.33V kW mA VDD-VLCD=5.00V, VOL=0.50V 500 800 — mA VDD-VLCD=3.30V, VOH=2.97V −140 −230 — mA VDD-VLCD=5.00V, VOH=4.50V −300 −500 — mA VDD-VLCD=3.30V, VOL=0.33V 250 400 — mA VDD-VLCD=5.00V, VOL=0.50V 500 800 — mA VDD-VLCD=3.30V, VOH=2.97V −140 −230 — mA VDD-VLCD=5.00V, VOH=4.50V −300 −500 — mA 6 April 18, 2014 HT9B92G A.C. Characteristics Symbol fLCD1 Ta=-40 to +85°C Test Condition Parameter Min. Typ. Max. Ta=25°C, internal oscillator is used, Display control command: P[4:3]="00" 72.0 80.0 88.0 Ta=25°C, internal oscillator is used, Display control command: P[4:3]="01" 63.9 71.0 78.1 Ta=25°C, internal oscillator is used, Display control command: P[4:3]="10" 57.6 64.0 70.4 Ta=25°C, internal oscillator is used, Display control command: P[4:3]="11" 47.7 53.0 58.3 Condition VDD LCD Frame Frequency 3.3V Hz Ta=-40 to 85°C, internal oscillator is used, 56.0 Display control command: P[4:3]="00" fLCD2 Ta=-40 to 85°C, internal oscillator is used, 49.7 2.4V Display control command: P[4:3]="01" ~ 5.5V Ta=-40 to 85°C, internal oscillator is used, 44.8 Display control command: P[4:3]="10" LCD Frame Frequency Ta=-40 to 85°C, internal oscillator is used, 37.1 Display control command: P[4:3]="11" — Unit 80.0 104.0 71.0 92.3 64.0 83.2 53.0 68.9 Hz tSR VDD Slew Rate — 0.05 — — V/ms tPOF VDD OFF Times — VDD drop down to 0.9V 10 — — ms tRSOFF Wait Time for Data Transfers — 2-wire I C-bus 1 — — ms 2 Note: fLCD=1/tLCD I2C Interface Characteristics Symbol Unless otherwise specified, VSS=0V; VDD=2.4V~5.5V; Ta=-40 to +85°C Parameter Condition Min. Max. Unit — — 400 kHz Time in which the bus must be free before a new transmission can start 1.3 — ms After this period, the first clock pulse is generated 0.6 — ms SCL Low time — 1.3 — ms SCL High time — 0.6 — ms 0.6 — ms 0 — ns 100 — ns Note — 0.3 ms Note — 0.3 ms 0.6 — ms — 0.9 ms — 50 ns fSCL Clock frequency tBUF bus free time tHD: STA Start condition hold time tLOW tHIGH tSU: STA Start condition setup time tHD: DAT Data hold time — tSU: DAT Data setup time — tR SDA and SCL rise time tF SDA and SCL fall time tSU: STO Stop condition set-up time — tAA Output Valid from Clock — tSP Input Filter Time Constant (SDA and SCL Pins) Only relevant for repeated START condition Noise suppression time Note: These parameters are periodically sampled but not 100% tested. Rev. 1.00 7 April 18, 2014 HT9B92G Timing Diagrams I2C Timing SDA tBUF tSU:DAT tf tLOW tHD:STA tr tSP SCL tHD:SDA S tHD:DAT tHIGH tSU:STA tAA tSU:STO P Sr S SDA OUT Power On Reset Timing tSR VDD Data transfer tSR 80% 0.9V tRSOFF 0.9V tPOF 50% 80% tRSOFF 50% Note: 1. If the conditions of Reset timing are not satisfied in power ON/OFF sequence, the internal Power on Reset (POR) circuit will not operate normally. 2. If the VDD drops lower than the minimum operating voltage during operating, the conditions of Power on Reset timing must also be satisfied. That is the VDD drop to 0.9V and keep at 0.9V for 10ms (min.) before rising to the normal operating voltage. 3. Data transfers on the I2C serial bus should at least be delayed for 1ms after the power-on sequence to ensure that the reset operation is complete. 4. If it is difficult to meet the power on reset timing specifications, users can execute the software reset command after power-on. Rev. 1.00 8 April 18, 2014 HT9B92G Functional Description Column Driver Outputs The LCD drive section includes 4 column outputs COM0~COM3 which should be connected directly to the LCD panel. The column output signals are generated in accordance with the selected LCD drive mode. The unused column outputs should be left open-circuit if less than 4 column outputs are required. Power-On Reset When the power is applied, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: • All common outputs are set to VSS. • All segment outputs are set to VSS. • LCD Driver Output Waveform: A-type inversion. Address Pointer • Internal oscillator is selected. The addressing mechanism for the display RAM is implemented using the address pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the address pointer by the Display Data Input command. • The 1/3 bias drive mode is selected. • LCD bias generator is in an off state. • LCD Display and internal oscillator are in off states. • Power save mode is set to normal current. • Frame Frequency is set to 80Hz. • Blinking function is switched off. Display Memory – RAM Structure Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. The display RAM is static 40×4 bits RAM which stores the LCD data. Logic “1” in the RAM bit-map indicates the “on” state of the corresponding LCD segment; similarly, logic 0 indicates the “off” state. System Oscillator The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the segments operated with respect to COM0. In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with COM1, COM2 and COM3 respectively. The following diagram is a data transfer format for I2C interface. The timing for the internal logic and the LCD drive signals are generated by the internal oscillator or external clock source input. The System Clock frequency (fSYS) determines the LCD frame frequency. During initial system power on the System Oscillator will be in the stop state. Segment Driver Outputs The LCD drive section includes up to 40 segment outputs SEG0~SEG39 which should be connected directly to the LCD panel. The segment output signals are generated in accordance with the multiplexed common signals and with the data resident in the display latch. The unused segment outputs should be left open-circuit. Rev. 1.00 MSB SDA Data LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COM0 COM1 COM2 COM3 COM0 COM1 COM2 COM3 Address n Address n+1 LCD Display Output Data Transfer Format for I2C bus 9 April 18, 2014 HT9B92G Address COM0 COM1 COM2 COM3 Output 00H SEG0 01H SEG1 02H SEG2 03H SEG3 04H SEG4 05H SEG5 06H SEG6 07H SEG7 08H SEG8 09H SEG9 0AH SEG10 0BH SEG11 0CH SEG12 0DH SEG13 0EH SEG14 0FH SEG15 10H SEG16 11H SEG17 12H SEG18 13H SEG19 14H SEG20 15H SEG21 16H SEG22 17H SEG23 18H SEG24 19H SEG25 1AH SEG26 1BH SEG27 1CH SEG28 1DH SEG29 1EH SEG30 1FH SEG31 20H SEG32 21H SEG33 22H SEG34 23H SEG35 24H SEG36 25H SEG37 26H SEG38 27H RAM Data SEG39 Bit 3 Bit 2 Bit 1 Bit 0 Note: 1. The LCD display RAM address is specified by the Address Set command and the address will be automatically incremented by one after a 4-bit data is shifted in. 2. The address of the display RAM data is from 00H to 27H. Rev. 1.00 10 April 18, 2014 HT9B92G LCD Bias Generator Fractional LCD biasing voltages, known as 1/2 or 1/3 bias voltage, are obtained from an internal voltage divider of three series resistors connected between VLCD and VDD. The centre resistor can be switched out of circuits to provide a 1/2 bias voltage level configuration. LCD Drive Mode Waveforms • When the LCD drive mode is selected as 1/4 duty and 1/2 bias, the waveform and LCD display is shown as follows: AAType Typeinversion inversion BBType Typeinversion inversion tLCD COM0 COM0 COM1 COM1 COM2 COM2 COM3 COM3 SEG n SEG n SEG n+1 SEG n+1 SEG n+2 SEG n+2 SEG n+3 SEG n+3 LCD LCDsegment segment tLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM0 Vop/2 COM0 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM1 Vop/2 COM1 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM2 Vop/2 COM2 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM3 Vop/2 COM3 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n Vop/2 SEG n VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n+1 Vop/2 SEG n+1 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n+2 Vop/2 SEG n+2 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n+3 Vop/2 SEG n+3 VLCD VLCD VLCD VLCD State1 State1 (on) (on) State2 State2 (off) (off) Waveforms for 1/4 duty drive mode with 1/2 bias (VOP=VDD-VLCD) Note: tLCD=1/fLCD Rev. 1.00 11 April 18, 2014 HT9B92G • When the LCD drive mode is selected as 1/4 duty and 1/3bias, the waveform and LCD display is shown as follows: BBType Typeinversion inversion AAType Typeinversion inversion COM0 COM0 VDD VDD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 COM0 COM0 VLCD VLCD COM1 COM1 VLCD VLCD VDD VDD VDD VDD 2Vop/3 2Vop/3 COM1 COM1 VLCD VLCD COM2 COM2 VDD VDD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 COM2 COM2 VDD VDD 2Vop/3 2Vop/3 COM3 COM3 VLCD VLCD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 SEG n SEG n VLCD VLCD SEG n+1 SEG n+1 VLCD VLCD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 SEG n+1 SEG n+1 Vop/3 Vop/3 VLCD VLCD VDD VDD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 SEG n+2 SEG n+2 VLCD VLCD 2Vop/3 2Vop/3 Vop/3 Vop/3 VLCD VLCD Vop/3 Vop/3 VLCD VLCD VDD VDD SEG n+3 SEG n+3 Vop/3 Vop/3 VDD VDD VLCD VLCD SEG n+2 SEG n+2 Vop/3 Vop/3 VDD VDD Vop/3 Vop/3 State2 State2 (off) (off) VLCD VLCD 2Vop/3 2Vop/3 Vop/3 Vop/3 State1 State1 (on) (on) Vop/3 Vop/3 VDD VDD VLCD VLCD SEG n SEG n Vop/3 Vop/3 VLCD VLCD VLCD VLCD COM3 COM3 Vop/3 Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 LCD LCDsegment segment tLCD tLCD VDD VDD SEG n+3 SEG n+3 2Vop/3 2Vop/3 Vop/3 Vop/3 VLCD VLCD Waveforms for 1/4 duty drive mode with 1/2 bias (VOP=VDD-VLCD) Note: tLCD=1/fLCD Rev. 1.00 12 April 18, 2014 HT9B92G Blinking Function Data Validity The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the data line can only change when the clock signal on the SCL line is Low as shown in the diagram. The device contains versatile blinking capabilities. The whole display can be blinked at frequencies selected by the Blinking Frequency command. The blinking frequency is a subdivided ratio of the system frequency. The ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table: Blinking Mode Blinking frequency (Hz) 0 Blink off 1 0.5 2 1 3 2 SDA SCL Data line stable; Data valid START and STOP Conditions • A high to low transition on the SDA line while SCL is high defines a START condition. • A low to high transition on the SDA line while SCL is high defines a STOP condition. Frame Frequency • START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The device provides four frame frequencies selected with the Frame Frequency command known as 80Hz, 71Hz, 64Hz and 53Hz respectively. Mode Frame frequency (Hz) @ VDD=3.3V 0 80 1 71 2 64 3 53 Change of data allowed • The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the START(S) and repeated START (Sr) conditions are functionally identical. SDA SDA SCL I C Serial Interface 2 P START condition STOP condition Byte Format I2C Operation Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit, MSB, first. The device supports I2C serial interface. The I2C bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are connected to the positive supply via pull-up resistors. When the bus is free, both lines are high. Devices connected to the bus must have open-drain or open-collector outputs to implement a wired-or function. Data transfer is initiated only when the bus is not busy. Rev. 1.00 SCL S P SDA Sr SCL 13 S or Sr 1 2 7 8 9 ACK 1 2 3-8 9 ACK P or Sr April 18, 2014 HT9B92G I2C Interface Write Operation Acknowledge • Each bytes of eight bits is followed by one acknowledge bit. This Acknowledge bit is a low level placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse. Byte Write Operation • Single Command Type A Single Command write operation requires a START condition, a slave address with a write control bit, a command byte and a STOP condition for a single command write operation. • A slave receiver which is addressed must generate an Acknowledge, ACK, after the reception of each byte. • Compound Command Type A Compound Command write operation requires a START condition, a slave address with a write control bit, a command byte, up to two command setting bytes and a STOP condition for a compound command write operation. • The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. • A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition. • Display RAM Single Data Byte A display RAM data byte write operation requires a START condition, a slave address with a write control bit, a valid Register Address byte, a Data byte and a STOP condition. The start address can only be set from 00H to 1FH. The start address which is greater than 1FH will be regarded as a command. Therefore, it is recommended that the start address should be set from 00H to 1FH. Data Output by Transmitter not acknowledge Data Outptu by Receiver acknowledge SCL From Master 1 2 7 8 Display RAM Page Write Operation 9 After a START condition the slave address with a write control bit is placed on the bus followed with the specified display RAM Register Address of which the contents are written into the internal address pointer. The data to be written into the memory will be transmitted next. The internal address pointer will be incremented by 1 after a 4-bit data is shifted in. Then the acknowledge clock pulse will be received after an 8-bit data is shifted. After the internal address point reaches the maximum memory address, 27H, the address pointer will be reset to 00H. It is strongly recommended to write the display RAM data from address 00H to 27H using the Display RAM Page Write Operation. S START condition clock pulse for acknowledgement Slave Addressing • The slave address byte is the first byte received following the START condition form the master device. The first seven bits of the first byte make up the slave address. This device only supports the write operation and therefore, the eighth data bit, R/W, which is used to define a read or write operation will be fixed at a “0” state. If the R/W bit is set to 1 to execute a read operation, it will result in no operation. • The device address bits are “0111110”. When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line. Slave Address MSB 0 1 1 1 1 1 LSB 0 0 R/W=0 Rev. 1.00 14 April 18, 2014 HT9B92G Slave Address S 0 1 1 1 Command byte 1 1 0 0 1 P Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write ACK ACK 1st I2C Single Command Type Write Operation 0 1 1 1 Command setting Command byte Slave Address S 1 1 0 0 1 Write Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACK 1 ACK 1st P Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACK ACK 3rd I2C Compound Command Type Write Operation Slave Address S 0 1 1 1 Register Address byte 1 1 0 0 0 Write 0 0 A4 A3 A2 Data byte A1 D7 A0 ACK D6 D5 D4 D3 D2 D1 P D0 ACK ACK I C Display RAM Single Data Byte Write Operation 2 Command Summary The bit 7 denoted as “C” here is the control bit which is used to determine that the next byte is the display RAM data or command byte. C bit Remark 0 Next byte is Display RAM data. 1 Next byte is command. Slave Address S 0 1 1 1 1 Register Address byte 1 0 0 Write Data byte D7 D6 th n D5 data D4 D3 0 0 0 A4 A3 A2 A1 A0 Address n ACK ACK Data byte D2 ( n+1) D1 th D0 D7 data D6 (n+2) D5 th D4 data D3 Data byte D2 ( n+3) D1 th ACK D0 D7 data D6 (N-1) ACK D5 th data D4 D3 D2 N th D1 P D0 data ACK ACK I C Interface N Bytes Display RAM Data Write Operation 2 Display RAM Address Setting Command This command is used to define the start address of the display RAM. Function Address Pointer (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 C 0 0 A4 A3 A2 A1 A0 Note Display RAM memory start address Note: 1. The address ranges from 00H to 1FH. 2. It is strongly recommended to write the display RAM data from address 00H to 27H at one time. 3. Power on status: the address will be set to 00H. 4. If the programmed command is not defined, the function will not be affected. Rev. 1.00 15 April 18, 2014 HT9B92G Drive Mode Setting Command This command is used to control the LCD bias and display on/off. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Bias and Display on/off setting C 1 0 X P3 P2 X X Note — Note: P2 Bias 0 1/3 bias (default) 1 1/2 bias P3 LCD Display On/Off 0 Off (default) 1 On ●●Power on status: The 1/3 bias drive mode is selected and the LCD display is switched off. ●●If the programmed command is not defined, the function will not be affected. Display Control Command This command is used to select the Current mode according to the characteristics of the LCD panel for achieving high display quality and LCD driver output waveform set and frame frequency select. Function (MSB) Bit7 Bit6 Display Control Setting C 0 Bit5 Bit4 Bit3 Bit2 1 P4 P3 P2 Bit1 (LSB) Bit0 P1 P0 Note — Note: P [1:0] Power Save Mode 00 Low Current2 Mode 01 Low Current1 Mode 10 Normal Current Mode 11 High Current Mode P2 Current Consumption Remark x 0.5 ●●The data listed here is for reference only. The actual data depends upon the panel load. ●●Please meet the condition: VDD−VLCD≥3V when used in High current mode. x 0.67 x 1 (default) x 1.8 LCD Driver Output Waveform 0 A Type inversion (default) 1 B Type inversion Remark P [4:3] Frame Frequency @VDD=3.3V (Hz) Remark ●●The data listed here is for reference only. The actual data depends upon the panel load. ●●Please meet the condition: VDD−VLCD≥3V when used in High current mode. 00 80 (default) 01 71 10 64 11 53 ●●The setting of the frame frequency, LCD output waveform and current mode will influence the display image qualities. Please select a proper display setting suitable for the current consumption and display image quality with LCD panel. Mode Flicker Frame Frequency O LCD Driver Output Waveform O Image Quality/Contrast O Power Save Mode O ●●If the programmed command is not defined, the function will not be affected. Rev. 1.00 16 April 18, 2014 HT9B92G Software Reset and Oscillator Mode Setting Command This command is used to select the system oscillator source and to initiate a software reset. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 System Oscillator Setting and Software Reset P1 C 1 1 Software Reset 0 No Operation (default) 1 Initiate a Software Reset P0 0 1 Bit1 X P1 (LSB) Bit0 Note P0 — Remark When a “Software Reset” is executed, the device will be reset to an initial condition. Other settings can be configured after Software reset is completed. Oscillator Mode Remark ●●When the internal oscillator is used, the OSCIN pin must be Internal Oscillator (default) connected to VSS or open-circuit. ●●When the external clock mode is selected, the external clock External Clock Input Mode is supplied on the OSCIN pin. 0 1 When the software reset is executed, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: ●●All common outputs are set to VSS. ●●All segment outputs are set to VSS. ●●LCD Driver Output Waveform: A-type inversion. ●●Internal oscillator source is selected. ●●1/3 bias is selected. ●●LCD bias generator is off state. ●●LCD Display and system oscillation are off state. ●●Power save mode is set to normal current. ●●Frame Frequency is set to 80Hz. ●●Blinking function is switched off. Note that if the programmed command is not defined, the function will not be affected. Blinking Frequency Setting Command This command defines the blinking frequency of the display modes. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Blinking Frequency setting C 1 1 1 0 X Bit1 (LSB) Bit0 Note P1 P0 — Note: P [1:0] Blinking Frequency 00 Blinking off (default) 01 0.5 Hz 10 1 Hz 11 2 Hz Remark — ●●Power on status: Blinking function is switched off. ●●If the programmed command is not defined, the function will not be affected. Rev. 1.00 17 April 18, 2014 HT9B92G All Pixels On/Off Setting Command This command controls that all pixels are switched on or off when the LCD normally displays. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 All Pixels On/Off setting C 1 1 1 1 1 P1 Note P0 — Note: P [1:0] Blinking Frequency Remark 00 Normal Display (default) 01 All Pixels Off ●●This command is only available when the LCD is normally displayed. The display RAM contents will not be changed when this command is executed. ●●All pixels are switched on or off regardless of the display RAM data when the relevant setting is selected. 10 All Pixels On 11 All Pixels Off ●●Power on status: Normal display. ●●If the programmed command is not defined, the function will not be affected. Operation Flow Chart Access procedures are illustrated below using flowcharts. Initialization Display Data Write (Address Setting) Power On Start Software Reset Setting Address setting Internal LCD Bias Setting Display data RAM write LCD Blinking Frequency Setting Display on LCD Current Mode Setting Next processing LCD Frame Frequency Setting LCD Output Waveform Setting Oscillator Source Input Mode Setting Next processing Rev. 1.00 18 April 18, 2014 HT9B92G Display Quality or Operating Current (Power Save Mode) Setting Start Reduce operating current or enhance display quality. Display quality 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. A type inversion 3. High current mode Operating current 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. Low Current 2 mode Screen Flicker ? 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. B type inversion 3. Low Current 2 mode No YES 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. Low Current 1 mode Screen Flicker ? 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. B type inversion 3. Low Current 1 mode No YES 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. Normal Current mode Screen Flicker ? 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. B type inversion 3. Normal Current mode No YES 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. High Current mode Rev. 1.00 19 April 18, 2014 HT9B92G Application Circuit Internal Oscillator Circuit Mode VLCD * Adjust VR to fit LCD display VR* VDD VDD 0.1 F 4.7k HT9B92G 4.7k COM VDD SCL MCU SEG SDA 4 40 LCD Panel VSS VSS VSS OSCIN TEST1 TEST2 External Clock Input Mode VLCD * Adjust VR to fit LCD display VR* VDD VDD 0.1uF 4.7KΩ VDD MCU HT9B92G 4.7KΩ COM SCL SDA SEG 4 40 LCD panel VSS VSS VSS OSCIN TEST1 TEST2 Rev. 1.00 20 April 18, 2014 HT9B92G Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com. Rev. 1.00 21 April 18, 2014