RGB666 to YCbCr8Bit Converter - Documentation

RGB666 to YCbCr 8-Bit Converter
April 2013
Reference Design RD1155
Introduction
RGB666 to 8-bit YCbCr converter converts RGB color space to YCbCr 4:2:2 color space. To facilitate easy insertion to practical video systems, this design example takes video stream control signals (H_SYNC, V_SYNC, and
DEN) and delays them appropriately, so that control signals can be easily synchronized with the output video
stream. This document provides a brief description of RGB666 to YcbCr 8-bit Converter and its implementation.
The design is implemented in VHDL. The Lattice iCEcube2™ Place and Route tool integrated with the Synopsys
Synplify Pro® synthesis tool is used for the implementation of the design. The design can be targeted to other
iCE40™ FPGA product family devices.
Features
• RGB666 mode input and 8-bit YCbCr 4:2:2 mode output
• Pipelined implementation
• Latency of 5 cycles
• H_SYNC, V_SYNC and DEN control signals for video synchronization
Functional Description
Figure 1. Functional Description
iCE CMD
i CLK
IO
i RST
IO
IO
RGB
Source
i_PIX_DEN
IO
i_H_SYNC
IO
i_V_SYNC
IO
i_Red[5:0]
IO
IO
i_Blue[5:0]
IO
IO
i_Green[5:0]
IO
IO
RGB666 to
YCbCr
Converter
IO
IO
o_PIX_DEN
o_H_SYNC
o_V_SYNC
o_Y[7:0]
YCbCr
Device
o_Cb[7:0]
o_Cr[7:0]
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rd1155_01.0
RGB666 to YCbCr 8-Bit Converter
Signal Description
Table 1. Signal Description
Signal
Width
Type
Description
i_CLK
1
Input
Input Pixel Clock
i_RST
1
Input
Asynchronous Active High System Reset
i_PIX_DEN
1
Input
Data Enable (RGB valid) synchronized with pixel clock
i_H_SYNC
1
Input
Horizontal Sync
i_V_SYNC
1
Input
Vertical Sync
i_RED
6
Input
Red component of pixel
i_GREEN
6
Input
Green component of pixel
i_BLUE
6
Input
Blue component of pixel
o_PIX_DEN
1
Output
YCbCr valid data synchronized with pixel clock
o_H_SYNC
1
Output
Pipelined Horizontal Sync
o_V_SYNC
1
Output
Pipelined Vertical Sync
o_Y
8
Output
Converted Y component
o_Cb
8
Output
Converted Cb component
o_Cr
8
Output
Converted Cr component
Design Module Description
Figure 2. Functional Block Diagram
Y
F/F
M
U
L
i CLK
i RST
A
D
D
F/F
F/F
MIN/
F/F
MAX
o_PIX_DEN
Red
i_PIX_DEN
i_H_SYNC
o_H_SYNC
F/F
i_V_SYNC
M
U
L
i_Red[5:0]
i_Blue[5:0]
Cb
A
D
D
F/F
F/F
MIN/
MAX
o_V_SYNC
F/F
o_Y[7:0]
o_Cb[7:0]
Green
o_Cr[7:0]
Cr
i_Green[5:0]
F/F
M
U
L
A
D
D
F/F
Blue
Configurable parameter
None
2
F/F
MIN/
MAX
F/F
RGB666 to YCbCr 8-Bit Converter
Register Map
This design does not have any user accessible registers or memory.
Design Details
This module converts RGB to YCbCr, consisting of one luma component(Y) representing brightness, and two
chroma components (Cb and Cr) as per the following conversion expressions:
• Y = 16 + (0.2567890625 * Red) + (0.50412890625 * Green) + (0.09790625 * Blue)
• Cb = 128 + (0.14822265625 * Red) + (0.2909921875 * Green) + (0.43921484375 * Blue)
• Cr = 128 + (0.43921484375 * Red) + (0.3677890625 * Green) + (0.071442578125 * Blue)
The implementation comprises of a set of constant coefficient multipliers implemented as shift and add adders.
This is a fully synchronous design and all the modules listed in the block diagram generate registered outputs,
clocked by input pixel clock. Considering the large amount of data path involved here, a pipelined implementation is
provided to improve the performance. Computed Y, Cb and Cr values are clipped and limited to maximum/minimum
permissible range. To facilitate easy insertion to practical video systems, the design conveniently pipelines the
video control signals H_SYNC, V_SYNC, and DEN by introducing a latency of 5 clock cycles.
Initialization Conditions
This design does not have any user specific initialization conditions.
Timing Diagram
Figure 3. Timing Diagram
o_H_SYNC
o_V_SYNC
o_Y/Cb/Cr
o_PIX_DEN
i_Reb/Green/Blue
i_H_SYNC
i_V_SYNC
i_RST
i_CLK
3
RGB666 to YCbCr 8-Bit Converter
Simulation Waveforms
Figure 4. Simulation Waveforms
Usage Examples
RGB to YCbCr converters are useful in applications like JPEG and MPEG image encoders, which is used in DVDs,
digital TV and Video CDs, where images are coded in YCbCr format. YCbCr is also the most preferred format for
hue and saturation control of images.
Simulation setup comprises of a testbench which provides input RGB666 values for various colors like red, blue,
green, white etc… The DUT generated output YCbCr 8-bit values are compared against the corresponding known
YCbCr values.
Implementation
This design is implemented in VHDL. When using this design in a different device, density, speed or grade, performance and utilization may vary.
Performance and Resource Utilization
Table 2. Performance and Resource Utilization
Family
Language
Utilization (LUTs)
fMAX (MHz)
I/Os
Architecture
Resources
iCE401
VHDL
334
>50
49
(78/160) PLBs
1. Performance and utilization characteristics are generated using iCE40-LP1K-CM121 with iCEcube2 design software.
References
• iCE40 Family Handbook
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RGB666 to YCbCr 8-Bit Converter
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
April 2013
01.0
Change Summary
Initial release.
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