KAD5512HP ® Data Sheet October 1, 2009 High Performance 12-Bit, 250/210/170/125MSPS ADC FN6808.3 Features The KAD5512HP is the high-performance member of the KAD5512 family of 12-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5512HP is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. • Pin-Compatible with the KAD5512P Family, Offering 2.2dB Higher SNR • Programmable Gain, Offset and Skew control • 950MHz Analog Input Bandwidth • 60fs Clock Jitter • Over-Range Indicator • Selectable Clock Divider: ÷1, ÷2 or ÷4 • Clock Phase Selection • Nap and Sleep Modes Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512HP is available in 72- and 48-contact QFN packages with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40°C to +85°C). • Two’s Complement, Gray Code or Binary Data Format Key Specifications • Pb-Free (RoHS Compliant) • SNR = 68.2dBFS for fIN = 105MHz (-1dBFS) • DDR LVDS-Compatible or LVCMOS Outputs • Programmable Built-in Test Patterns • Single-Supply 1.8V Operation Applications • SFDR = 81.1dBc for fIN = 105MHz (-1dBFS) • Power Amplifier Linearization • Power Consumption - 429/345mW @ 250/125MSPS (SDR Mode) - 390/309mW @ 250/125MSPS (DDR Mode) • Radar and Satellite Antenna Array Processing • Broadband Communications OVDD AVDD CLKDIV • High-Performance Data Acquisition • Communications Test Equipment • WiMAX and Microwave Receivers CLKP CLKOUTP CLOCK GENERATION CLKN RESOLUTION SPEED (MSPS) KAD5514P-25 14 250 KAD5514P-21 14 210 KAD5514P-17 14 170 ORN KAD5514P-12 14 125 OUTFMT KAD5512P-50 12 500 OUTMODE KAD5512P-25, KAD5512HP-25 12 250 KAD5512P-21, KAD5512HP-21 12 210 KAD5512P-17, KAD5512HP-17 12 170 KAD5512P-12, KAD5512HP-12 12 125 KAD5510P-50 10 500 CLKOUTN D[11:0]P 12-BIT 250 MSPS ADC VINN VCM + – AVSS NAPSLP 1.25V SPI CONTROL CSB SCLK SDIO SDO SHA 1 D[11:0]N DIGITAL ERROR CORRECTION ORP LVDS/CMOS DRIVERS OVSS VINP Pin-Compatible Family MODEL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. KAD5512HP Ordering Information PART NUMBER PART MARKING SPEED (MSPS) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # KAD5512HP-25Q72 (Note 1) KAD5512HP-25 Q72EP-I 250 -40 to +85 72 Ld QFN L72.10x10D KAD5512HP-21Q72 (Note 1) KAD5512HP-21 Q72EP-I 210 -40 to +85 72 Ld QFN L72.10x10D KAD5512HP-17Q72 (Note 1) KAD5512HP-17 Q72EP-I 170 -40 to +85 72 Ld QFN L72.10x10D KAD5512HP-12Q72 (Note 1) KAD5512HP-12 Q72EP-I 125 -40 to +85 72 Ld QFN L72.10x10D KAD5512HP-25Q48 (Note 2) KAD5512HP-25 Q48EP-I 250 -40 to +85 48 Ld QFN L48.7x7E KAD5512HP-21Q48 (Note 2) KAD5512HP-21 Q48EP-I 210 -40 to +85 48 Ld QFN L48.7x7E KAD5512HP-17Q48 (Note 2) KAD5512HP-17 Q48EP-I 170 -40 to +85 48 Ld QFN L48.7x7E KAD5512HP-12Q48 (Note 2) KAD5512HP-12 Q48EP-I 125 -40 to +85 48 Ld QFN L48.7x7E NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020 2 FN6808.3 October 1, 2009 KAD5512HP Table of Contents Absolute Maximum Ratings ......................................... 4 Serial Peripheral Interface ........................................... 22 Thermal Information...................................................... 4 SPI Physical Interface................................................ SPI Configuration....................................................... Device Information ..................................................... Indexed Device Configuration/Control ....................... Global Device Configuration/Control.......................... Device Test ................................................................ SPI Memory Map ....................................................... Operating Conditions.................................................... 4 Electrical Specifications ............................................... 4 Digital Specifications .................................................... 6 Timing Diagrams ........................................................... 7 Switching Specifications .............................................. 8 Pinout/Package Information......................................... 9 Pin Descriptions - 72QFN........................................... Pinout ......................................................................... Pin Descriptions - 48QFN........................................... Pinout ......................................................................... 9 11 12 13 Typical Performance Curves ........................................ 14 Theory of Operation ...................................................... 17 Functional Description ................................................ Power-On Calibration ................................................. User-Initiated Reset.................................................... Analog Input ............................................................... Clock Input ................................................................. Jitter............................................................................ Voltage Reference...................................................... Digital Outputs ............................................................ Over-Range Indicator ................................................. Power Dissipation....................................................... Nap/Sleep................................................................... Data Format ............................................................... 3 17 17 18 18 19 20 20 20 20 20 21 21 23 24 24 24 25 27 28 Equivalent Circuits ....................................................... 29 72 Pin/48 Pin Package Options ................................... 30 ADC Evaluation Platform ............................................. 31 Layout Considerations................................................. 31 Split Ground and Power Planes................................. Clock Input Considerations ........................................ Exposed Paddle......................................................... Bypass and Filtering .................................................. LVDS Outputs ............................................................ LVCMOS Outputs ...................................................... Unused Inputs............................................................ 31 31 31 31 31 31 31 Definitions ..................................................................... 31 Revision History ........................................................... 32 Package Outline Drawings........................................... 33 L48.7x7E.................................................................... . 33 L72.10x10D................................................................ . 34 FN6808.3 October 1, 2009 KAD5512HP Absolute Maximum Ratings Thermal Information AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Inputs to AVSS . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Thermal Resistance (Typical, Note 3) θJA (°C/W) 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). KAD5512HP-25 (Note 4) PARAMETER SYMBOL CONDITIONS KAD5512HP-21 (Note 4) KAD5512HP-17 (Note 4) KAD5512HP-12 (Note 4) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 DC SPECIFICATIONS Analog Input Full-Scale Analog Input Range VFS Differential Input Resistance RIN Differential 500 500 500 500 Ω Input Capacitance CIN Differential 2.6 2.6 2.6 2.6 pF Full Scale Range Temp. Drift AVTC Full Temp 90 90 90 90 ppm/°C Input Offset Voltage VOS Gain Error -10 ±2 10 -10 ±2 10 -10 ±2 10 -10 ±2 10 VP-P mV EG ±2 ±2 ±2 ±2 % VCM 0.535 0.535 0.535 0.535 V Inputs Common Mode Voltage 0.9 0.9 0.9 0.9 V CLKP,CLKN Input Swing 1.8 1.8 1.8 1.8 V Common-Mode Output Voltage Clock Inputs Power Requirements 1.8V Analog Supply Voltage AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.8V Digital Supply Voltage OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.8V Analog Supply Current IAVDD 170 180 157 166 145 153 129 137 mA 1.8V Digital Supply Current (SDR) (Note 5) IOVDD 68 76 66 74 64 72 62 70 mA 3mA LVDS 4 FN6808.3 October 1, 2009 KAD5512HP Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5512HP-25 (Note 4) PARAMETER SYMBOL CONDITIONS MIN TYP KAD5512HP-21 (Note 4) MAX MIN TYP KAD5512HP-17 (Note 4) MAX MIN TYP KAD5512HP-12 (Note 4) MAX MIN TYP MAX UNITS 1.8V Digital Supply Current (DDR) (Note 5) IOVDD 3mA LVDS 46 44 43 42 mA Power Supply Rejection Ratio PSRR 30MHz, 200mVP-P signal on AVDD -36 -36 -36 -36 dB Total Power Dissipation Normal Mode (SDR) PD 3mA LVDS 429 Normal Mode (DDR) PD 3mA LVDS 390 Nap Mode PD Sleep Mode PD 463 402 433 378 363 406 345 339 376 309 mW mW 148 163 142 157 136 151 129 143 mW CSB at logic high 2 6 2 6 2 6 2 6 mW Nap Mode Wakeup Time (Note 6) Sample Clock Running 1 1 1 1 µs Sleep Mode Wakeup Time (Note 6) Sample Clock Running 1 1 1 1 ms AC SPECIFICATIONS Differential Nonlinearity DNL -0.75 ±0.2 0.75 -0.75 ±0.2 0.75 -0.75 ±0.2 0.75 -0.75 ±0.2 0.75 LSB Integral Nonlinearity INL -2.0 ±0.6 2.0 ±1.1 2.0 ±1.1 2.0 ±1.4 2.5 LSB Minimum Conversion Rate (Note 7) fS MIN 40 MSPS Maximum Conversion Rate fS MAX Signal-to-Noise Ratio SNR 40 250 fIN = 10MHz fIN = 105MHz Signal-to-Noise and Distortion Effective Number of Bits SINAD 40 210 68.3 65.9 68.2 -2.0 40 170 68.8 66.4 68.7 -2.5 125 69.1 67.1 68.9 67.1 MSPS 69.3 dBFS 69.1 dBFS fIN = 190MHz 67.8 68.3 68.6 68.7 dBFS fIN = 364MHz 66.8 67.3 67.8 67.7 dBFS fIN = 695MHz 64.4 64.9 65.7 65.2 dBFS fIN = 995MHz 62.4 62.9 63.8 63.1 dBFS fIN = 10MHz 68.2 68.7 69.0 69.2 dBFS 68.9 dBFS fIN = 105MHz ENOB -2.0 65.6 68.0 66.1 68.7 66.6 68.7 66.6 fIN = 190MHz 67.5 68.0 68.2 68.4 dBFS fIN = 364MHz 66.0 66.4 66.7 66.8 dBFS fIN = 695MHz 59.1 59.1 60.0 59.8 dBFS fIN = 995MHz 48.6 48.2 49.2 50.5 dBFS fIN = 10MHz 11.0 11.1 11.2 11.2 Bits 11.1 Bits fIN = 105MHz 10.6 11.0 10.7 11.1 10.8 11.1 10.8 fIN = 190MHz 10.9 11.0 11.0 11.1 Bits fIN = 364MHz 10.7 10.7 10.8 10.8 Bits fIN = 695MHz 9.5 9.5 9.7 9.6 Bits fIN = 995MHz 7.8 7.7 7.9 8.1 Bits 5 FN6808.3 October 1, 2009 KAD5512HP Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5512HP-25 (Note 4) PARAMETER SYMBOL Spurious-Free Dynamic Range Intermodulation Distortion SFDR CONDITIONS fIN = 10MHz fIN = 105MHz IMD MIN TYP KAD5512HP-21 (Note 4) MAX MIN 86.4 70 81.1 TYP KAD5512HP-17 (Note 4) MAX MIN TYP 87.2 70 85.5 KAD5512HP-12 (Note 4) MAX MIN 87.3 70 82.0 70 TYP MAX UNITS 84.9 dBc 81.7 dBc fIN = 190MHz 79.6 80.0 79.2 80.3 dBc fIN = 364MHz 75.0 75.6 75.1 75.5 dBc fIN = 695MHz 60.8 60.0 61.3 61.6 dBc fIN = 995MHz 48.3 47.9 48.7 50.2 dBc fIN = 70MHz -89.0 -92.2 -94.6 -94.8 dBFS fIN = 170MHz -91.4 -86.9 -91.7 -85.7 dBFS 10-12 10-12 10-12 950 950 950 Word Error Rate WER 10-12 Full Power Bandwidth FPBW 950 MHz NOTES: 4. Parameters with MIN and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C). 5. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 6. See Nap/Sleep Mode description on page 21 for more detail. 7. The DLL Range setting must be changed for low speed operation. See Table 14 on page 26. Digital Specifications PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0 1 10 µA -25 -12 -5 µA INPUTS Input Current High (SDIO,RESETN) IIH VIN = 1.8V Input Current Low (SDIO,RESETN) IIL VIN = 0V Input Voltage High (SDIO, RESETN) VIH Input Voltage Low (SDIO, RESETN) VIL Input Current High (OUTMODE, NAPSLP, CLKDIV, OUTFMT) (Note 8) IIH 15 Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT) IIL -40 Input Capacitance CDI 6 1.17 V .63 V 25 40 µA 25 -15 µA 3 pF FN6808.3 October 1, 2009 KAD5512HP Digital Specifications (Continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS OUTPUTS Differential Output Voltage Output Offset Voltage VT 3mA Mode VOS 3mA Mode 620 950 mVP-P 965 980 mV Output Rise Time tR 500 ps Output Fall Time tF 500 ps OVDD - 0.1 V CMOS OUTPUTS Voltage Output High VOH IOH = -500µA Voltage Output Low VOL IOL = 1mA OVDD - 0.3 0.1 0.3 V Output Rise Time tR 1.8 ns Output Fall Time tF 1.4 ns Timing Diagrams SAMPLE N SAMPLE N INP INP INN INN tA tA CLKN CLKP tCPD CLKN CLKP LATENCY = L CYCLES tCPD CLKOUTN CLKOUTP CLKOUTN CLKOUTP tDC tDC tPD D[10/8/6/4/2/0]P ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS N-L N-L N-L + 1 N-L + 1 N-L + 2 N-L + 2 D[10/8/6/4/2/0]N LATENCY = L CYCLES EVEN BITS N tPD D[11/0]P D[11/0]N DATA N-L FIGURE 1A. DDR DATA N-L + 1 DATA N FIGURE 1B. SDR FIGURE 1. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 20 SAMPLE N SAMPLE N INP INP INN INN tA tA CLKN CLKP CLKN CLKP tCPD LATENCY = L CYCLES tCPD CLKOUT CLKOUT tDC tDC tPD D[10/8/6/4/2/0] LATENCY = L CYCLES ODD BITS N-L EVEN BITS ODD BITS N-L N-L + 1 EVEN BITS ODD BITS EVEN BITS N-L + 1 N-L + 2 N-L + 2 FIGURE 2A. DDR EVEN BITS N tPD D[11/0] DATA N-L DATA N-L + 1 DATA N FIGURE 2B. SDR FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 20 7 FN6808.3 October 1, 2009 KAD5512HP Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS ADC OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 60 fs Output Clock to Data Propagation Delay, LVDS Mode (Note 9) Output Clock to Data Propagation Delay, CMOS Mode (Note 9) DDR Rising Edge tDC -260 -50 120 ps DDR Falling Edge tDC -160 10 230 ps SDR Falling Edge tDC -260 -40 230 ps DDR Rising Edge tDC -220 -10 200 ps DDR Falling Edge tDC -310 -90 110 ps SDR Falling Edge tDC -310 -50 200 ps Latency (Pipeline Delay) Overvoltage Recovery L 8.5 cycles tOVR 1 cycles SPI INTERFACE (Notes 10, 11) SCLK Period Write Operation t CLK 16 cycles (Note 10) Read Operation tCLK 66 cycles SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) Read or Write CSB↓ to SCLK↑ Setup Time Read or Write tS 1 cycles CSB↑ after SCLK↑ Hold Time Read or Write tH 3 cycles Data Valid to SCLK↑ Setup Time Write tDSW 1 cycles Data Valid after SCLK↑ Hold Time Write tDHW 3 cycles Data Valid after SCLK↓ Time Read tDVR Data Invalid after SCLK↑ Time Read tDHR 3 cycles Sleep Mode CSB↓ to SCLK↑ Setup Time (Note 12) Read or Write in Sleep Mode tS 150 µs 25 50 75 16.5 % cycles NOTES: 8. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 9. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. 10. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. 11. The SPI may operate asynchronously with respect to the ADC sample clock 12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). 8 FN6808.3 October 1, 2009 KAD5512HP Pinout/Package Information Pin Descriptions - 72QFN LVDS [LVCMOS] FUNCTION SDR MODE PIN NUMBER LVDS [LVCMOS] NAME 1, 6, 12, 19, 24, 71 AVDD 1.8V Analog Supply 2-5, 13, 14, 17, 18, 28-31 DNC Do Not Connect 7, 8, 11, 72 AVSS Analog Ground 9, 10 VINN, VINP 15 VCM 16 CLKDIV 20, 21 CLKP, CLKN Clock Input True, Complement 22 OUTMODE Output Mode (LVDS, LVCMOS) 23 NAPSLP Power Control (Nap, Sleep modes) 25 RESETN Power On Reset (Active Low, see “User-Initiated Reset” on page 18) 26, 45, 55, 65 OVSS Output Ground 27, 36, 56 OVDD 1.8V Output Supply 32 D0N [NC] LVDS Bit 0 (LSB) Output Complement [NC in LVCMOS] DDR Logical Bits 1, 0 (LVDS) 33 D0P [D0] LVDS Bit 0 (LSB) Output True [LVCMOS Bit 0] DDR Logical Bits 1, 0 (LVDS or CMOS) 34 D1N [NC] LVDS Bit 1 Output Complement [NC in LVCMOS] NC in DDR 35 D1P [D1] LVDS Bit 1 Output True [LVCMOS Bit 1] NC in DDR 37 D2N [NC] LVDS Bit 2 Output Complement [NC in LVCMOS] DDR Logical Bits 3,2 (LVDS) 38 D2P [D2] LVDS Bit 2 Output True [LVCMOS Bit 2] DDR Logical Bits 3,2 (LVDS or CMOS) 39 D3N [NC] LVDS Bit 3 Output Complement [NC in LVCMOS] NC in DDR 40 D3P [D3] LVDS Bit 3 Output True [LVCMOS Bit 3] NC in DDR 41 D4N [NC] LVDS Bit 4 Output Complement [NC in LVCMOS] DDR Logical Bits 5,4 (LVDS) 42 D4P [D4] LVDS Bit 4 Output True [LVCMOS Bit 4] DDR Logical Bits 5,4 (LVDS or CMOS) 43 D5N [NC] LVDS Bit 5 Output Complement [NC in LVCMOS] NC in DDR 44 D5P [D5] LVDS Bit 5 Output True [LVCMOS Bit 5] NC in DDR 9 DDR MODE COMMENTS Analog Input Negative, Positive Common Mode Output Clock Divider Control FN6808.3 October 1, 2009 KAD5512HP Pin Descriptions - 72QFN (Continued) LVDS [LVCMOS] FUNCTION SDR MODE PIN NUMBER LVDS [LVCMOS] NAME DDR MODE COMMENTS 46 RLVDS 47 CLKOUTN [NC] LVDS Clock Output Complement [NC in LVCMOS] 48 CLKOUTP [CLKOUT] LVDS Clock Output True [LVCMOS CLKOUT] 49 D6N [NC] LVDS Bit 6 Output Complement [NC in LVCMOS] DDR Logical Bits 7,6 (LVDS) 50 D6P [D6] LVDS Bit 6 Output True [LVCMOS Bit 6] DDR Logical Bits 7,6 (LVDS or CMOS) 51 D7N [NC] LVDS Bit 7 Output Complement [NC in LVCMOS] NC in DDR 52 D7P [D7] LVDS Bit 7 Output True [LVCMOS Bit 7] NC in DDR 53 D8N [NC] LVDS Bit 8 Output Complement [NC in LVCMOS] DDR Logical Bits 9, 8 (LVDS) 54 D8P [D8] LVDS Bit 8 Output True [LVCMOS Bit 8] DDR Logical Bits 9, 8 (LVDS or CMOS) 57 D9N [NC] LVDS Bit 9 Output Complement [NC in LVCMOS] NC in DDR 58 D9P [D9] LVDS Bit 9 Output True [LVCMOS Bit 9] NC in DDR 59 D10N [NC] LVDS Bit 10 Output Complement [NC in LVCMOS] DDR Logical Bits 11, 10 (LVDS) 60 D10P [D10] LVDS Bit 10 Output True [LVCMOS Bit 10] DDR Logical Bits 11, 10 (LVDS or CMOS) 61 D11N [NC] LVDS Bit 11 Output Complement [NC in LVCMOS] NC in DDR 62 D11P [D11] LVDS Bit 11 Output True [LVCMOS Bit 11] NC in DDR 63 ORN [NC] LVDS Over Range Complement [NC in LVCMOS] 64 ORP [OR] LVDS Over Range True [LVCMOS Over Range] 66 SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output 70 OUTFMT Exposed Paddle AVSS LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor) Output Data Format (Two’s Comp., Gray Code, Offset Binary) Analog Ground NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection), SDR is the default state at power-up for the 72pin package 10 FN6808.3 October 1, 2009 KAD5512HP Pinout AVSS AVDD OUTFMT SDIO SCLK CSB SDO OVSS ORP ORN D11P D11N D10P D10N D9P D9N OVDD OVSS KAD5512HP (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD 1 54 D8P DNC 2 53 D8N DNC 3 52 D7P DNC 4 51 D7N DNC 5 50 D6P AVDD 6 49 D6N AVSS 7 48 CLKOUTP AVSS 8 47 CLKOUTN VINN 9 46 RLVDS VINP 10 45 OVSS AVSS 11 44 D5P AVDD 12 43 D5N DNC 13 42 D4P DNC 14 41 D4N VCM 15 40 D3P CLKDIV 16 39 D3N DNC 17 DNC 18 38 D2P Connect Thermal Pad to AVSS 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CLKN OUTMODE NAPSLP AVDD RESETN OVSS OVDD DNC DNC DNC DNC D0N D0P D1N D1P OVDD AVDD 19 CLKP 37 D2N 11 FN6808.3 October 1, 2009 KAD5512HP Pin Descriptions - 48QFN PIN NUMBER LVDS [LVCMOS] NAME 1, 9, 13, 17, 47 AVDD 1.8V Analog Supply 2-4, 11, 21, 22 DNC Do Not Connect 5, 8, 12, 48 AVSS Analog Ground 6, 7 VINN, VINP 10 VCM 14, 15 CLKP, CLKN 16 NAPSLP Power Control (Nap, Sleep modes) 18 RESETN Power On Reset (Active Low, see “User-Initiated Reset” on page 18) 19, 29, 42 OVSS Output Ground 20, 37 OVDD 1.8V Output Supply 23 D0N [NC] LVDS DDR Logical Bits 1, 0 Output Complement [NC in LVCMOS] 24 D0P [D0] LVDS DDR Logical Bits 1, 0 Output True [CMOS DDR Logical Bits 1, 0 in LVCMOS] 25 D1N [NC] LVDS DDR Logical Bits 3, 2 Output Complement [NC in LVCMOS] 26 D1P [D1] LVDS DDR Logical Bits 3, 2 Output True [CMOS DDR Logical Bits 3, 2 in LVCMOS] 27 D2N [NC] LVDS DDR Logical Bits 5, 4 Output Complement [NC in LVCMOS] 28 D2P [D2] LVDS DDR Logical Bits 5, 4 Output True [CMOS DDR Logical Bits 5, 4 in LVCMOS] 30 RLVDS 31 CLKOUTN [NC] LVDS Clock Output Complement [NC in LVCMOS] 32 CLKOUTP [CLKOUT] LVDS Clock Output True [LVCMOS CLKOUT] 33 D3N [NC] LVDS DDR Logical Bits 7, 6 Output Complement [NC in LVCMOS] 34 D3P [D3] LVDS DDR Logical Bits 7, 6 Output True [CMOS DDR Logical Bits 7, 6 in LVCMOS] 35 D4N [NC] LVDS DDR Logical Bits 9, 8 Output Complement [NC in LVCMOS] 36 D4P [D4] LVDS DDR Logical Bits 9, 8 Output True [CMOS DDR Logical Bits 9, 8 in LVCMOS] 38 D5N [NC] LVDS DDR Logical Bits 11, 10 Output Complement [NC in LVCMOS] 39 D5P [D5] LVDS DDR Logical Bits 11, 10 Output True [CMOS DDR Logical Bits 11, 10 in LVCMOS] 40 ORN [NC] LVDS Over Range Complement [NC in LVCMOS] 41 ORP [OR] LVDS Over Range True [LVCMOS Over Range] 12 LVDS [LVCMOS] FUNCTION Analog Input Negative, Positive Common Mode Output Clock Input True, Complement LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor) FN6808.3 October 1, 2009 KAD5512HP Pin Descriptions - 48QFN (Continued) PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 43 SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) 44 CSB SPI Chip Select (active low) 45 SCLK SPI Clock 46 SDIO SPI Serial Data Input/Output Exposed Paddle AVSS Analog Ground NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection) Pinout AVSS AVDD SDIO SCLK CSB SDO OVSS ORP ORN D5P D5N OVDD KAD5512HP (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 AVDD 1 36 D4P DNC 2 35 D4N DNC 3 34 D3P DNC 4 33 D3N AVSS 5 32 CLKOUTP VINN 6 31 CLKOUTN VINP 7 30 RLVDS AVSS 8 29 OVSS AVDD 9 28 D2P VCM 10 27 D2N DNC 11 AVSS 12 13 Connect Thermal Pad to AVSS 26 D1P 13 14 15 16 17 18 19 20 21 22 23 24 AVDD CLKP CLKN NAPSLP AVDD RESETN OVSS OVDD DNC DNC D0N D0P 25 D1N FN6808.3 October 1, 2009 KAD5512HP Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). -50 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 90 SFDR @ 250MSPS 85 80 SFDR @ 125MSPS 75 SNR @ 125MSPS 70 65 60 SNR @ 250MSPS 55 50 0M 200M 400M 600M 800M HD3 @ 250MSPS -55 HD3 @ 125MSPS -60 -65 -70 -75 -80 HD2 @ 250MSPS -85 HD2 @ 125MSPS -90 -95 -100 0M 1G 200M INPUT FREQUENCY (Hz) -20 90 -30 SNR AND SFDR HD2 AND HD3 MAGNITUDE 100 SFDRFS (dBFS) 70 60 SNRFS (dBFS) 50 SFDR (dBc) 40 SNR (dBc) 30 20 -60 -20 -10 0 HD3 (dBFS) -60 -50 -40 -30 -20 INPUT AMPLITUDE (dBFS) FIGURE 6. HD2 AND HD3 vs AIN FIGURE 5. SNR AND SFDR vs AIN 95 -60 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 0 -90 -100 INPUT AMPLITUDE (dBFS) 90 SFDR 85 80 75 SNR 70 65 60 40 -10 HD2 (dBFS) -80 -110 -30 HD3 (dBc) -70 -120 -40 HD2 (dBc) -50 0 -50 1G -40 10 -60 800M FIGURE 4. HD2 AND HD3 vs fIN FIGURE 3. SNR AND SFDR vs fIN 80 400M 600M INPUT FREQUENCY (Hz) 70 100 130 160 190 220 SAMPLE RATE (MSPS) FIGURE 7. SNR AND SFDR vs fSAMPLE 14 250 -70 HD3 -80 -90 HD2 -100 -110 -120 40 70 100 130 160 190 220 250 SAMPLE RATE (MSPS) FIGURE 8. HD2 AND HD3 vs fSAMPLE FN6808.3 October 1, 2009 KAD5512HP Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) 450 0.5 0.4 0.3 SDR 350 0.2 DNL (LSBs) TOTAL POWER (mW) 400 DDR 300 250 0.1 0.0 -0.1 -0.2 200 -0.3 150 -0.4 100 40 70 100 130 160 190 220 -0.5 250 0 512 1024 1536 SAMPLE RATE (MSPS) 1.0 SNR (dBFS) AND SFDR (dBc) 0.6 0.4 INL (LSBs) 3072 3584 4096 90 0.8 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 512 1024 1536 2048 2560 3072 3584 85 SFDR 80 75 70 SNR 65 60 55 50 300 4096 400 CODE FIGURE 11. INTEGRAL NONLINEARITY 0 800 Ain = -1.0 dBFS SNR = 68.2 dBFS SFDR = 91.9 dBc SINAD = 68.2 dBFS -20 AMPLITUDE (dBFS) 600000 450000 300000 150000 0 2050 500 600 700 INPUT COMMON MODE (mV) FIGURE 12. SNR AND SFDR vs VCM 750000 NUMBER OF HITS 2560 FIGURE 10. DIFFERENTIAL NONLINEARITY FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS MODE -1.0 2048 CODE -40 -60 -80 -100 -120 2051 2052 2053 CODE 2054 FIGURE 13. NOISE HISTOGRAM 15 2055 2056 0M 20M 40M 60M 80M FREQUENCY (Hz) 100M 120M FIGURE 14. SINGLE-TONE SPECTRUM @ 10MHz FN6808.3 October 1, 2009 KAD5512HP Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) 0 Ain = -1.0dBFS SNR = 68.0dBFS -20 SFDR = 82.6dBc SINAD = 67.8dBFS -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 -40 -60 -80 Ain = -1.0dBFS SNR = 67.3dBFS SFDR = 77.2dBc SINAD = 66.8dBFS -40 -60 -80 -100 -100 -120 0M 20M 40M 60M 80M 100M -120 120M 0M 20M 40M 0 120M -40 -60 -80 Ain = -1.0dBFS SNR = 59.9dBFS SFDR = 47.0dBc SINAD = 47.4dBFS -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 100M 0 Ain = -1.0dBFS SNR = 64.5dBFS SFDR = 69.2dBc SINAD = 63.4dBFS -20 -100 -40 -60 -80 -100 -120 0M 20M 40M 60M 80M FREQUENCY (Hz) 100M -120 0M 120M FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz 0 IMD = -89.0dBFS AMPLITUDE (dBFS) -20 -40 -60 -80 20M 40M 60M 80M FREQUENCY (Hz) 100M 120M FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz 0 AMPLITUDE (dBFS) 80M FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz FIGURE 15. SINGLE-TONE SPECTRUM @ 105MHz IMD = -91.4dBFS -20 -40 -60 -80 -100 -100 -120 60M FREQUENCY (Hz) FREQUENCY (Hz) 0M 20M 40M 60M 80M FREQUENCY (Hz) 100M FIGURE 19. TWO-TONE SPECTRUM @ 70MHz 16 120M -120 0M 20M 40M 60M 80M FREQUENCY (Hz) 100M 120M FIGURE 20. TWO-TONE SPECTRUM @ 170MHz FN6808.3 October 1, 2009 KAD5512HP Theory of Operation Functional Description The KAD5512HP is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 21). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. The converter pipeline requires six samples to produce a result. Digital error correction is also applied, resulting in a total latency of eight and one half clock cycles. This is evident to the user as a time lag between the start of a conversion and the data being available on the digital outputs. The KAD5512HP family offers 2.5dB improvement in SNR over the KAD5512P by simultaneously sampling the input signal with two ADC cores in parallel and summing the digital result. Since the input signal is correlated between the two cores and noise is not, an increase in SNR is achieved. As a result of this architecture, indexed SPI operations must be executed on each core in series. Refer to “Indexed Device Configuration/Control” on page 24 for more details. Power-On Calibration ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: • A frequency-stable conversion clock must be applied to the CLKP/CLKN pins • DNC pins (especially 3, 4 and 18) must not be pulled up or down • SDO (pin 66) must be high • RESETN (pin 25) must begin low • SPI communications must not be attempted A user-initiated reset can subsequently be invoked in the event that the previous conditions cannot be met at power-up. The SDO pin requires an external 4.7kΩ pull-up to OVDD. If the SDO pin is pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is required, the RESETN pin should be connected to an open-drain driver with a drive strength of less than 0.5mA. The ADC performs a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage CLOCK GENERATION INP SHA 2.5-BIT FLASH 6-STAGE 1.5-BIT/STAGE 3-STAGE 1-BIT/STAGE 3-BIT FLASH INN 1.25V + – DIGITAL ERROR CORRECTION LVDS/LVCMOS OUTPUTS FIGURE 21. ADC CORE BLOCK DIAGRAM 17 FN6808.3 October 1, 2009 KAD5512HP While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms. CLKN CLKP +25°C, and +85°C. Each plot shows the variation of SNR/SFDR across temperature after a single calibration at -40°C, +25°C and +85°C. Best performance is typically achieved by calibration at the operating conditions as stated earlier but it can be seen that performance drift with temperature is not a very strong function of the temperature at which the calibration is performed. Full-rated performance will be achieved after power-up calibration regardless of the operating conditions. 3 SNR CHANGE (dBfs) The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 22. The over-range output (OR) is set high once RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it is important that the analog input be within the converter’s full-scale range to observe the transition. If the input is in an over-range condition the OR pin will stay high, and it will not be possible to detect the end of the calibration cycle. CAL DONE AT +85°C 2 1 0 -1 -2 CALIBRATION TIME -3 -4 -40 RESETN CAL DONE AT +25°C CAL DONE AT -40°C -15 10 35 60 85 TEMPERATURE (°C) CALIBRATION BEGINS FIGURE 23. SNR PERFORMANCE vs TEMPERATURE ORP CALIBRATION COMPLETE 15 FIGURE 22. CALIBRATION TIMING User-Initiated Reset Recalibration of the ADC can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength of less than 0.5mA is recommended, RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512HP changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the ADC under the environmental conditions at which it will operate. SFDR CHANGE (dBc) CLKOUTP 10 CAL DONE AT -40°C 5 0 -5 CAL DONE AT +85°C -10 -15 -40 -15 10 35 TEMPERATURE (°C) CAL DONE AT +25°C 60 85 FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE Analog Input A single fully differential input (VINP/VINN) connects to the sample and hold amplifier (SHA) of each unit ADC. The ideal A supply voltage variation of <100mV will generally result in an SNR change of less than 0.5dBFS and SFDR change of less than 3dBc. In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 80MSPS will typically result in an SNR change of less than 0.5dBFS and an SFDR change of less than 3dBc. Figures 23 and 24 show the effect of temperature on SNR and SFDR performance with calibration performed at -40°C, 18 FN6808.3 October 1, 2009 KAD5512HP full-scale input voltage is 1.45V, centered at the VCM voltage of 0.535V as shown in Figure 25. transformer and low shunt resistance are recommended for optimal performance. Ω 348O 1.8 Ω 69.8O 1.4 1.0 Ω 25O Ω 100O INN INP 0.725V VCM 0.6 CM VCM 25O Ω Ω 69.8O Ω 49.9O 0.2 Ω 348O Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 26 through 28. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 26 and 27. ADT1-1WT 1000pF 0.1µF FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT FIGURE 25. ANALOG INPUT RANGE ADT1-1WT KAD5512HP Ω 100O 0.22µF 0.535V 217O Ω KAD5512HP VCM 0.1µF A differential amplifier, as shown in Figure 28, can be used in applications that require DC-coupling. In this configuration the amplifier will typically dominate the achievable SNR and distortion performance. Clock Input The clock input circuit is a differential pair (see Figure 42). Driving these inputs with a high level (up to 1.8VP-P on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The recommended drive circuit is shown in Figure 29. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC-coupling. Ω 1kO FIGURE 26. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS Ω 1kO AVDD 200pF TC4-1W ADTL1-12 ADTL1-12 1000pF 200pF 0.1µF 1000pF CLKP Ω 200O KAD5512HP 1000pF VCM CLKN 200pF FIGURE 27. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS This dual transformer scheme is used to improve commonmode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512HP is 500Ω. The SHA design uses a switched capacitor input stage (see Figure 41), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 19 FIGURE 29. RECOMMENDED CLOCK DRIVE A selectable 2x frequency divider is provided in series with the clock input. The divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate. This allows the use of the Phase Slip feature, which enables synchronization of multiple ADCs. TABLE 1. CLKDIV PIN SETTINGS CLKDIV PIN DIVIDE RATIO AVSS 2 Float 1 AVDD 4 FN6808.3 October 1, 2009 KAD5512HP The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline. If the frequency of the input clock changes, the DLL may take up to 52µs to regain lock at 250MSPS. The lock time is inversely proportional to the sample rate. The DLL has two ranges of operation, slow and fast. The slow range can be used for sample rates between 40MSPS and 100MSPS, while the default fast range can be used from 80MSPS to the maximum specified sample rate. Jitter In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 30. 1 SNR = 20 log 10 ⎛ --------------------⎞ ⎝ 2πf t ⎠ (EQ. 1) IN J Output data is available as a parallel bus in LVDS-compatible or CMOS modes. Additionally, the data can be presented in either double data rate (DDR) or single data rate (SDR) formats. The even numbered data output pins are active in DDR mode in the 72 pin package option. When CLKOUT is low the MSB and all odd logical bits are output, while on the high phase the LSB and all even logical bits are presented (this is true in both the 72 pin and 48 pin package options). Figures 1 and 2 show the timing relationships for LVDS/CMOS and DDR/SDR modes. The 48 Ld QFN package option contains six LVDS data output pin pairs, and therefore can only support DDR mode. Additionally, the drive current for LVDS mode can be set to a nominal 3mA or a power-saving 2mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the ADC. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 2. 100 95 tj = 0.1ps 90 14 BITS 85 SNR (dB) Digital Outputs 80 tj = 1ps 75 12 BITS 70 tj = 10ps 65 60 10 BITS TABLE 2. OUTMODE PIN SETTINGS OUTMODE PIN MODE AVSS LVCMOS Float LVDS, 3mA AVDD LVDS, 2mA tj = 100ps 55 50 1M 10M 100M INPUT FREQUENCY (Hz) 1G FIGURE 30. SNR vs CLOCK JITTER The output mode can also be controlled through the SPI port, which overrides the OUTMODE pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 1 on page 7. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR. An external resistor creates the bias for the LVDS drivers. A 10kΩ, 1% resistor must be connected from the RLVDS pin to OVSS. Voltage Reference Power Dissipation A temperature compensated voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The voltage reference is internally bypassed and is not accessible to the user. The power dissipated by the KAD5512HP is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation changes to a lesser degree in LVDS mode, but is more strongly related to the clock frequency in CMOS mode. 20 Over-Range Indicator The over-range (OR) bit is asserted when the output code reaches positive full-scale (e.g. 0xFFF in offset binary mode). The output code does not wrap around during an over-range condition. The OR bit is updated at the sample rate. FN6808.3 October 1, 2009 KAD5512HP Nap/Sleep Data Format Portions of the device may be shut down to save power during times when operation of the ADC is not required. Two power saving modes are available: Nap, and Sleep. Nap mode reduces power dissipation to less than 163mW and recovers to normal operation in approximately 1µs. Sleep mode reduces power dissipation to less than 6mW but requires approximately 1ms to recover from a sleep command. Output data can be presented in three formats: two’s complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4. Wake-up time from sleep mode is dependent on the state of CSB; in a typical application CSB would be held high during sleep, requiring a user to wait 150µs max after CSB is asserted (brought low) prior to writing ‘001x’ to SPI Register 25. The device would be fully powered up, in normal mode 1ms after this command is written. Wake-up from Sleep Mode Sequence (CSB high) • Pull CSB Low • Wait 150us • Write ‘001x’ to Register 25 • Wait 1ms until ADC fully powered on In an application where CSB was kept low in sleep mode, the 150µs CSB setup time is not required as the SPI registers are powered on when CSB is low, the chip power dissipation increases by ~ 15mW in this case. The 1ms wake-up time after the write of a ‘001x’ to register 25 still applies. It is generally recommended to keep CSB high in sleep mode to avoid any unintentional SPI activity on the ADC. All digital outputs (Data, CLKOUT and OR) are placed in a high impedance state during Nap or Sleep. The input clock should remain running and at a fixed frequency during Nap or Sleep, and CSB should be high. Recovery time from Nap mode will increase if the clock is stopped, since the internal DLL can take up to 52µs to regain lock at 250MSPS. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 3. TABLE 4. OUTFMT PIN SETTINGS OUTFMT PIN MODE AVSS Offset Binary Float Two’s Complement AVDD Gray Code The data format can also be controlled through the SPI port, which overrides the OUTFMT pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s complement coding simply complements the MSB of the offset binary representation. When calculating Gray code, the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 31 shows this operation. BINARY 11 10 9 •••• 1 0 •••• GRAY CODE 11 10 9 •••• 1 0 FIGURE 31. BINARY TO GRAY CODE CONVERSION Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 32. TABLE 3. NAPSLP PIN SETTINGS NAPSLP PIN MODE AVSS Normal Float Sleep AVDD Nap The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. 21 FN6808.3 October 1, 2009 KAD5512HP GRAY CODE 11 10 •••• 9 1 Serial Peripheral Interface 0 A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data input (SDI) and serial data input/output (SDIO). The maximum SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 16 for write operations and fSAMPLE divided by 66 for reads. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and 3.79MHz for read operations. There is no minimum SCLK rate. •••• The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results. •••• BINARY 11 10 •••• 9 1 0 FIGURE 32. GRAY CODE TO BINARY CONVERSION Mapping of the input voltage to the various data formats is shown in Table 5. TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING INPUT TWO’S VOLTAGE OFFSET BINARY COMPLEMENT GRAY CODE –Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00 –Full Scale 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01 + 1LSB Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00 +Full Scale – 1LSB 111 11 111 11 10 011 11 111 11 10 100 00 000 00 01 +Full Scale 111 11 111 11 11 011 11 111 111 1 100 00 000 00 00 CSB SCLK SDIO R/W W1 W0 A12 A11 A10 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 33. MSB-FIRST ADDRESSING CSB SCLK SDIO A0 A1 A2 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 FIGURE 34. LSB-FIRST ADDRESSING 22 FN6808.3 October 1, 2009 KAD5512HP tDSW CSB tDHW tS tCLK tHI tH tLO SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SPI WRITE FIGURE 35. SPI WRITE tDSW CSB tDHW tS tCLK tHI tH tDHR tDVR tLO SCLK WRITING A READ COMMAND SDIO R/W W1 W0 A12 A11 A10 A9 A2 READING DATA (3 WIRE MODE) A1 A0 D7 D6 SDO D3 D2 D1 D0 (4 WIRE MODE) D7 D3 D2 D1 D0 SPI READ FIGURE 36. SPI READ CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD 2 FIGURE 37. 2-BYTE TRANSFER LAST LEGAL CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD N FIGURE 38. N-BYTE TRANSFER SPI Physical Interface The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication 23 protocol (described in the following). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the KAD5512HP functioning as a slave. FN6808.3 October 1, 2009 KAD5512HP Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high-to-low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 33 and 34 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it’s decremented. In the default mode the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 6). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 35, and timing values are given in “Switching Specifications” on page 8. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the ADC (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer. TABLE 6. BYTE TRANSFER SELECTION [W1:W0] BYTES TRANSFERRED 00 1 01 2 10 3 11 4 or more Figures 37 and 38 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams. SPI Configuration ADDRESS 0X00: CHIP_PORT_CONFIG Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various microcontrollers. Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. ADDRESS 0X02: BURST_END If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data. Device Information ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers. Indexed Device Configuration/Control ADDRESS 0X10: DEVICE_INDEX_A A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command. It is important to note that only a single converter can be addressed at a time. This register defaults to 00h, indicating that no ADC is addressed. Error code ‘AD’ is returned if any indexed 24 FN6808.3 October 1, 2009 KAD5512HP register is read from without properly setting device_index_A. TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS ADDRESS 0X20: OFFSET_COARSE PARAMETER ADDRESS 0X21: OFFSET_FINE The input offset of each ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 7. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. TABLE 7. OFFSET ADJUSTMENTS PARAMETER 0x20[7:0] COARSE OFFSET 0x21[7:0] FINE OFFSET 0x23[7:0] MEDIUM GAIN 0x24[7:0] FINE GAIN Steps 256 256 –Full Scale (0x00) -2% -0.20% Mid–Scale (0x80) 0.00% 0.00% +Full Scale (0xFF) +2% +0.2% Nominal Step Size 0.016% 0.0016% ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to “Nap/Sleep” on page 21). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset. Steps 255 255 –Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV) Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB +Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV) VALUE 0x25[2:0] POWER-DOWN MODE Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV) 000 Pin Control 001 Normal Operation 010 Nap Mode 100 Sleep Mode TABLE 10. POWER-DOWN CONTROL ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Gain of the ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of ± 4.2%. (‘0011’ =~ -4.2% and ‘1100’ =~ +4.2%) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. TABLE 8. COARSE GAIN ADJUSTMENT 0x22[3:0] NOMINAL COARSE GAIN ADJUST (%) Bit3 +2.8 Bit2 +1.4 Bit1 -2.8 Bit0 -1.4 Global Device Configuration/Control ADDRESS 0X71: PHASE_SLIP When using the clock divider, it’s not possible to determine the synchronization of the incoming and divided clock phases. This is particularly important when multiple ADCs are used in a time-interleaved system. The phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle when in CLK/4 mode, as shown in Figure 39. Execution of a phase_slip command is accomplished by first writing a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to Bit 0 at address 71h (32 sclk cycles). CLK = CLKP – CLKN CLK 1.00ns CLK÷4 4.00ns CLK÷4 SLIP ONCE CLK÷4 SLIP TWICE FIGURE 39. PHASE SLIP: CLK÷4 MODE, fCLOCK = 1000MHz 25 FN6808.3 October 1, 2009 KAD5512HP ADDRESS 0X72: CLOCK_DIVIDE ADDRESS 0X74: OUTPUT_MODE_B The KAD5512HP has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “Clock Input Considerations” on page 31). This functionality can be overridden and controlled through the SPI, as shown in Table 11. This register is not changed by a Soft Reset. ADDRESS 0X75: CONFIG_STATUS TABLE 11. CLOCK DIVIDER SELECTION VALUE 0x72[2:0] CLOCK DIVIDER 000 Pin Control 001 Divide by 1 010 Divide by 2 100 Divide by 4 ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5512HP can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to “Digital Outputs” on page 20). This functionality can be overridden and controlled through the SPI, as shown in Table 12. Data can be coded in three possible formats: two’s complement, Gray code or offset binary. By default, the tri-level OUTFMT pin selects the data format (refer to “Data Format” on page 21). This functionality can be overridden and controlled through the SPI, as shown in Table 13. This register is not changed by a Soft Reset. TABLE 12. OUTPUT MODE CONTROL VALUE 0x93[7:5] OUTPUT MODE 000 Pin Control 001 LVDS 2mA 010 LVDS 3mA 100 LVCMOS Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. Bit 4 DDR Enable Setting this bit enables Double Data-Rate mode. Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 14 shows the allowable sample rate ranges for the slow and fast settings. TABLE 14. DLL RANGES DLL RANGE MIN MAX UNIT Slow 40 100 MSPS Fast 80 fS MAX MSPS The output_mode_B and config_status registers are used in conjunction to enable DDR mode and select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers. READ OUTPUT_MODE_B 0x74 READ CONFIG_STATUS 0x75 WRITE TO 0x74 DESIRED VALUE FIGURE 40. SETTING OUTPUT_MODE_B REGISTER The procedure for setting output_mode_B is shown in Figure 40. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register. TABLE 13. OUTPUT FORMAT CONTROL VALUE 0x93[2:0] OUTPUT FORMAT 000 Pin Control 001 Two’s Complement 010 Gray Code 100 Offset Binary 26 FN6808.3 October 1, 2009 KAD5512HP Device Test TABLE 15. OUTPUT TEST MODES The KAD5512HP can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 15) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to Table 16. VALUE 0xC0[3:0] OUTPUT TEST MODE 0000 Off 0001 WORD 1 WORD 2 Midscale 0x8000 N/A 0010 Positive Full-Scale 0xFFFF N/A 0011 Negative Full-Scale 0x0000 N/A 0100 Checkerboard 0xAAAA 0x5555 0101 Reserved N/A N/A 0110 Reserved N/A N/A 0111 One/Zero 0xFFFF 0x0000 1000 User Pattern user_patt1 user_patt2 ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined test word. ADDRESS 0XC4: USER_PATT2_LSB ADDRESS 0XC5: USER_PATT2_MSB These registers define the lower and upper eight bits, respectively, of the second user-defined test word. 27 FN6808.3 October 1, 2009 KAD5512HP SPI Memory Map Indexed Device Config/Control Info SPI Config TABLE 16. SPI MEMORY MAP INDEXED/ GLOBAL 00h G 00h G Chip ID # Read only G Chip Version # Read only G 00h I Coarse Offset cal. value I Fine Offset cal. value I cal. value I Medium Gain cal. value I Fine Gain cal. value I 00h NOT affected by Soft Reset I 00h G PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 00 Port_Config SDO Active LSB First Soft Reset 01 Reserved Reserved 02 Burst_End Burst end address [7:0] 03-07 Reserved Reserved 08 Chip_Id 09 Chip_Version 10 Device_Index_A 11-1F Reserved Reserved 20 Offset_Coarse 21 Offset_Fine 22 Gain_Coarse 23 Gain_Medium 24 Gain_Fine 25 Modes 26-5F Reserved Reserved 60-6F Reserved Reserved 70 Reserved Reserved 71 Phase_Slip BIT 4 BIT 3 Reserved BIT 2 BIT 1 BIT 0 (LSB) Mirror (bit5) Mirror (bit6) Mirror (bit7) ADC01 Reserved ADC00 Coarse Gain Reserved Power-Down Mode [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep other codes = reserved Reserved 72 Global DeviceConfig/Control DEF. VALUE (Hex) ADDR (Hex) Next Clock Edge clock_divide Clock Divide [2:0] 000 = Pin Control 001 = Divide by 1 010 = Divide by 2 100 = Divide by 4 other codes = reserved 00h NOT affected by Soft Reset G Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved Output Format [2:0] 000 = Pin Control 001 = Twos Complement 010 = Gray Code 100 = Offset Binary other codes = reserved 00h NOT affected by Soft Reset G 73 Output_Mode_A 74 Output_Mode_B DLL Range 0 = fast 1 = slow DDR Enable (Note 13) 00h NOT affected by Soft Reset G 75 Config_Status XOR Result XOR Result Read Only G 76-BF Reserved Reserved 28 FN6808.3 October 1, 2009 KAD5512HP Device Test TABLE 16. SPI MEMORY MAP (Continued) ADDR (Hex) PARAMETER NAME C0 Test_io BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 0 (LSB) BIT 1 Output Test Mode [3:0] User Test Mode [1:0] 00 = Single 01 = Alternate 10 = Reserved 11 = Reserved 0 = Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved DEF. VALUE (Hex) INDEXED/ GLOBAL 00h G 00h G 7 = One/Zero Word Toggle 8 = User Input 9-15 = reserved C1 Reserved Reserved C2 User_Patt 1_LSB B7 B6 B5 B4 B3 B2 B1 B0 00h G C3 User_Patt1_MSB B15 B14 B13 B12 B11 B10 B9 B8 00h G C4 User_Patt 2_LSB B7 B6 B5 B4 B3 B2 B1 B0 00h G C5 User_Patt2_MSB B15 B14 B13 B12 B11 B10 B9 B8 00h G C6-FF Reserved Reserved NOTE: 13. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up. Equivalent Circuits AVDD TO CLOCKPHASE GENERATION AVDD CLKP AVDD CSAMP 1.6pF INP Ω 1000O Φ2 F Φ1 F CSAMP 1.6pF AVDD INN Φ2 F Φ F1 FIGURE 41. ANALOG INPUTS 29 TO CHARGE PIPELINE Φ F3 TO CHARGE PIPELINE Φ3 F AVDD 11kO Ω AVDD 11kO Ω Ω 18kO Ω 18kO CLKN FIGURE 42. CLOCK INPUTS FN6808.3 October 1, 2009 KAD5512HP Equivalent Circuits (Continued) AVDD AVDD (20k PULL-UP ON RESETN ONLY) AVDD Ω 75kO AVDD Ω 75kO OVDD TO SENSE LOGIC Ω 280O OVDD OVDD 20kΩ INPUT INPUT Ω 75kO Ω 75kO TO LOGIC 280Ω FIGURE 43. TRI-LEVEL DIGITAL INPUTS FIGURE 44. DIGITAL INPUTS OVDD 2mA OR 3mA OVDD DATA DATA D[11:0]P OVDD OVDD D[11:0]N OVDD DATA DATA DATA D[11:0] 2mA OR 3mA FIGURE 46. CMOS OUTPUTS FIGURE 45. LVDS OUTPUTS AVDD VCM 0.535V + – FIGURE 47. VCM_OUT OUTPUT 72 Pin/48 Pin Package Options The KAD5512HP is available in both 72 pin and 48 pin packages. The 48 pin package option supports LVDS DDR only. A reduced set of pin selectable functions are available in the 48 pin package due to the reduced pinout; (OUTMODE, OUTFMT, and CLKDIV pins are not available). Table 17 shows the default state for these functions for the 48 pin package. Note that these functions are available through the SPI, allowing a user to set these modes as they desire, offering the same flexibility as the 72 pin package 30 option. DC and AC performance of the ADC is equivalent for both package options. . TABLE 17. 48 PIN SPI - ADDRESSABLE FUNCTIONS FUNCTION DESCRIPTION DEFAULT STATE CLKDIV Clock Divider Divide by 1 OUTMODE Output Driver Mode LVDS, 3mA (DDR) OUTFMT Data Coding Two’s Complement FN6808.3 October 1, 2009 KAD5512HP ADC Evaluation Platform Definitions Intersil offers an ADC Evaluation platform which can be used to evaluate any of the KADxxxxx ADC family. The platform consists of a FPGA based data capture motherboard and a family of ADC daughtercards. This USB based platform allows a user to quickly evaluate the ADC’s performance at a user’s specific application frequency requirements. More information is available at http://www.intersil.com/converters/adc_eval_platform/ Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Layout Considerations Aperture Jitter is the RMS variation in aperture delay for a set of samples. Split Ground and Power Planes Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Clock Input Considerations Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. LVDS Outputs Output traces and connections must be designed for 50Ω (100Ω differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces. LVCMOS Outputs Output traces and connections must be designed for 50Ω characteristic impedance. Unused Inputs Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. 31 Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 LSB. It is typically expressed in percent. Integral Non-Linearity (INL) is the maximum deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. FN6808.3 October 1, 2009 KAD5512HP SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter’s full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic. Revision History DATE REVISION 7/30/08 Rev 1 CHANGE Initial Release of Production Datasheet 10/29/08 FN6808.0 Converted to intersil template. Assigned file number FN6808. Rev 0 - first release (as preliminary datasheet) with new file number. 12/5/08 FN6808.0 Applied Intersil Standards 1/13/09 FN6808.1 P1; revised Key Specs. Features - 1st bullet; changed 2.5dB to 2.2dB P2; added Part Marking column to Order Info P4; Moved Thermal Impedance under Thermal Info (used to be on p. 8). Added Theta JA Note 3. P4-6; edits throughout the Elec Specs table. Revised Note 6. P6; Revised Digital Specs table (added VIH, VIL specs) P8; added Notes 9-10 to Switching Specs table. Removed ESD section P13-15; revised Performance Curves throughout P16; Functional Description section; revised 6th sentence of 1st paragraph P17; User Initiated Reset section; revised 2nd sentence of 1st paragraph P20; SPI section; revised 4th sentence of 1st paragraph P22; SPI Physical Interface; revised 2nd sentence of 4th paragraph P23; added last 2 sentences to 1st paragraph of "ADDRESS 0X24: GAIN_FINE". Revised Table 8 P24; revised last 2 sentence of "ADDRESS 0X71: PHASE_SLIP". Removed Figure of "PHASE SLIP: CLK÷2 MODE, fCLOCK = 500MHz" P27; revised Figure 45, Table 17; revised Bits7:4, Addr C0 Throughout; formatted graphics to Intersil standards 2/25/09 FN6808.2 Changed “odd” bits N in Figure 1A - DDR to “even” bits N, Replaced POD L48.7x7E due to changed dimension from “9.80 sq” to “6.80” sq. in land pattern 5/29/09 FN6808.3 1) Added nap mode, sleep mode wake up times to spec table 2) Added CSB, SCLK Setup time specs for nap, sleep modes 3) Added section showing 72pin/48pin package feature differences and default state for clkdiv, outmode, outfmt page 30 4) Changed SPI setup time specs wording in spec table 5) Added ‘Reserved’ to SPI memory map at address 25H 6) Renumbered Notes 7) Added test platform link on page 31 8) Added DDR enable Note 13 for 48 pin/72 pin options 9) Changed pin description table for 72/48 pin option, added DDR notes 10) Changed multi device note in SPI physical interface section to show 3-wire application.page 23 11) Updated digital output section for DDR operation page 20 12) Change to Figures 23 and 24 and description in text 13) Added connect note for thermal pad 14) Formatted Figures 25 and 26 with Intersil Standards, 15) Added Pb-free reflow link, Over-temp reference in Min and Max and Note 08/19/09 9/3/09 16) Updated sleep mode Power spec 17) Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs. 18) Updated SPI timing diagrams, Figures 35, 36 19) Updated wakeup time description in “Nap/Sleep” on page 21. 20) Removed calibration note in spec table 21) Updated cal paragraph in user initiated reset section per DC. 22) Removed “ADDRESS 0X70: SKEW_DIFF” and associated Table 11 from page 25. 23) Modified Note 4 from: "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." to: "Parameters with Min and/or MAX limits are 100% production tested at their worst case temperature extreme ( +85C)." 24) Removed reference to Note 7 in digital and switching specification table headers (Note 7 reads "The DLL Range setting must be changed for low speed operation. See Table 14 on page 26." All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 FN6808.3 October 1, 2009 KAD5512HP Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09 7.00 PIN 1 INDEX AREA PIN 1 INDEX AREA 4X 5.50 A 6 B 37 6 48 1 36 44X 0.50 Exp. DAP 5.60 Sq. 7.00 (4X) 12 25 0.15 24 13 48X 0.25 48X 0.40 TOP VIEW 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 Max C 0.10 C 0.08 C SEATING PLANE SIDE VIEW 44X 0.50 6.80 Sq C 0 . 2 REF 5 48X 0.25 5.60 Sq 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" 48X 0.60 TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 33 FN6808.3 October 1, 2009 KAD5512HP Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 A 4X 8.50 PIN 1 INDEX AREA B 55 6 72 1 54 68X 0.50 Exp. DAP 6.00 Sq. 10.00 18 37 (4X) PIN 1 INDEX AREA 6 0.15 36 19 72X 0.24 72X 0.40 TOP VIEW 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 Max C 0.10 C 0.08 C SEATING PLANE 68X 0.50 SIDE VIEW 72X 0.24 9.80 Sq 6.00 Sq C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. 72X 0.60 DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 34 FN6808.3 October 1, 2009