MC74HC174A D

MC74HC174A
Hex D Flip-Flop with
Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active−low.
•
•
•
MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
16
Features
•
•
•
•
•
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Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 162 FETs or 40.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
MC74HC174AN
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
16
1
HC174AG
AWLYWW
1
16
HC
174A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
16
1
1
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 12
1
Publication Order Number:
MC74HC174A/D
MC74HC174A
3
2
4
5
D2
D3
6
7
11
10
13
12
14
15
D0
RESET
1
16
VCC
Q0
2
15
Q5
D0
3
14
D5
D1
4
13
D4
D4
D5
Q1
5
12
Q4
D2
6
11
D3
Q2
7
10
Q3
GND
8
9
D1
DATA
INPUTS
CLOCK
CLOCK
9
RESET
1
Figure 1. Pin Assignment
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
Q4
Q5
PIN 16 = VCC
PIN 8 = GND
Figure 2. Logic Diagram
FUNCTION TABLE
DESIGN/VALUE TABLE
Inputs
Output
Design Criteria
Value
Units
Reset
Clock
D
Q
Internal Gate Count*
40.5
ea.
L
X
X
L
Internal Gate Propagation Delay
1.5
ns
H
H
H
Internal Gate Power Dissipation
5.0
mW
H
L
L
Speed Power Product
0.0075
pJ
X
No Change
X
No Change
H
L
H
*Equivalent to a two−input NAND gate.
ORDERING INFORMATION
Package
Shipping†
MC74HC174ANG
PDIP−16
(Pb−Free)
500 Units / Rail
MC74HC174ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC174ADR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HC174ADTR2G
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
NLV74HC174ADG*
SOIC−16
(Pb−Free)
55 Units / Rail
NLV74HC174ADR2G*
SOIC−16
(Pb−Free)
2500 / Tape & Reel
NLV74HC174ADTR2G*
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
NLV74HC174ANG*
PDIP−16
(Pb−Free)
25 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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2
MC74HC174A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
(Referenced to GND)
*0.5 to )7.0
V
VIN
DC Input Voltage
(Referenced to GND)
*1.5 to VCC )1.5
V
(Referenced to GND) (Note 1)
*0.5 to VCC )0.5
V
VOUT
IIN
DC Output Voltage
DC Input Current, per Pin
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$50
mA
*65 to )150
_C
260
_C
)150
_C
TSTG
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PDIP
SOIC
TSSOP
78
112
148
_C/W
PD
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILATCHUP
Level 1
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Latchup Performance
PDIP, SOIC, TSSOP
UL 94 V−0 @ 0.125 in.
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u100
u500
V
Above VCC and Below GND at 85_C (Note 5)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
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Symbol
Parameter
VCC
DC Supply Voltage
VIN,
VOUT
DC Input Voltage, Output Voltage
TA
Operating Temperature, All Package Types
tr, tf
CLOCK Input Rise and Fall Time (Figure 4)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
*55
)125
_C
0
0
0
0
1000
700
500
400
ns
(Referenced to GND)
(Referenced to GND) (Note 6)
VCC = 2.0 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6.0 V
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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3
MC74HC174A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
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Symbol
Parameter
Test Conditions
V
*55_C to 25_C
v85_C
v125_C
Unit
VIH
Minimum High−Level Input
Voltage
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| v 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| v 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
VIN = VIH or VIL
|IOUT| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN = VIH or VIL
|IOUT| v 4.0 mA
|IOUT| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VIN = VIH or VIL
|IOUT| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN = VIH or VIL
|IOUT| v 4.0 mA
|IOUT| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOL
Maximum Low−Level Output
Voltage
V
IIN
Maximum Input Leakage Current
VIN = VCC or GND
6.0
$0.1
$1.0
$1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
VIN = VCC or GND
IOUT = 0 mA
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
Guaranteed Limit
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
V
*55_C to 25_C
v85_C
v125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 4 and 7)
Parameter
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 5 and 7)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tPLH
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 7)
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 4 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Typical @ 25_C, VCC = 5.0 V
CPD
Power Dissipation Capacitance, per Enabled Output
(Note 7)
7. Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
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4
62
pF
MC74HC174A
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
*55_C to 25_C
v85_C
v125_C
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Symbol
Parameter
Figure
V
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
6
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Data
6
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec
Minimum Recovery Time,
Reset Inactive to Clock
5
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
4
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tw
Minimum Pulse Width, Reset
5
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Rise and Fall Times
4
2.0
4.5
6.0
tr, tf
CLOCK
9
D0
3
RESET
1
D1
4
D2
6
D3
11
1000
500
400
C
D
Q
D4
D5
Q
Q
Q
D
Q
D
Q
R
Figure 3. Expanded Logic Diagram
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5
Q2
10
Q3
12
Q4
R
C
14
7
R
C
13
Q1
R
C
D
5
R
C
D
Q0
R
C
D
2
1000
500
400
15
Q5
1000
500
400
ns
MC74HC174A
tr
CLOCK
tf
VCC
90%
50%
10%
tw
GND
GND
tPHL
tPLH
tPHL
Q
90%
50%
10%
trec
tTLH
50%
CLOCK
tTHL
Figure 4. Switching Waveform
Figure 5. Switching Waveform
TEST POINT
VALID
VCC
DATA
VCC
50%
1/fmax
Q
tw
RESET
OUTPUT
50%
tsu
th
DEVICE
UNDER
TEST
GND
CL *
VCC
CLOCK
50%
GND
*Includes all probe and jig capacitance
Figure 6. Switching Waveform
Figure 7. Test Circuit
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6
VCC
GND
MC74HC174A
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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7
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC74HC174A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74HC174A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC174A
ON Semiconductor and
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MC74HC174A/D