NCP81074 D

NCP81074A, NCP81074B
Single Channel 10A High
Speed Low-Side MOSFET
Driver
The NCP81074 is a single channel, low−side MOSFET driver. It is
capable of providing large peak currents into capacitive loads. This
driver can deliver a 7 A peak current at the Miller plateau region to
help reduce the Miller effect during MOSFETs switching transitions.
It exhibits a split output configuration allowing the user to control the
turn on and turn off slew rates. This part is available in SOIC−8 and
DFN8 2x2 mm packages.
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MARKING
DIAGRAMS
DFN8
MN SUFFIX
CASE 506AA
Features
•
•
•
•
•
•
•
•
•
High Current Drive Capability ±10 A
TTL/CMOS Compatible Inputs Independent of Supply Voltage
High Reverse Current Capability (10 A) Peak
4 ns Typical Rise and 4 ns Typical Fall Times with 1.8 nF Load
Fast Propagation Delay Times of 15 ns with Input Falling and 15 ns
with Input Rising
Input Voltage Range from 4.5 V to 20 V
Split Output Configuration
Dual Input Design Offering Drive Flexibility
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•
•
•
•
•
•
•
•
Server Power
Telecommunication, Datacenter Power
Synchronous Rectifier
Switch Mode Power Supply
DC/DC Converter
Power Factor Correction
Motor Drive
Renewable Energy, Solar Inverter
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 3
1
XXMG
G
1
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
(Note: Microdot may be in either location)
8
8
1
XXXXXX
AYWW
G
SOIC−8
CASE 751
1
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
1
Publication Order Number:
NCP81074/D
NCP81074A, NCP81074B
ORDERING INFORMATION
Device
Temperature
Range (5C)
Marking
Input Type
Package Type
Shipping†
NCP81074AMNTBG
−40 to +140
CL
Fixed Digital Threshold
DFN8 2x2
(Pb−Free)
3000 / Tape & Reel
NCP81074BMNTBG
−40 to +140
CM
VDD Based Threshold
DFN8 2x2
(Pb−Free)
3000 / Tape & Reel
NCP81074ADR2G
−40 to +140
NCP81074A
Fixed Digital Threshold
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP81074BDR2G
−40 to +140
NCP81074B
VDD Based Threshold
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
Figure 1. NCP81074 Block Diagram
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2
NCP81074A, NCP81074B
PIN DESCRIPTION
Pin No.
Symbol
1
IN+
2
GND
Common ground. This ground should be connected very closely to the source of the power MOSFET.
3
GND
Common ground. This ground should be connected very closely to the source of the power MOSFET.
4
OUTL
Sink pin. Connect to Gate of MOSFET.
5
OUTH
Source Pin. Connect to Gate of MOSFET.
6
VDD
Power Supply Input Pin.
7
VDD
Power supply Input Pin.
IN−
Inverting Input which has logic compatible threshold and hysteresis. If not used, this pin should be connected to either VDD or GND. It should not be left unconnected
8
Description
Non−Inverting Input which has logic compatible threshold and hysteresis. If not used, this pin should be
connected to either VDD or GND. It should not be left unconnected.
Figure 2. TYPICAL APPLICATION CIRCUIT
ABSOLUTE MAXIMUM RATINGS
Value
Parameter
Supply Voltage
VDD
Output Current (DC)
Min
Max
Unit
−0.3
24
V
Iout_dc
0.6
Iout_pulse
10
A
Reverse Current (Pulse<1 ms)
10
Output Current (Pulse<0.5 ms)
Input Voltage
A
A
IN+, IN−
−6
24
V
Output Voltages
OUTH, OUTL
−0.3
VDD + 0.3
V
Output Voltages (Pulse<0.5 ms)
OUTH, OUTL
−3.0
VDD + 3.0
V
Junction Operation Temperature
TJ
−40
150
°C
Tstg
−65
Storage Temperature
Electrostatic Discharge
160
Human body model, HBM
4000
Charge device model, CDM
1000
OUT Latch−up Protection
500
Moisture Sensitivity Level (MSL)
V
mA
MSL1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCP81074A, NCP81074B
RECOMMENDED OPERATING CONDITIONS
Rating
Unit
VDD supply Voltage
Parameter
4.5 to 20
V
IN+, IN− input voltages
−5 to 20
V
−40 to +140
°C
Junction Temperature Range
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 1. THERMAL INFORMATION
Package
Theta JA (5C/W)
Theta JC (5C/W)
DFN−8 2x2
80.3
11.9
SOIC−8
115
50
Table 2. ELECTRICAL CHARACTERISTICS (Note 1) (Typical values: VDD =12V, 1uF from VDD to GND,TA = TJ =
−405C to 1405C, typical at TAMB = 255C, unless otherwise specified)
Parameter
SYMBOL
Test Conditions
MIN
TYP
MAX
Unit
VDD Under Voltage Lockout (rising)
VCCR
VDD rising
3.7
3.9
4.1
V
VDD Under Voltage Lockout (Falling)
VCCF
VDD falling
3.4
3.6
3.8
V
VDD Under Voltage Lockout (hysteresis)
VCCH
300
IDD
1.2
SUPPLY VOLTAGE
Operating Current (no switching)
VDD Under Voltage Lockout to Output
Delay (Note 1)
VDD rising
mV
2
mA
ms
10
INPUTS
NCP81074A High Threshold
NCP81074A Low Threshold
VIN_HYS
VthH
Input rising from logic low
1.9
2.1
2.3
V
VthL
Input falling from logic high
1.1
1.3
1.5
V
Input Signal
Hysteresis
0.8
V
NCP81074B High Threshold
VthH
Input rising from logic low
(VDD = 8 V to 12 V)
VDD
−3.5
VDD
−3.1
VDD
−2.7
V
NCP81074B Low Threshold
VthL
Input falling from logic high
(VDD = 8 V to 12 V)
GND
+2.6
GND
+2.9
GND
+3.2
V
IN− Pull−up Resistor
Rin−
200
kW
IN+ Pull−Down Resistor
Rin+
200
kW
OUTPUTS
Output Resistance High
ROH
IOUT = −10 mA
0.4
0.8
W
Output Resistance Low
ROL
IOUT = +10 mA
0.4
0.8
W
Peak Source Current(2)
ISource
OUT = GND
200 ns Pulse
10
A
Miller Plateau Source Current(2)
ISource
OUT = 5.0 V
200 ns Pulse
7
A
Peak Sink Current(2)
ISink
OUT = VDD
200 ns Pulse
10
A
Miller Plateau Sink Current(2)
ISink
OUT = 5.0 V
200 ns Pulse
7
A
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4
NCP81074A, NCP81074B
Table 2. ELECTRICAL CHARACTERISTICS (Note 1) (Typical values: VDD =12V, 1uF from VDD to GND,TA = TJ =
−405C to 1405C, typical at TAMB = 255C, unless otherwise specified)
Parameter
SYMBOL
Test Conditions
Propagation Delay Time Low to High, IN
Rising (IN to OUT) (Note 2)
td1
Propagation Delay Time High to Low, IN
Falling (IN to OUT) (Note 2)
MIN
TYP
MAX
Unit
CLoad = 1.8 nF
15
27
ns
td2
CLoad = 1.8 nF
15
27
ns
Rise Time (Note 2)
tr
CLoad = 1.8 nF
4
7
ns
Fall Time (Note 2)
tf
CLoad = 1.8 nF
4
7
ns
SWITCHING CHARACTERISTICS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All Limits are 100% tested at TAMB = 25 °C and guaranteed across temperature by design and statistical analysis.
2. Guaranteed by characterization. *See timing Waveforms.
Table 3. LOGIC TRUTH TABLE
IN+
IN−
OUTH
OUTL
OUT
(OUTH & OUTL CONNECTED
TOGETHER)
L
L
HIGH−Z
L
L
L
H
HIGH−Z
L
L
H
L
H
HIGH−Z
H
H
H
HIGH−Z
L
L
Figure 3. Non−inverting Input Driver Operation
Figure 4. Inverting Input Driver Operation
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5
NCP81074A, NCP81074B
TYPICAL CHARACTERISTICS
250
100
200
150
4.7 nF
100
2.2 nF
470 pF
50
1 nF
0
0
70
60
4.7 nF
50
40
30
2.2 nF
20
1 nF
10
0
470 pF
0
200 400 600 800 1000 1200 1400 1600 1800 2000
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
Figure 5. Supply Current vs. Switching
Frequency, VDD = 12 V
Figure 6. Supply Current vs. Switching
Frequency, VDD = 4.5 V
8.0
4.75
7.5
20 V
4.25
15 V
4.00
5V
3.75
10 V
RISE TIME (nS)
4.50
5V
6.5
15 V
6.0
10 V
5.5
5.0
3.25
4.5
3.00
−60 −40 −20
0
20
40
4.0
−60 −40 −20
80 100 120 140 160
60
20 V
7.0
3.50
0
20
40
60
80 100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Fall Time vs. Temperature
CLOAD = 1.8 nF
Figure 8. Rise Time vs. Temperature
Cload = 1.8 nF
18
16
17
15
16
14
TD2, DELAY TIME (nS)
FALL TIME (nS)
80
200 400 600 800 1000 1200 1400 1600 1800 2000
5.00
TD1, DELAY TIME (nS)
10 nF
90
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10 nF
15
14
13
CLOAD = 1 nF
CLOAD = 2.2 nF
CLOAD = 4.7 nF
CLOAD = 10 nF
12
11
13
12
11
10
CLOAD = 1 nF
CLOAD = 2.2 nF
CLOAD = 4.7 nF
CLOAD = 10 nF
9
8
10
7
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
VDD, SUPPLY VOLTAGE (V)
VDD, SUPPLY VOLTAGE (V)
Figure 9. Propagation Delay TD1 vs. Supply
Voltage
Figure 10. Propagation Delay TD2 vs. Supply
Voltage
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6
NCP81074A, NCP81074B
TYPICAL CHARACTERISTICS
200
200
180
2 MHz
160
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
180
140
120
100
80
1 MHz
60
40
140
120
100
80
60
40
20
0
20
0
4
6
8
12
10
14
16
18
4
20
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 11. Supply Current vs. Supply Voltage
CLOAD = 2.2 nF
Figure 12. Supply Current vs. Supply Voltage
CLOAD = 4.7 nF
20
16
Test Conditions:
TJ = 25°C
1 ms Positive Pulse
Fsw = 1 kHz
12
10
8
6
4
16
14
12
10
8
6
4
2
2
0
−3.0
0
0
0.5
1.0
Test Conditions:
TJ = 25°C
1 ms Positive Pulse
Fsw = 1 kHz
18
OUTPUT CURRENT (A)
14
1.5
2.0
2.5
3.0
−2.5
−2.0
−1.5
−1.0
−0.5
OUT H − VDD (V)
OUT L (V)
Figure 13. Reverse Current, PMOS(on), PMOS(off)
Figure 14. Reverse Current, PMOS(off), PMOS(on)
1.6
IN+ = VDD
1.4
SUPPLY CURRENT (A)
OUTPUT CURRENT (A)
160
GND and VDD
1.2
IN− = VDD
1.0
0.8
0.6
0.4
0.2
0
0
5
10
15
20
SUPPLY VOLTAGE (V)
Figure 15. Supply Current vs. Supply Voltage
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7
25
0
NCP81074A, NCP81074B
BENCH WAVEFORMS − Non−Inverting Input
Figure 16. Rise Time with 1.8 nF Load
Figure 17. Fall Time with 1.8 nF Load
Figure 18. Propagation Delays with 1.8 nF Load
Figure 19. Propagation Delays with 1.8 nF Load
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8
NCP81074A, NCP81074B
BENCH WAVEFORMS − Inverting Input
Figure 20. Rise Time with 1.8 nF Load
Figure 21. Fall Time with 1.8 nF Load
Figure 22. Propagation Delays with 1.8 nF Load
Figure 23. Propagation Delays with 1.8 nF Load
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9
NCP81074A, NCP81074B
PCB LAYOUT RECOMMENDATION
Proper component placement is extremely important in
high current, fast switching applications to provide
appropriate device operation and design robustness. The
NCP81074 gate driver exhibits a powerful output stage
enabling large peak currents with fast rise and fall times.
Eventhough the NCP81074 provides a split output
configuration for slew rate control, a proper PCB layout is
crucial to ensure maximum performance. The following
circuit layout guidelines are strongly recommended when
designing with the NCP81074.
• Place the driver close to the power MOSFET in order to
have a low impedance path between the output pins and
the gate. Keep the traces short and wide to minimize the
parasitic inductance and accommodate for high peak
currents.
• Place the decoupling capacitor close to the gate drive
IC. Placing the VDD capacitor close to the pin and
ground improves noise filtering. This capacitor supplies
•
•
•
high peak currents during the turn−on transition of the
MOSFET. Using a low ESL chip capacitor is highly
recommended.
Keep a tight turn−on turn−off current loop paths to
minimize parastic inductance. High di/dt will induce
voltage spikes on the output pin and the MOSFET gate.
Parallel the source and return signals taking advantage
of flux cancellation.
Since the NCP81074 is a 2x2mm package driving high
peak currents into capacitive loads, adding a shielding
ground plane helps in power dissipation and noise
blocking. The ground plane should not be a current
carrying path to any of the current loops.
Any unused pin, should be pulled to either rail
depending on the functionality of the pin to avoid any
malfunction on the output. Please refer to the pin
description table for more information.
Figure 24.
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10
NCP81074A, NCP81074B
PACKAGE DIMENSIONS
DFN8 2x2
CASE 506AA
ISSUE E
D
PIN ONE
REFERENCE
0.15 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
ÇÇ
ÇÇ
0.15 C
2X
A
B
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
A1
C
SIDE VIEW
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
D2
1
8X
8X
L
1.30
4
0.50
PACKAGE
OUTLINE
E2
0.90
K
8
5
8X
e/2
e
2.30
b
1
0.10 C A B
0.05 C
8X
NOTE 3
0.30
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
NCP81074A, NCP81074B
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
SOLDERING FOOTPRINT*
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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For additional information, please contact your local
Sales Representative
NCP81074/D