MC10EP32 D

MC10EP32, MC100EP32
3.3V / 5V ECL B2 Divider
Description
• 350 ps Typical Propagation Delay
• Maximum Frequency > 4 GHz Typical (Figure 3)
• PECL Mode Operating Range:
•
MARKING DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
TSSOP−8
DT SUFFIX
CASE 948R
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• Pb−Free Packages are Available
1
DFN8
MN SUFFIX
CASE 506AA
H
K
5P
3K
M
8
HEP32
ALYW
G
= MC10
= MC100
= MC10
= MC100
= Date Code
KEP32
ALYW
G
1
8
HP32
ALYWG
G
1
KP32
ALYWG
G
3K MG
G
Features
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5P MG
G
The MC10/100EP32 is an integrated B2 divider with differential
CLK inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power−up, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP32’s in a system.
The 100 Series contains temperature compensation.
1
4
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
4
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 11
1
Publication Order Number:
MC10EP32/D
MC10EP32, MC100EP32
Table 1. PIN DESCRIPTION
RESET
1
8
VCC
Pin
R
CLK
2
7
Q
B2
CLK
VBB
3
6
4
5
Q
Function
CLK, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.
VEE
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 2 Function
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
78 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10EP32, MC100EP32
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
(Note 2)
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
40
23
30
40
23
30
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single−Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single−Ended)
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1890
2.0
150
0.5
1955
150
0.5
0.5
2015
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
4. All loading with 50 W to VCC − 2.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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3
MC10EP32, MC100EP32
Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
40
23
30
40
23
30
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single−Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single−Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
3590
2.0
3655
150
3715
150
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
7. All loading with 50 W to VCC − 2.0 V.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 9)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
40
23
30
40
23
30
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
−1135
−1010
−885
−1070
−945
−820
−1010
−885
−760
mV
VOL
Output LOW Voltage (Note 10)
−1935
−1810
−1685
−1870
−1745
−1620
−1810
−1685
−1560
mV
VIH
Input HIGH Voltage (Single−Ended)
−1210
−885
−1145
−820
−1085
−760
mV
VIL
Input LOW Voltage (Single−Ended)
−1935
−1610
−1870
−1545
−1810
−1485
mV
VBB
Output Voltage Reference
−1510
−1310
−1445
−1245
−1385
−1185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 11)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1410
VEE+2.0
0.0
VEE+2.0
150
0.5
−1345
0.0
VEE+2.0
150
0.5
−1285
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 W to VCC − 2.0 V.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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4
MC10EP32, MC100EP32
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
26
34
40
28
36
42
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1875
2.0
1875
150
0.5
1875
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
13. All loading with 50 W to VCC − 2.0 V.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
26
34
40
28
36
42
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single−Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
3575
2.0
150
0.5
3575
150
0.5
0.5
3575
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
16. All loading with 50 W to VCC − 2.0 V.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP32, MC100EP32
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 18)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
30
37
26
34
40
28
36
42
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 19)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 19)
−1945
−1820
−1695
−1945
−1820
−1695
−1945
−1820
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625
−1945
−1625
−1945
−1625
mV
VBB
Output Voltage Reference
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 20)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1425
VEE+2.0
0.0
−1425
VEE+2.0
150
0.5
0.0
−1425
VEE+2.0
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 W to VCC − 2.0 V.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
−40°C
Symbol
VOPP
Min
Typ
fin < 3.5 GHz
fin @ 4.0 GHz
640
700
740
CLK to Q, Q
RESET to Q, Q
RESET to Q, Q
250
220
320
330
290
400
200
550
Characteristic
Output Voltage Amplitude
(See Figure 3)
tPLH,
tPHL
Propagation Delay to
Output Differential
10 Series
100 Series
tRR
Set/Reset Recovery
tPW
Minimum Pulse width
tJITTER
CLOCK Random Jitter (RMS)
fin < 3.5 GHz
fin @ v4.0 GHz
VPP
Input Voltage Swing
(Differential Configuration)
tr
tf
Output Rise/Fall Times
(20% − 80%)
RESET
Q, Q
25°C
Max
Min
Typ
630
700
710
270
250
320
350
300
400
175
200
475
550
420
390
480
0.5
0.5
1.5
150
800
1200
50
100
150
85°C
Max
Min
Typ
500
700
600
320
320
375
400
380
450
175
200
175
ps
475
550
475
ps
450
390
480
0.5
0.5
1.5
150
800
1200
70
120
170
Max
Unit
mV
480
460
525
ps
ps
0.5
0.5
1.5
150
800
1200
mV
70
130
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
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VOPP, OUTPUT VOLTAGE (mV)
MC10EP32, MC100EP32
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.0
5.0 V
3.3 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fin, INPUT FREQUENCY (GHz)
Figure 3. Input Frequency (fin) versus Typical Output Voltage (VOPP)
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC10EP32, MC100EP32
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC10EP32DG
SOIC−8 (Pb−Free)
98 Units / Rail
MC10EP32DR2
SOIC−8
2500 / Tape & Reel
MC10EP32DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC10EP32DT
TSSOP−8
100 Units / Rail
MC10EP32DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC10EP32DTR2
TSSOP−8
2500 / Tape & Reel
MC10EP32DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC10EP32MNR4
DFN8
1000 / Tape & Reel
DFN8
(Pb−Free)
1000 / Tape & Reel
SOIC−8
98 Units / Rail
MC100EP32DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EP32DR2
SOIC−8
2500 / Tape & Reel
MC100EP32DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EP32DT
TSSOP−8
100 Units / Rail
MC100EP32DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EP32DTR2
TSSOP−8
2500 / Tape & Reel
MC100EP32DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EP32MNR4
DFN8
1000 / Tape & Reel
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC10EP32D
MC10EP32MNR4G
MC100EP32D
MC100EP32MNR4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10EP32, MC100EP32
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC10EP32, MC100EP32
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
V
S
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
http://onsemi.com
10
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC10EP32, MC100EP32
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
TOP VIEW
0.08 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
(A3)
SIDE VIEW
A1
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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11
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MC10EP32/D