NLSV4T240 D

NLSV4T240
4-Bit Dual-Supply Inverting
Level Translator
The NLSV4T240 is a 4−bit configurable dual−supply voltage level
translator. The input An and output Bn ports are designed to track two
different power supply rails, VCCA and VCCB respectively. Both
supply rails are configurable from 0.9 V to 4.5 V allowing universal
low−voltage translation from the input An to the output Bn port.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
•
Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V
High−Speed w/ Balanced Propagation Delay
Inputs and Outputs have OVT Protection to 4.5 V
Non−preferential VCCA and VCCB Sequencing
Outputs at 3−State until Active VCC is Reached
Power−Off Protection
Outputs Switch to 3−State with VCCB at GND
Ultra−Small Packaging: 1.7 mm x 2.0 mm UQFN12
This is a Pb−Free Device
1
WB = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
OE
Typical Applications
VCCA
1
• Mobile Phones, PDAs, Other Portable Devices
A1
Important Information
• ESD Protection for All Pins:
HBM (Human Body Model) > 6000 V
VCCA
11
VCCB
2
10
B1
A2
3
9
B2
A3
4
8
B3
A4
5
7
B4
VCCB
A1
B1
A2
B2
B3
A4
B4
12
6
GND
(Top View)
ORDERING INFORMATION
Device
A3
WBMG
G
UQFN12
MU SUFFIX
CASE 523AE
NLSV4T240MUTAG
Package
Shipping†
UQFN12 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
OE
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 2
1
Publication Order Number:
NLSV4T240/D
NLSV4T240
TRUTH TABLE
PIN ASSIGNMENT
Inputs
PIN
FUNCTION
VCCA
Input Port DC Power Supply
VCCB
Output Port DC Power Supply
GND
OE
Outputs
An
Bn
L
L
H
Ground
L
H
L
An
Input Port
H
X
3−State
Bn
Output Port
OE
Output Enable
MAXIMUM RATINGS
Symbol
VCCA, VCCB
VI
VC
VO
Rating
Value
DC Supply Voltage
Condition
Unit
−0.5 to +5.5
V
An
−0.5 to +5.5
V
OE
−0.5 to +5.5
V
(Power Down)
Bn
−0.5 to +5.5
(Active Mode)
Bn
−0.5 to +5.5
V
(Tri−State Mode)
Bn
−0.5 to +5.5
V
DC Input Voltage
Control Input
DC Output Voltage
VCCA = VCCB = 0
V
IIK
DC Input Diode Current
−20
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
IO
DC Output Source/Sink Current
±50
mA
ICCA, ICCB
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCCA, VCCB
Parameter
Bus Input Voltage
VC
Control Input
VIO
Bus Output Voltage
Dt / DV
Max
Unit
0.9
4.5
V
GND
4.5
V
OE
GND
4.5
V
Bn
GND
4.5
V
(Active Mode)
Bn
GND
VCCB
V
(Tri−State Mode)
Bn
GND
4.5
V
−40
+85
°C
0
10
nS
Positive DC Supply Voltage
VI
TA
Min
(Power Down Mode)
Operating Temperature Range
Input Transition Rise or Rate
VI, from 30% to 70% of VCC; VCC = 3.3 V ±0.3 V
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2
NLSV4T240
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
VIH
VIL
VOH
Parameter
Test Conditions
Input HIGH Voltage
(An, OE)
Input LOW Voltage
(An, OE)
Output HIGH Voltage
Min
Max
Unit
3.6 – 4.5
0.9 – 4.5
V
2.2
−
2.7 – 3.6
2.0
−
2.3 – 2.7
1.6
−
1.4 − 2.3
0.65 * VCCA
−
0.9 – 1.4
0.9 * VCCA
−
0.9 – 4.5
−
0.8
2.7 – 3.6
−
0.8
2.3 – 2.7
−
0.7
1.4 − 2.3
−
0.35 * VCCA
0.9 – 1.4
−
0.1 * VCCA
IOH = −100 mA; VI = VIL
0.9 – 4.5
0.9 – 4.5
VCCB – 0.2
−
IOH = −0.5 mA; VI = VIL
0.9
0.9
0.75 * VCCB
−
IOH = −2 mA; VI = VIL
1.4
1.4
1.05
−
IOH = −6 mA; VI = VIL
1.65
1.65
1.25
−
2.3
2.3
2.0
−
2.3
2.3
1.8
−
2.7
2.7
2.2
−
2.3
2.3
1.7
−
IOH = −18 mA; VI = VIL
Output LOW Voltage
VCCB (V)
3.6 – 4.5
IOH = −12 mA; VI = VIL
VOL
VCCA (V)
3.0
3.0
2.4
−
IOH = −24 mA; VI = VIL
3.0
3.0
2.2
−
IOL = 100 mA; VI = VIH
0.9 – 4.5
0.9 – 4.5
−
0.2
IOL = 0.5 mA; VI = VIH
1.1
1.1
−
0.3
IOL = 2 mA; VI = VIH
1.4
1.4
−
0.35
IOL = 6 mA; VI = VIH
1.65
1.65
−
0.3
IOL = 12 mA; VI = VIH
2.3
2.3
−
0.4
2.7
2.7
−
0.4
2.3
2.3
−
0.6
3.0
3.0
−
0.4
IOL = 18 mA; VI = VIH
IOL = 24 mA; VI = VIH
V
V
V
3.0
3.0
−
0.55
Input Leakage Current
VI = VCCA or GND
0.9 – 4.5
0.9 – 4.5
−1.0
1.0
mA
IOFF
Power−Off Leakage Current
OE = 0 V
0
0.9 – 4.5
0.9 – 4.5
0
−1.0
−1.0
1.0
1.0
mA
ICCA
Quiescent Supply Current
VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5
0.9 − 4.5
−
2.0
mA
ICCB
Quiescent Supply Current
VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5
0.9 − 4.5
−
2.0
mA
ICCA + ICCB Quiescent Supply Current
VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5
0.9 – 4.5
−
4.0
mA
II
DICCA
Increase in ICC per Input Voltage,
Other Inputs at VCCA or GND
VI = VCCA – 0.6 V;
VI = VCCA or GND
4.5
3.6
4.5
3.6
−
10
5.0
mA
DICCB
Increase in ICC per Input Voltage,
Other Inputs at VCCA or GND
VI = VCCA – 0.6 V;
VI = VCCA or GND
4.5
3.6
4.5
3.6
−
10
5.0
mA
I/O Tri−State Output Leakage
Current
TA = 25°C, OE = 0 V
0.9 – 4.5
0.9 – 4.5
−1.0
1.0
mA
IOZ
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3
NLSV4T240
TOTAL STATIC POWER CONSUMPTION (ICCA + ICCB)
−405C to +855C
VCCB (V)
4.5
VCCA (V)
Min
3.3
Max
Min
2.8
Max
Min
1.8
Max
Min
0.9
Max
Min
Max
Unit
4.5
2
2
2
2
< 1.5
μA
3.3
2
2
2
2
< 1.5
μA
2.8
<2
<1
<1
< 0.5
< 0.5
μA
1.8
<1
<1
< 0.5
< 0.5
< 0.5
μA
0.9
< 0.5
< 0.5
< 0.5
< 0.5
< 0.5
μA
NOTE: Connect ground before applying supply voltage VCCA or VCCB. This device is designed with the feature that the power−up sequence
of VCCA and VCCB will not damage the IC.
AC ELECTRICAL CHARACTERISTICS
−405C to +855C
VCCB (V)
4.5
Symbol
tPLH,
tPHL
(Note 1)
tPZH,
tPZL
(Note 1)
tPHZ,
tPLZ
(Note 1)
tOSHL,
tOSLH
(Note 1)
Min
3.3
Max
Min
2.8
Max
Min
1.8
Max
Unit
2.1
2.3
nS
2.1
2.3
2.6
2.1
2.3
2.5
2.8
2.1
2.4
2.5
2.7
3.0
1.2
2.4
2.7
2.8
3.0
3.3
4.5
2.6
3.8
4.0
4.1
4.3
3.3
3.7
3.9
4.1
4.3
4.6
2.5
3.9
4.1
4.3
4.5
4.8
1.8
4.1
4.4
4.5
4.7
5.0
1.2
4.4
4.7
4.8
5.0
5.3
4.5
2.6
3.8
4.0
4.1
4.3
3.3
3.7
3.9
4.1
4.3
4.6
2.5
3.9
4.1
4.3
4.5
4.8
1.8
4.1
4.4
4.5
4.7
5.0
1.2
4.4
4.7
4.8
5.0
5.3
4.5
0.15
0.15
0.15
0.15
0.15
3.3
0.15
0.15
0.15
0.15
0.15
2.5
0.15
0.15
0.15
0.15
0.15
1.8
0.15
0.15
0.15
0.15
0.15
1.2
0.15
0.15
0.15
0.15
0.15
VCCA (V)
Propagation
Delay,
4.5
1.6
1.8
2.0
3.3
1.7
1.9
An to Bn
2.8
1.9
1.8
Output
Enable,
OE to Bn
Output
Disable,
OE to Bn
Output to
Output
Skew,
Time
1.2
Max
Parameter
Min
Max
Min
nS
nS
nS
1. Propagation delays defined per Figure 2.
CAPACITANCE
Symbol
Parameter
Test Conditions
Typ (Note 2)
Unit
CIN
Control Pin Input Capacitance
VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B
3.5
pF
CI/O
I/O Pin Input Capacitance
VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B
5.0
pF
CPD
Power Dissipation Capacitance
VCCA = VCCB = 3.3 V, VI = 0 V or VCCA, f = 10 MHz
20
pF
2. Typical values are at TA = +25°C.
3. CPD is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
ICC(operating) ^ CPD x VCC x fIN x NSW where ICC = ICCA + ICCB and NSW = total number of outputs switching.
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4
NLSV4T240
VCC
Pulse
Generator
RL
DUT
CL
VCCO x 2
OPEN
GND
RL
Figure 2. AC (Propagation Delay) Test Circuit
Test
Switch
tPLH, tPHL
OPEN
tPLZ, tPZL
VCCO x 2
tPHZ, tPZH
GND
CL = 15 pF or equivalent (includes probe and jig capacitance)
RL = 2 kW or equivalent
ZOUT of pulse generator = 50 W
VIH
Input (An)
Vm
Vm
tPHL
tPLH
Output (Bn)
Vm
0V
VOH
Vm
VOL
Waveform 1 − Propagation Delays
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VIH
OEn
Vm
Vm
tPZH
0V
tPHZ
Output (Bn)
VOH
VY
Vm
≈0V
tPZL
tPLZ
≈ VCC
Vm
Output (Bn)
VX
VOL
Waveform 2 − Output Enable and Disable Times
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC (Propagation Delay) Test Circuit Waveforms
VCC
Symbol
3.0 V – 4.5 V
2.3 V − 2.7 V
1.65 V − 1.95 V
1.4 V − 1.6 V
0.9 V − 1.3 V
VmA
VCCA/2
VCCA/2
VCCA/2
VCCA/2
VCCA/2
VmB
VCCB/2
VCCB/2
VCCB/2
VCCB/2
VCCB/2
VX
VOL x 0.1
VOL x 0.1
VOL x 0.1
VOL x 0.1
VOL x 0.1
VY
VOH x 0.9
VOH x 0.9
VOH x 0.9
VOH x 0.9
VOH x 0.9
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5
NLSV4T240
PACKAGE DIMENSIONS
UQFN12 1.7x2.0, 0.4P
CASE 523AE
ISSUE A
ÉÉ
ÉÉ
ÉÉ
D
PIN 1 REFERENCE
2X
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH 0.03
MAX ON BOTTOM SURFACE OF
TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
A B
L1
DETAIL A
E
NOTE 5
TOP VIEW
DIM
A
A1
A3
b
D
E
e
K
L
L1
L2
DETAIL B
A
0.05 C
12X
0.05 C
A1
A3
8X
C
SIDE VIEW
SEATING
PLANE
K
5
MOUNTING FOOTPRINT
SOLDERMASK DEFINED
7
DETAIL A
e
1
12X
DETAIL B
OPTIONAL
CONSTRUCTION
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.70 BSC
2.00 BSC
0.40 BSC
0.20
---0.45
0.55
0.00
0.03
0.15 REF
11
L
2.00
12X
L2
BOTTOM VIEW
1
b
0.10
M
C A B
0.05
M
C
0.32
NOTE 3
2.30
0.40
PITCH
11X
0.22
12X
0.69
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NLSV4T240/D