NB3H83905C 1.8V/2.5V/3.3V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer with OE Description The NB3H83905C is a 1.8 V, 2.5 V or 3.3 V VDD core Crystal input to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by flexible 1.8 V, 2.5 V, or 3.3 V supply VDDO (with VDD w VDDO). The device accepts a fundamental Parallel Resonant crystal from 3 MHz to 40 MHz or a single−ended LVCMOS Clock from up to 100 MHz. Two synchronous LVTTL/LVCMOS Enable lines permit independent control over outputs BCLK[0:4] and output BCLK5; enabling or disabling only when the output is in LOW state eliminating potential output glitching or runt pulse generation. When unused, leave floating open, pins will default to HIGH state. The 6 outputs drive 50 W series or parallel terminated transmission lines. Parallel termination should be to 1/2 VCC. Series terminated lines can drive 2 loads each, or 12 lines total. Fit, Form, and Function compatible with ICS83905 and PI6C10806. Features • Six Copies of LVTTL/LVCMOS Output Clock • Supply Operation VDD w VDDO: 1.8 V$0.2 V, 2.5 V $5% or 3.3 V $5% Core VDD 1.8 V$0.2 V, 2.5 V $5%, or 3.3 V $5% Output VDDO Crystal Oscillator Interface Crystal Input Frequency Range: 3 MHz to 40 MHz Clock Input Frequency Range: Up to 100 MHz LVCMOS compatible Enable Inputs 5 V Tolerant Enable Inputs Low Output to Output Skew: 80 ps Max Synchronous Output Enable Phase Noise Floor −160 dBc (1 MHz) Industrial Temperature Range These are Pb−Free Devices http://onsemi.com MARKING DIAGRAMS* 16 SOIC−16 D SUFFIX CASE 751B NB3H83905G ALYYWW 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F NB3H 905C ALYWG G 1 ♦ • • • • • • • • • • ♦ 1 1 QFN20 MN SUFFIX CASE 485BH 20 NB3H 83905 ALYWG G A = Assembly Location L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (*Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. BCLK0 XTAL_IN/CLK C1 XTAL_OUT BCLK1 ORDERING INFORMATION BCLK2 See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. BCLK3 C2 BCLK4 ENABLE1 ENABLE2 SYNC BCLK5 SYNC Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2012 November, 2012 − Rev. 9 1 Publication Order Number: NB3H83905C/D 1 16 XTAL_IN/CLK ENABLE2 2 15 ENABLE1 GND 3 14 BCLK5 13 VDDO 5 12 BCLK4 BCLK1 6 11 GND GND 7 10 BCLK3 BCLK2 8 9 VDD VDDO GND 1 15 GND 2 14 BCLK0 VDDO BCLK1 3 EP 13 4 12 5 11 8 9 10 VDD BCLK3 4 Exposed Pad 20 19 18 17 16 GND GND BCLK2 BCLK0 XTAL_IN/CLK ENABLE1 NC XTAL_OUT ENABLE2 XTAL_OUT NB3H83905C 6 7 BCLK5 VDDO BCLK4 GND GND QFN20 SOIC−16/TSSOP−16 Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION SOIC−16 / TSSOP−16 QFN−20 Name I/O 1 19 XTAL_OUT Crystal Interface 2 20 ENABLE 2 LVTTL / LVCMOS Input 3, 7, 11 1, 2, 6, 7, 11, 12 GND GND 4, 6, 8, 10, 12, 14 3, 5, 8, 10, 13, 15 BCLK0, 1, 2, 3, 4, 5 LVCMOS Outputs Buffered Clock Outputs 5, 13 4, 14 VDDO POWER Positive Supply voltage for outputs. All GND, VDD and VDDO pins must be externally connected to power supply to guarantee proper operation. Bypass with 0.01 mF cap to GND. 9 9 VDD POWER Positive Supply voltage for core. All GND, VDD and VDDO pins must be externally connected to power supply to guarantee proper operation. Bypass with 0.01 mF cap to GND. − 16 NC 15 17 ENABLE 1 LVTTL / LVCMOS Input 16 18 XTAL_IN/ CLK Crystal Interface − EP Description Oscillator Output to drive Crystal Synchronous Enable Input for BCLK5 Output. Switches only when HIGH. Open default condition HIGH due to an internal pullup resistor to VCC. GND Supply pins. All GND, VDD and VDDO pins must be externally connected to power supply to guarantee proper operation. No Connect − Synchronous Enable Input for BCLK0/1/2/3/4 Output block. Switches only when HIGH. Open default condition HIGH due to an internal pullup resistor to VCC Oscillator Input from Crystal. Single ended Clock Input. The Exposed Pad (EP) on the QFN−20 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. http://onsemi.com 2 NB3H83905C Table 2. CLOCK ENABLE FUNCTION TABLE Control Inputs Outputs ENABLE1* ENABLE2* BCLK0:BCLK4 BCLK5 0 0 LOW LOW 0 1 LOW Toggling 1 0 Toggling LOW 1 1 Toggling Toggling *Defaults HIGH when floating open. BCLK5 BCLK0:4 ENABLE2 ENABLE1 Figure 3. ENABLEx Control Timing Diagram The ENABLEx control inputs will synchronously enable or disable the selected output(s). This control detects the falling edge of the internal signal and asserts or de−asserts the output after 3 clock cycles. When ENABLEx is LOW, the outputs are disabled to a LOW state. When ENABLEx is HIGH, the outputs are enabled to toggle. Table 3. RECOMMENDED CRYSTAL PARAMETERS Crystal Fundamental AT−Cut Frequency 10 to 40 MHz Load Capacitance* 16−20 pF Shunt Capacitance, C0 7 pF Max Equivalent Series Resistance 50 W Max Drive Level 1 mW *See APPLICATION INFORMATION; Crystal Input Interface for CL loading Table 4. ATTRIBUTES (Note 1) Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index Transistor Count > 2 kV > 200 V Level 1 UL−94 code V−0 A 1/8” 28 to 34 213 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NB3H83905C Table 5. MAXIMUM RATINGS (Note 2) Symbol VDDx Parameter Positive Power Supply Condition 1 Condition 1 GND = 0 V Rating Unit 4.6 V –0.5 v VI v VDD + 0.5 V −40 to v +85 °C −65 to +150 °C VI Input Voltage TA Operating Temperature Range, Industrial Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−16 SOIC−16 80 55 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) SOIC−16 33−36 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−16 TSSOP−16 138 108 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) TSSOP−16 33−36 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−20 QFN−20 47 33 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) QFN−20 18 °C/W Tsol Wave Solder 265 °C 3 sec @ 248°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 4 NB3H83905C Table 6. DC CHARACTERISTICS Symbol Characteristic Min Typ Max Unit Core Quiescent Power Supply Current (ENABLEx = LOW) 10 mA Output Quiescent Power Supply Current (ENABLEx = LOW) 5 mA VDD = VDDO = 3.135 V to 3.465 V (3.3 V $5%); GND = 0 V, TA = −405C to +855C IDD IDDO VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK 2 VDD + 0.3 V V VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK −0.3 0.8 V VOH Output HIGH Voltage (Note 4) 2.6 VOL Output LOW Voltage (Note 4) V 0.5 V CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per Output) (Note 4) 19 pF ROUT Output Impedance (Note 4) 7 W VDD = VDDO = 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, TA = −405C to +855C IDD IDDO Core Quiescent Power Supply Current (ENABLEx = LOW) 8 mA Output Quiescent Power Supply Current (ENABLEx = LOW) 4 mA VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK 1.7 VDD + 0.3 V V VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK −0.3 0.7 V VOH Output HIGH Voltage (IOH = −1 mA) Output HIGH Voltage (Note 4) 2.0 1.8 VOL Output LOW Voltage (IOL = 1 mA) Output LOW Voltage (Note 4) CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per Output) (Note 4) 18 pF ROUT Output Impedance (Note 4) 7 W V 0.4 0.45 V VDD = VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, TA = −405C to +855C IDD IDDO Core Quiescent Power Supply Current (ENABLEx = LOW) 5 mA Output Quiescent Power Supply Current (ENABLEx = LOW) 3 mA VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK 0.65*VDD VDD + 0.3 V V VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK −0.3 0.35*VDD V VOH Output HIGH Voltage (Note 4) VOL Output LOW Voltage (Note 4) CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per Output) (Note 4) 16 pF ROUT Output Impedance (Note 4) 10 W VDDO−0.3 V 0.35 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Parallel terminated 50 W to VDDO/2 (see Figure 5). http://onsemi.com 5 NB3H83905C Table 6. DC CHARACTERISTICS (continued) Symbol Characteristic Min Typ Max Unit Core Quiescent Power Supply Current (ENABLEx = LOW) 10 mA Output Quiescent Power Supply Current (ENABLEx = LOW) 4 mA VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, TA = −405C to +855C IDD IDDO VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK 2 VDD + 0.3 V V VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK −0.3 0.8 V VOH Output HIGH Voltage (IOH = −1 mA) Output HIGH Voltage (Note 4) 2.0 1.8 VOL Output LOW Voltage (IOL = 1 mA) Output LOW Voltage (Note 4) CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per Output) (Note 4) 18 pF ROUT Output Impedance (Note 4) 7 W V 0.4 0.45 V VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V.); GND = 0 V, TA = −405C to +855C IDD IDDO Core Quiescent Power Supply Current (ENABLEx = LOW) Output Quiescent Power Supply Current (ENABLEx = LOW) 10 mA 3 mA VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK 2 VDD + 0.3 V V VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK −0.3 0.8 V VOH Output HIGH Voltage (Note 4) VOL Output LOW Voltage (Note 4) CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per Output) (Note 4) 16 pF ROUT Output Impedance (Note 4) 10 W VDDO−0.3 V 0.35 V VDD = 2.375 V to 2.625 V (2.5 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, TA= −405C to +855C IDD IDDO Core Quiescent Power Supply Current (ENABLEx = LOW) 8 mA Output Quiescent Power Supply Current (ENABLEx = LOW) 3 mA 1.7 VDD + 0.3 V V −0.3 0.7 V VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK VOH Output HIGH Voltage (Note 4) VOL Output LOW Voltage (Note 4) CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per Output) (Note 4) 16 pF ROUT Output Impedance (Note 4) 10 W VDDO−0.3 V 0.35 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Parallel terminated 50 W to VDDO/2 (see Figure 5). http://onsemi.com 6 NB3H83905C Table 7. AC CHARACTERISTICS Symbol Characteristic Min Typ Max Unit 3 40 MHz DC 100 VDD = VDDO = 3.135 V to 3.465 V (3.3 V $ 5%); GND = 0 V, TA = −405C to +855C (Note 5) Fmax Input Frequency Crystal Input Frequency Clock (XTAL_IN/CLK) tEN / tDIS Delay for Output Enable / Disable Time ENABLEx to BCLKn tSKEWDC Duty Cycle Skew (See Figure 4) 48 tSKEWO−O Output to Output Skew Within A Device (same conditions) 0 FNOISE tJIT(F) tr/tf Phase−Noise Performance fout = 25 MHz RMS Phase Jitter 50 100 Hz off Carrier 1 kHz off Carrier 10 kHz off Carrier 100 kHz off Carrier −123 −142 −153 −164 25 MHz carrier, Integration Range 12 kHz to 20 MHz 25 MHz carrier, Integration Range 100 Hz to 1 MHz 0.08 0.08 Output rise and fall times (20%; 80%) 4 Cycles 52 % 80 ps dBc/Hz ps 200 800 ps 3 40 MHz DC 100 VDD = VDDO = 2.375 V to 2.625 V (2.5 V $ 5%); GND = 0 V, TA = −405C to +855C (Note 5) Fmax Input Frequency Crystal Input Frequency Clock (XTAL1) tEN / tDIS Delay for Output Enable / Disable Time ENABLEx to BCLKn tSKEWDC Duty Cycle Skew (See Figure 4) 47 tSKEWO−O Output to Output Skew Within A Device (same conditions) 0 FNOISE tJIT(F) tr/tf Phase−Noise Performance fout = 25 MHz RMS Phase Jitter 50 100 Hz off Carrier 1 kHz off Carrier 10 kHz off Carrier 100 kHz off Carrier −118 −137 −151 −165 25 MHz carrier, Integration Range 12 kHz to 20 MHz 25 MHz carrier, Integration Range 100 Hz to 1 MHz 0.13 0.13 Output rise and fall times (20%; 80%) 4 Cycles 53 % 80 ps dBc/Hz ps 200 800 ps 3 40 MHz DC 100 VDD = VDDO = 1.6 V to 2.0 V (1.8 V $ 0.2 V); GND = 0 V, TA = −405C to +855C (Note 5) Fmax Input Frequency Crystal Input Frequency Clock (XTAL1) tEN / tDIS Delay for Output Enable / Disable Time ENABLEx to BCLKn tSKEWDC Duty Cycle Skew (See Figure 4) 47 tSKEWO−O Output to Output Skew Within A Device (same conditions) 0 FNOISE tJIT(F) tr/tf Phase−Noise Performance fout = 25 MHz RMS Phase Jitter 50 100 Hz off Carrier 1 kHz off Carrier 10 kHz off Carrier 100 kHz off Carrier −129 −145 −147 −157 25 MHz carrier, Integration Range 12 kHz to 20 MHz 25 MHz carrier, Integration Range 100 Hz to 1 MHz 0.27 0.27 Output rise and fall times (20%; 80%) 200 4 Cycles 53 % 80 ps dBc/Hz ps 900 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Crystal inputs v Fmax. Outputs loaded with 50 W to VDDO/2. CLOCK (LVCMOS levels at XTAL1 input) 50% duty cycle. See Figures 4 and 7. See APPLICATION INFORMATION; Crystal Input Interface for CL loading. http://onsemi.com 7 NB3H83905C Table 7. AC CHARACTERISTICS (continued) Symbol Characteristic Min Typ Max Unit VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, TA = −405C to +855C (Note 5) Fmax Input Frequency Crystal Input Frequency Clock (XTAL_IN/CLK) 3 40 DC 100 tEN / tDIS Delay for Output Enable / Disable Time ENABLEx to BCLKn tSKEWDC Duty Cycle Skew (See Figure 4) 48 tSKEWO−O Output to Output Skew Within A Device (same conditions) 0 FNOISE tJIT(F) tr/tf Phase−Noise Performance fout = 25 MHz RMS Phase Jitter 50 100 Hz off Carrier 1 kHz off Carrier 10 kHz off Carrier 100 kHz off Carrier −129 −145 −147 −157 25 MHz carrier, Integration Range 12 kHz to 20 MHz 25 MHz carrier, Integration Range 100 Hz to 1 MHz 0.14 0.14 Output rise and fall times (20%; 80%) 200 MHz 4 Cycles 52 % 80 ps dBc/Hz ps 800 ps VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, TA = −405C to +855C (Note 5) Fmax Input Frequency Crystal Input Frequency Clock (XTAL1) 3 40 DC 100 tEN / tDIS Delay for Output Enable / Disable Time ENABLEx to BCLKn tSKEWDC Duty Cycle Skew (See Figure 4) 48 tSKEWO−O Output to Output Skew Within A Device (same conditions) 0 FNOISE tJIT(F) tr/tf Phase−Noise Performance fout = 25 MHz RMS Phase Jitter 50 100 Hz off Carrier 1 kHz off Carrier 10 kHz off Carrier 100 kHz off Carrier −129 −145 −147 −157 25 MHz carrier, Integration Range 12 kHz to 20 MHz 25 MHz carrier, Integration Range 100 Hz to 1 MHz 0.18 0.18 Output rise and fall times (20%; 80%) 200 MHz 4 Cycles 52 % 80 ps dBc/Hz ps 900 ps VDD = 2.375 V to 2.625 V (2.5 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, TA = −405C to +855C (Note 5) Fmax Input Frequency Crystal Input Frequency Clock (XTAL1) 3 40 DC 100 tEN / tDIS Delay for Output Enable / Disable Time ENABLEx to BCLKn tSKEWDC Duty Cycle Skew (See Figure 4) 47 tSKEWO−O Output to Output Skew Within A Device (same conditions) 0 FNOISE tJIT(F) tr/tf Phase−Noise Performance fout = 25 MHz/ RMS Phase Jitter 50 100 Hz off Carrier 1 kHz off Carrier 10 kHz off Carrier 100 kHz off Carrier −129 −145 −147 −157 25 MHz carrier, Integration Range 12 kHz to 20 MHz 25 MHz carrier, Integration Range 100 Hz to 1 MHz 0.19 0.19 Output rise and fall times (20%; 80%) 200 MHz 4 Cycles 53 % 80 ps dBc/Hz ps 900 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Crystal inputs v Fmax. Outputs loaded with 50 W to VDDO/2. CLOCK (LVCMOS levels at XTAL1 input) 50% duty cycle. See Figures 4 and 7. See APPLICATION INFORMATION; Crystal Input Interface for CL loading. http://onsemi.com 8 NB3H83905C BCLKx BCLKy V DDO V DDO 2 2 V DDO V DDO 2 2 tSKEW O−O tSKEW O−O V DDO BCLKx tPW 2 V DDO V DDO 2 2 tP t SKEWDC % + ǒt PWńt PǓ 100% 80% BCLKx 20% tr tf Figure 4. AC Reference Measurement Figure 5. Typical Phase Noise Plot of the NB3H83905C Operating at 25 MHz VDD = VDDO= 3.3 V http://onsemi.com 9 NB3H83905C Figure 6. Typical Phase Noise Plot of the NB3H83905C Operating at 25 MHz VDD = VDDO = 2.5 V VDD NB3H83905C VDDO ZO = 50 W BCLKx IN Scope 50 W DUT GND GND Figure 7. Typical Device Evaluation and Termination Setup − See Table 8 Table 8. TEST SUPPLY SETUP. VDDO SUPPLY MAY BE CENTERED ON 0.0 V (SCOPE GND) TO PERMIT DIRECT CONNECTION INTO “50 W TO GND” SCOPE MODULE. VDD SUPPLY TRACKS DUT GND PIN Spec Condition: Test Setup VDD: Test Setup VDDO: Test Setup DUT GND: VDD = VDDO = 3.135 V to 3.465 V (3.3 V $5%) 1.56 to 1.73 V 1.56 to 1.73 V −1.56 to −1.73 V VDD = VDDO = 2.375 V to 2.625 V (2.5 V $5%) 1.1875 to 1.3125 V 1.1875 to 1.3125 V −1.1875 to −1.3125 V 0.8 to 1.0 V 0.8 to 1.0 V −0.8 to −1.0 V VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 2.375 V to 2.625 V (2.5 V $5%) 1.955 to 2.1525 V 1.1875 to 1.3125 V −1.1875 to −1.3125 V VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V) 2.335 to 2.465 V 0.8 to 1.0 V −0.8 to −1.0 V VDD = 2.375 V to 2.625 V (2.5 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V) 1.575 to 1.625 V 0.8 to 1.0 V −0.8 to −1.0 V VDD = VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V) http://onsemi.com 10 NB3H83905C APPLICATION INFORMATION Crystal Input Interface Unused Input and Output Pins Figure 8 shows the NB3H83905C device crystal oscillator interface using a typical parallel resonant crystal. A parallel crystal with loading capacitance CL = 18 pF would use C1 = 32 pF and C2 = 32 pF as nominal values, assuming 4 pF of stray cap per line. The frequency accuracy and duty cycle skew can be fine tuned by adjusting the C1 and C2 values. For example, increasing the C1 and C2 values will reduce the operational frequency. Note R1 is optional and may be 0 W. All LVCMOS control pins have internal pull−ups or pull−downs; additional external resistors are not required (optionally 1 kW resistors may be used). All unused LVCMOS outputs can be left floating with no trace attached. Bypass The VDD and VDDO supply pins should be bypassed with both a 10 mF and a 0.1 mF cap from supply pins to GND. Rseries = 28 W 32 pF C1 X1 18 pF Parallel Resonant Crystal 32 pF C2 BCLKx XTAL_IN/CLK R1* LVCMOS NB3H83905C Figure 9. Series Termination XTAL_OUT R = 100 W Figure 8. NB3H83905C Crystal Oscillator Interface * R1 is optional BCLKx Termination NB3H83905C device output series termination may be used by locating a 28 W series resistor at the driver pin as shown in Figure 9. Alternatively, a Thevenin Parallel termination may be used by locating a 100 W pullup resistor to VDD and a 100 W pullup resistor to GND at the receiver pin, instead of an Rs source termination resistor, Figure 10. LVCMOS R = 100 W Figure 10. Optional Thevenin Termination ORDERING INFORMATION Package Shipping† NB3H83905CDG SOIC−16 (Pb*Free) 48 Units / Rail NB3H83905CDR2G SOIC−16 (Pb*Free) 2500 Units / Tape & Reel NB3H83905CDTG TSSOP−16 (Pb*Free) 96 Units /Rail NB3H83905CDTR2G TSSOP−16 (Pb*Free) 2500 Units / Tape & Reel NB3H83905CMNG QFN−20 (Pb−Free) 92 Units / Rail NB3H83905CMNTXG QFN−20 Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NB3H83905C PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 NB3H83905C PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB3H83905C PACKAGE DIMENSIONS QFN20 4x4, 0.5P CASE 485BH ISSUE O ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ B A D L1 DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉÉ ÉÉÉ EXPOSED Cu 0.15 C 0.15 C L L PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION A 0.10 C A3 0.08 C DETAIL B NOTE 4 DETAIL A 6 MOUNTING FOOTPRINT* A1 SIDE VIEW D2 MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.20 0.30 4.00 BSC 2.60 2.80 4.00 BSC 2.60 2.80 0.50 BSC 0.20 −−− 0.35 0.45 0.00 0.15 C SEATING PLANE 4.30 2.80 20X 0.60 K 1 20X L 11 2.80 4.30 E2 1 PACKAGE OUTLINE 16 e 20X BOTTOM VIEW b 0.10 C A B 0.05 C NOTE 3 0.50 PITCH 20X 0.35 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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