NB3L853141 2.5V/3.3V 1:5 LVPECL Fanout Buffer Description The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer designed explicitly for low output skew applications. The NB3L853141 features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The SEL pin will select the differential clock inputs, CLK0 & CLK0, when LOW (or left open and pulled LOW by the internal pull−down resistor). When SEL is HIGH, the single−ended CLK1 input is selected. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. www.onsemi.com MARKING DIAGRAM NB3L 3141 ALYW TSSOP−20 DT SUFFIX CASE 948E A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Features • 700 MHz Maximum Clock Output Frequency • CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL, • • • • • • • • • • • LVHSTL, SSTL, LVCMOS CLK1 can Accept LVCMOS and LVTTL Five Differential LVPECL Clock Outputs 1.5 ns Maximum Propagation Delay Operating Range: VCC = 2.375 V to 3.8 V LVCMOS Compatible Control Inputs Selectable Differential or LVCMOS Clock Inputs Synchronous Clock Enable 30 ps Max. Skew Between Outputs −40°C to +85°C Ambient Operating Temperature Range TSSOP−20 Package These are Pb−Free Devices D EN Q Q0 Q0 CLK0 0 CLK0 Q1 Q1 + CLK1 Q2 1 Q2 Q3 SEL Q3 Q4 Q4 Figure 1. Simplified Logic Diagram of NB3L853141 ORDERING INFORMATION Applications See detailed ordering and shipping information on page 8 of this data sheet. • Computing and Telecom • Routers, Servers and Switches • Backplanes © Semiconductor Components Industries, LLC, 2015 December, 2015 − Rev. 2 1 Publication Order Number: NB3L853141/D NB3L853141 VCC EN VCC NC CLK1 CLK0 CLK0 NC 20 19 18 17 16 15 14 13 SEL VEE 12 Table 1. FUNCTION TABLE 11 CLK0 CLK1 SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* *On next negative transition of CLK0 or CLK1 X = Don’t Care 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Note: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Table 2. PIN DESCRIPTION Open Default Pin Number Name I/O Description 1 Q0 LVPECL Output Non−Inverted Differential Clock Output 2 Q0 LVPECL Output Inverted Differential Clock Output 3 Q1 LVPECL Output Non−Inverted Differential Clock Output 4 Q1 LVPECL Output Inverted Differential Clock Output 5 Q2 LVPECL Output Non−Inverted Differential Clock Output 6 Q2 LVPECL Output Inverted Differential Clock Output 7 Q3 LVPECL Output Non−Inverted Differential Clock Output 8 Q3 LVPECL Output Inverted Differential Clock Output 9 Q4 LVPECL Output Non−Inverted Differential Clock Output 10 Q4 LVPECL Output Inverted Differential Clock Output 11 VEE Power 12 SEL LVCMOS / LVTTL Input 13 NC 14 CLK0 Multi−Level Input High Inverted Differential Clock Input. Internal Pull−up Resistor. 15 CLK0 Multi−Level Input Low Non−Inverted Differential Clock Input. Internal Pull−down Resistor. 16 CLK1 LVCMOS/LVTTL Input Low Single−ended Clock Input. Internal Pull−down Resistor. 17 NC 18 VCC Power 19 EN LVCMOS/LVTTL Input 20 VCC Power Negative Supply Voltage Low Clock Select Input. When HIGH, selects CLK1 input. When LOW, selects CLK0, CLK0 inputs. Internal Pull−down Resistor. No Connect No Connect Positive Supply Voltage Low Synchronous Clock Enable Input. When Low, outputs are enabled. When High, outputs are disabled Low. Internal Pull−down Resistor. Positive Supply Voltage All VCC and VEE pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.01 mF to GND. www.onsemi.com 2 NB3L853141 Table 3. ATTRIBUTES (Note 1) Characteristics ESD Protection Value Human Body Model Machine Model > 2 kV > 200 V RPU − Pull−up Resistor 50 kW RPD − Pull−down Resistor 50 kW Moisture Sensitivity (Note 1) Flammability Rating TSSOP−20 Oxygen Index: 28 to 34 Level 1 UL*94 code V*0 @ 0.125 in Transistor Count 300 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 4.6 V −0.5 to VCC + 0.5 V 50 100 mA mA VCC LVPECL Mode Power Supply VEE = 0 V VI LVPECL Mode Input Voltage VEE = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 50 °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W Tsol Wave Solder <2 to 3 sec @ 260°C 265 °C VI ≤ VCC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 NB3L853141 Table 5. DC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 2); TA = −40°C to +85°C Symbol Characteristic Min Typ Max Unit 3.8 V 55 mA POWER SUPPLY VCC Power Supply Voltage IEE Power Supply Current (Outputs Open) 2.375 40 LVPECL OUTPUTS (Note 3) VOH Output HIGH Voltage VCC−1.4 VCC−0.9 V VOL Output LOW Voltage VCC−2.0 VCC−1.7 V 0.6 1.0 V VSWING Output Voltage Swing, Peak−to−Peak DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 4) (Figures 3 and 4) VIH Single−ended Input HIGH Voltage 0.5 VCC+0.3 V VIL Single−ended Input LOW Voltage −0.3 VCC−1.0 V Vth Input Threshold Reference Voltage Range (Note 5) 0.35 VCC−0.85 V Single−ended Input Voltage (VIH − VIL) 0.3 VCC V VISE DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 5 and 6) (Note 6) VIHD Differential Input HIGH Voltage 0.5 VCC−0.85 mV VILD Differential Input LOW Voltage 0 VIHD−150 mV VID Differential Input Voltage (VIHD − VILD) 0.15 1.3 V VCMR Common Mode Input Voltage; (Note 7) 0.5 VCC–0.85 IIH IIL Input HIGH Current VCC = VIN = 3.8 V CLK0 CLK0 Input LOW Current VCC = 3.8V, VIN = 0 V CLK0 CLK0 150 5 −5 −150 mA mA SINGLE−ENDED INPUTS (SEL, EN, CLK1) VIH Input HIGH Voltage SEL, EN CLK1 2.0 2.0 VCC+0.3 VCC+0.3 V VIL Input LOW Voltage SEL, EN CLK1 −0.3 −0.3 0.8 VCCx0.35 V IIH Input HIGH Current VCC = VIN = 3.8 V CLK1, SEL, EN 150 mA IIL CLK1, SEL, EN CLK1, SEL, EN −5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and Output parameters vary 1:1 with VCC. 3. LVPECL outputs loaded with 50 W to VCC − 2 V for proper operation. 4. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 5. Vth is applied to the complementary input when operating in single−ended mode. 6. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 7. The common mode voltage is defined as VIH. www.onsemi.com 4 mA NB3L853141 Table 6. AC CHARACTERISTICS, VCC = 2.375 V to 3.8 V, TA = −40°C to +85°C (Note 8) Symbol fMAX FN Characteristic Maximum Input Clock Frequency: VOUTpp ≥ 400 mV Phase Noise, fC = 155.52 MHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz tPLH, tPHL Propagation Delay to Differential Outputs, @ 50 MHz t∫FN Additive Phase Jitter, RMS; fC = 155.52 MHz, Integration Range: 12 kHz − 20 MHz tsk(o) tsk (pp) VINpp tr/tf ODC Min CLK0/CLK0, VINPPmin ≥ 250 mV CLK1 Offset from Carrier Note 9 Note 10 CLK0/CLK0 to Q/Q CLK1 to Q Typ Max 700 300 −100.5 −128.2 −138.6 −147.1 −149.7 −154.2 −154.2 −154.2 0.8 0.8 1.0 1.0 dBc/ Hz 1.5 1.5 0.05 Output−to−output skew; (Note 11) ns ps 30 Part−to−Part Skew; (Note 12) Unit MHz ps 150 ps Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14) 150 1300 mV Output rise and fall times, 20% to 80%, 200 700 ps 45 45 55 55 % Output Clock Duty Cycle Input Duty Cycle = 50% Q, Q CLK0/CLK0, f ≤ 700 MHz, VINPPmin ≥ 250 mV CLK1, f ≤ 250MHz All parameters measured at fMAX unless noted otherwise. The cycle−to−cycle jitter on the input will equal the jitter on the output. The part does not add jitter 8. Measured using a VINPPmin source, Reference Duty Cycle = 50% duty cycle clock source. All output loading with external 50 W to VCC * 2 V. 9. Measured from the differential input crossing point to the differential output crossing point. 10. Measured from VCC /2 input crossing point to the differential output crossing point. 11. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. 12. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 13. Output voltage swing is a single−ended measurement operating in differential mode. 14. Input voltage swing is a single−ended measurement operating in differential mode. www.onsemi.com 5 NB3L853141 NB3L853141 Additive Phase Jitter @ 155.52 MHz VDD = 3.3 V 12 kHz to 20 MHz = 40.3 fs (typical) Filter = 12 kHz − 20 MHz Source RMS Jitter = 123.13 fs Output RMS Jitter = 129.56 fs RMS addititive jitter + ǸRMS phase jitter of output 2 * RMS phase jitter of input 2 40.3 fs + Ǹ129.56 fs 2 * 123.13 fs 2 Output (DUT + Source) Input Source 155.52 M Source, F_carrier = 155.52 MHz NB3L853141 F_carrier = 155.52 MHz Figure 2. Typical Phase Noise Plot at fcarrier = 155.52 MHz at an Operating Voltage of 3.3 V, Room Temperature The above phase noise data was captured using Agilent E5052A/B. The data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. The RMS Phase Jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 40.3 fs. The additive phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. To obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the DUT. If the phase noise of the source is greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. The Figure above is a good example of the NB3L853141 source generator phase noise having a significantly higher floor such that the DUT output results in an additive phase jitter of 40.3 fs. RMS addititive jitter + ǸRMS phase jitter of output 2 * RMS phase jitter of input 2 40.3 fs + Ǹ129.56 fs 2 * 123.13 fs 2 www.onsemi.com 6 NB3L853141 IN VIH Vth VIL IN Vth Figure 3. Differential Input Driven Single−Ended VCC VIHmax Vthmax VILmax Vth IN VIH Vth VIL IN IN VIHmin Vthmin VILmin VEE Figure 4. Vth Diagram Figure 5. Differential Inputs Driven Differentially VCC VIHDmax VILDmax VCMRmax VID = VIHD − VILD IN IN IN VID = |VIHD(IN) − VILD(IN)| VCMR VIHD VIHDtyp VILDtyp IN VILD VIHDmin VCMRmin VILDmin VEE Figure 7. VCMR Diagram Figure 6. Differential Inputs Driven Differentially IN VCC / 2 VINPP = VIH(IN) − VIL(IN) IN VCC / 2 SEL tpd Q tpd Qx Q Qx tPHL tPLH Figure 9. SEL to Qx Timing Diagram Figure 8. AC Reference Measurement www.onsemi.com 7 NB3L853141 Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NB3L853141DTG TSSOP−20 (Pb−Free) 75 Units / Rail NB3L853141DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 8 NB3L853141 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B L SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 9 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB3L853141 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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