Si4894BDY-DS

SPICE Device Model Si4894BDY
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72998
S-60245Rev. B, 20-Feb-06
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SPICE Device Model Si4894BDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Simulated
Data
Measured
Data
Symbol
Test Condition
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 µA
2.1
V
On-State Drain Current a
ID(on)
VDS ≥ 5 V, VGS = 10 V
490
A
Drain-Source On-State Resistance a
rDS(on)
Unit
Static
Forward Transconductance a
Forward Voltage
Dynamic
a
VGS = 10 V, ID = 12 A
0.009
0.009
VGS = 4.5 V, ID = 9.8 A
0.013
0.013
gfs
VDS = 15 V, ID = 12 A
31
32
S
VSD
IS = 2.3 A, VGS = 0 V
0.81
0.76
V
24
25.4
VDS = 15 V, VGS = 10 V, ID = 12 A
5.3
5.3
Ω
b
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
4.3
4.3
Turn-On Delay Time
td(on)
14
13
tr
8
10
18
33
16
10
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
tf
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 72998
S-60245Rev. B, 20-Feb-06
SPICE Device Model Si4894BDY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72998
S-60245Rev. B, 20-Feb-06
www.vishay.com
3
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Document Number: 91000
Revision: 18-Jul-08
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