5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A ® Data Sheet May 31, 2006 ±15kV ESD Protected, +3.3V, 1Microamp, 250kbps, RS-232 Transmitters/Receivers The Intersil 5962-062070xQxA devices are 3.3V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide ±15kV ESD protection (IEC61000-4-2 Air Gap and MIL-STD 883 Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Targeted applications include ruggedized portable products and remotely deployed devices exposed to extreme temperature and humidity where the low operational and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic power-down functions (except for the 5962-0620703Q2A), reduce the standby supply current to a 1µA trickle. Small footprint packaging and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V-only systems. Specifications for QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-06207. A “hot-link” is provided on our website for downloading. FN6297.0 Features • Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V • Electrically Screened to DSCC SMD#5962-06207 • QML Qualified per MIL-PRF-38535 Requirements • SMD Compliance • Military Temperature Range • Latch-up Free • Hermetic Package • ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000) • Guaranteed Mouse Driveability (ICL3243E) • Requires Single +3.3V ±10% Power Supply • RS-232 Compatible with VCC = 2.7V • Receiver Hysteresis for Improved Noise Immunity • Low Power Automatic Power-down Modes (except for ICL3232E) . . . . . . . . . . . . . . . . . . . . . . . . .1µA • Guaranteed Minimum 250kbps Data Rate • Manual and Automatic Power-down Features • Multiple Drivers/Receivers • On-Chip Voltage Converters Require Only Four External 0.1µF Capacitors • Regulated Dual Charge Pumps Applications Ordering Information DESC P/N CONFIGURATION TEMP (°C) PACKAGE 5962-0620701Q3A ICL3243E 3D/5R -55 to +125 28 Ld CLCC 5962-0620702Q3A ICL3238E 5D/3R -55 to +125 28 Ld CLCC 5962-0620703Q2A ICL3232E 2D/2R -55 to +125 20 Ld CLCC 5962-0620704Q2A ICL3221E 1D/1R -55 to +125 20 Ld CLCC 1 • Any Military or High-Rel System Requiring RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Ruggedized Handheld GPS, Laptop Computers, Notebooks, Palmtops - Industrial Control/Shop Floor Communications - Field Deployed Sensors/Devices Exposed to Extreme Temperature/Humidity - Ruggedized Cellular/Mobile Phones CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Pinouts GND C1+ 16 R1IN 6 V- 7 15 NC NC 8 14 FORCEON 14 T1IN NC 8 NC NC 9 10 11 12 13 10 11 12 13 T1IN 15 R1OUT V- 7 16 T1OUT T2IN 17 GND R2OUT 5 INVALID VCC 17 T1OUT C2- 6 C2+ R1IN V+ 18 NC 18 NC R1OUT NC C1- 4 C2+ 5 4 9 1 20 19 20 19 C1C2- 2 R2IN 1 3 T2OUT EN 2 ICL3232E (CLCC) TOP VIEW VCC C1+ 3 FORCEOFF V+ ICL3221E (CLCC) TOP VIEW 26 VCC 27 V+ VCC 28 C1+ V+ 1 C2+ C1+ 2 GND C2+ 3 C2- C2- 4 V- V- ICL3238E (CLCC) TOP VIEW R1 IN ICL3243E (CLCC) TOP VIEW 4 3 2 1 28 27 26 6 24 T1 IN R4 IN 7 23 FORCEON T3 OUT 7 23 T2 IN R5 IN 8 22 FORCEOFF 8 22 T3 IN T1 OUT 9 21 INVALID 9 21 R1 OUT T2 OUT 10 20 R2OUTB 10 20 R2 OUT T3 OUT 11 19 R1 OUT 11 19 T4 IN 14 15 16 17 18 2 T4 OUT R3 IN 12 13 14 15 16 17 18 R3 OUT 13 R2 IN T5 OUT 12 R1 IN T5 IN T2 OUT R1OUTB C1- INVALID 24 FORCEOFF 6 FORCEON R3 IN R2 OUT 25 C1- R3 OUT 5 R4 OUT T1 OUT R5 OUT GND T1 IN 25 T2 IN 5 T3 IN R2 IN FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Pin Descriptions PIN FUNCTION VCC System power supply input (3.0V to 3.6V). V+ Internally generated positive transmitter supply (+5.5V). V- Internally generated negative transmitter supply (-5.5V). GND Ground connection. C1+ External capacitor (voltage doubler) is connected to this lead. C1- External capacitor (voltage doubler) is connected to this lead. C2+ External capacitor (voltage inverter) is connected to this lead. C2- External capacitor (voltage inverter) is connected to this lead. TIN TTL/CMOS compatible transmitter Inputs. (Note 1) TOUT ±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs. RIN ±15kV ESD Protected, RS-232 compatible receiver inputs. ROUT TTL/CMOS level receiver outputs. ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs. INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input. EN Active low receiver enable control; doesn’t disable ROUTB outputs. FORCEOFF Active low control to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Tables 1 & 2, Note 1). FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high, Note 1). NOTE: 1. The ICL3238E input pins incorporate positive feedback resistors. Once the input is driven to a valid logic level, the feedback resistor maintains that logic level until VCC is removed. Unused transmitter inputs may be left unconnected by the user. TABLE 1. POWER-DOWN LOGIC TRUTH TABLE RCVR OR XMTR EDGE WITHIN 30 SEC? FORCEOFF FORCEON TRANSMITTER RECEIVER INPUT INPUT OUTPUTS OUTPUTS ROUTB OUTPUT RS-232 LEVEL PRESENT AT RECEIVER INPUT? INVALID OUTPUT MODE OF OPERATION ICL3238E No H H Active Active Active No L No H H Active Active Active Yes H Yes H L Active Active Active No L Yes H L Active Active Active Yes H No H L High-Z Active Active No L No H L High-Z Active Active Yes H X L X High-Z High-Z Active No L X L X High-Z High-Z Active Yes H 3 Normal Operation (Enhanced Auto Power-down Disabled) Normal Operation (Enhanced Auto Power-down Enabled) Power-down Due to Enhanced Auto Power-down Logic Manual Power-down FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A TABLE 1. POWER-DOWN LOGIC TRUTH TABLE (Continued) RCVR OR XMTR EDGE WITHIN 30 SEC? FORCEOFF FORCEON TRANSMITTER RECEIVER INPUT INPUT OUTPUTS OUTPUTS ROUTB OUTPUT RS-232 LEVEL PRESENT AT RECEIVER INPUT? INVALID OUTPUT MODE OF OPERATION INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWER-DOWN) X Note 2 Note 2 Active Active Active Yes H Normal Operation X Note 2 Note 2 High-Z High-Z Active No L Forced Auto Power-down NOTE: 2. Input is connected to INVALID Output. TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE RS-232 SIGNAL PRESENT AT RECEIVER INPUT? (NOTE 3) FORCEOFF FORCEON ROUTB EN TRANSMITTER RECEIVER INVALID INPUT INPUT INPUT OUTPUTS OUTPUTS OUTPUTS OUTPUT MODE OF OPERATION ICL3221E No H H L Active Active N.A. L Normal Operation (Auto Power-down Disabled) No H H H Active High-Z N.A. L Yes H L L Active Active N.A. H Yes H L H Active High-Z N.A. H No H L L High-Z Active N.A. L No H L H High-Z High-Z N.A. L Yes L X L High-Z Active N.A. H Manual Power-down Yes L X H High-Z High-Z N.A. H Manual Power-down w/Rcvr. Disabled No L X L High-Z Active N.A. L Manual Power-down No L X H High-Z High-Z N.A. L Manual Power-down w/Rcvr. Disabled No H H N.A. Active Active Active L Normal Operation (Auto Power-down Disabled) Yes H L N.A. Active Active Active H Normal Operation (Auto Power-down Enabled) No H L N.A. High-Z Active Active L Power-down Due to Auto Power-down Logic Yes L X N.A. High-Z High-Z Active H Manual Power-down No L X N.A. High-Z High-Z Active L Manual Power-down Normal Operation (Auto Power-down Enabled) Power-down Due to Auto Power-down Logic ICL3243E NOTE: 3. Applies only to the ICL3243E. 4 FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Absolute Maximum Ratings Thermal Information VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, FORCEOFF, FORCEON, EN . . . . . . . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating (Receiver Input and Transmitter Output Pins) . . .±15kV Thermal Resistance (Typical) θJA (°C/W) 20 Ld CLCC Package . . . . . . . . . . . . . . . . . . . . . . . 90 28 Ld CLCC Package . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Ceramic Package) . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Operating Conditions Temperature Range ICL32XXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications ICL3221E, ICL3232E, ICL3243E Test Conditions: VCC = 3V to 3.6V, C1 - C4 = 0.1mF; Unless Otherwise Specified. Typicals are at TA = 25°C, VCC = 3.3V PARAMETER TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS Full - 1 10 µA DC CHARACTERISTICS Supply Current, Automatic Power- All RIN Open, FORCEON = GND, FORCEOFF = VCC down (ICL3221E, ICL3243E Only) Supply Current, Power-down FORCEOFF = GND (Except ICL3232E) Full - 1 10 µA Supply Current, Power-up VCC = 3.15V, All Outputs Unloaded, FORCEON = FORCEOFF = VCC ICL3221E/ICL3232E Full - 0.3 1.8 mA Full - 0.3 1.8 mA VCC = 3.0V, ICL3243E LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN Full - - 0.8 V Input Logic Threshold High TIN, FORCEON, FORCEOFF, EN Full 2.0 - - V Input Leakage Current TIN, FORCEON, FORCEOFF, EN Full - ±0.01 ±10 µA Output Leakage Current (Except ICL3232E) FORCEOFF = GND or EN = VCC Full - ±0.05 ±10 µA Output Voltage Low IOUT = 1.6mA Full - - 0.4 V Output Voltage High IOUT = -1.0mA Full - V VCC -0.6 VCC -0.1 AUTOMATIC POWER-DOWN (ICL3221E, ICL3243E Only, FORCEON = GND, FORCEOFF = VCC) Receiver Input Thresholds to Enable Transmitters Powers Up Full -2.7 - 2.7 V Receiver Input Thresholds to Disable Transmitters Powers Down Full -0.3 - 0.3 V INVALID Output Voltage Low IOUT = 1.6mA Full - - 0.4 V INVALID Output Voltage High IOUT = -1.0mA Full VCC-0.6 - - V Input Voltage Range Full -25 - 25 V Input Threshold Low Full 0.6 1.2 - V Input Threshold High Full - 1.5 2.4 V Input Resistance Full 3 5 7 kΩ RECEIVER INPUTS TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with 3kW to Ground Full ±5.0 ±5.4 - V Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω 5 FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Electrical Specifications ICL3221E, ICL3232E, ICL3243E Test Conditions: VCC = 3V to 3.6V, C1 - C4 = 0.1mF; Unless Otherwise Specified. Typicals are at TA = 25°C, VCC = 3.3V (Continued) TEMP (°C) MIN TYP MAX UNITS Full - ±35 ±60 mA Full - - ±25 µA T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kW to GND, T1OUT and T2OUT Loaded with 2.5mA Each Full ±5 - - V Maximum Data Rate RL = 3kW, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps Transmitter Skew tPHL - tPLH Full - 200 1000 ns Receiver Skew tPHL - tPLH Full - 100 1000 ns Transition Region Slew Rate VCC = 3.3V, RL = 3kW to 7kW, Measured From 3V to -3V or -3V to 3V PARAMETER TEST CONDITIONS Output Short-Circuit Current VOUT = ±12V, VCC = 0V or 3V to 3.6V (ICL3232E,VCC = 0 only) Automatic Power-down or FORCEOFF = GND Output Leakage Current MOUSE DRIVEABILITY (ICL3243 Only) Transmitter Output Voltage TIMING CHARACTERISTICS CL = 200pF to 2500pF Full 4 8.0 30 V/µs CL = 200pF to 1000pF Full 6 - 30 V/µs ESD PERFORMANCE RS-232 Pins (TOUT, RIN) All Other Pins Electrical Specifications Human Body Model (MIL-STD 883 Method 3015) 25 - ±15 - kV IEC61000-4-2 Contact Discharge 25 - ±8 - kV IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV Human Body Model (MIL-STD 883 Method 3015) 25 - ±2 - kV ICL3238E Test Conditions: VCC = 3V to 3.6V, C1 - C4 = 0.1µF, Unless Otherwise Specified. Typicals are at TA = 25°C, VCC = 3.3V PARAMETER TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS DC CHARACTERISTICS Supply Current, Automatic Power-down All RIN Open, FORCEON = GND, FORCEOFF = VCC Full - 1 10 µA Supply Current, Power-down FORCEOFF = GND Full - 1 10 µA Supply Current, Power-up All Outputs Unloaded, FORCEON = FORCEOFF = VCC Full - 0.3 1.8 mA LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low TIN, FORCEON, FORCEOFF Wake up Threshold Full - - 0.8 V Input Logic Threshold High TIN, FORCEON, FORCEOFF Wake up Threshold Full 2.0 - - V Input Leakage Current TIN, FORCEON, FORCEOFF, VIN = 0V or VCC (Note 4) Full - ±0.01 ±10 µA Output Leakage Current FORCEOFF = GND Full - ±0.05 ±10 µA Output Voltage Low IOUT = 1.0mA Full - - 0.4 V Output Voltage High IOUT = -1.0mA Full - V VCC -0.6 VCC -0.1 RECEIVER INPUTS Input Voltage Range Full -25 - 25 V Input Threshold Low Full 0.8 1.5 - V Input Threshold High Full - 1.8 2.4 V Input Resistance Full 3 5 7 kΩ 6 FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Electrical Specifications ICL3238E Test Conditions: VCC = 3V to 3.6V, C1 - C4 = 0.1µF, Unless Otherwise Specified. Typicals are at TA = 25°C, VCC = 3.3V (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN TYP MAX UNITS ENHANCED AUTOMATIC POWER-DOWN (FORCEON = GND, FORCEOFF = VCC) Receiver Input Thresholds to INVALID High Powered Up Full -2.7 - 2.7 V Receiver Input Thresholds to INVALID Low Powered Down Full -0.3 - 0.3 V INVALID Output Voltage Low IOUT = 1.0mA Full - - 0.4 V INVALID Output Voltage High IOUT = -1.0mA Full VCC-0.6 - - V All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V Full - ±35 ±60 mA VOUT = ±12V, VCC = 0V or 3V to 3.6V, Automatic Power-down or FORCEOFF = GND Full - - ±25 µA Maximum Data Rate RL = 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps Transmitter Skew tPHL - tPLH Full - 200 1000 ns Receiver Skew tPHL - tPLH Full - 100 1000 ns Transition Region Slew Rate VCC = 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or -3V to 3V CL = 150pF to 1000pF Full 6 15 30 V/µs CL = 150pF to 2500pF Full 4 12 30 V/µs IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV IEC61000-4-2 Contact Discharge 25 - ±8 - kV Human Body Model (MIL-STD 883 Method 3015) 25 - ±15 - kV Human Body Model (MIL-STD 883 Method 3015) 25 - ±2.5 - kV TRANSMITTER OUTPUTS Output Voltage Swing Output Short-Circuit Current Output Leakage Current TIMING CHARACTERISTICS ESD PERFORMANCE RS-232 Pins (TOUT, RIN) All Other Pins NOTE: 4. These inputs utilize a positive feedback resistor. The input current is negligible when the input is at either supply rail. Die Characteristics INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorous Silicon Glass) Thickness: 13.0kÅ ± 1.0kÅ Top Metallization: Type: AlSiCu Thickness: 10.0kÅ ± 1kÅ ASSEMBLY RELATED INFORMATION: Substrate Potential: GND ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: ICL3221E: 286 ICL3232E: 296 ICL3243E: 464 ICL3238E: 1235 Process: Si Gate CMOS All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Ceramic Leadless Chip Carrier Packages (CLCC) J28.A MIL-STD-1835 CQCC1-N28 (C-4) 28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 SYMBOL j x 45o E3 B E h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 -E- B1 L e -H- L3 MILLIMETERS MAX MAX NOTES A 0.060 0.100 1.52 2.54 6, 7 0.050 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.442 0.460 11.23 11.68 - D1 0.300 BSC 7.62 BSC - D2 0.150 BSC 3.81 BSC - D3 - 0.460 E 0.442 0.460 11.23 11.68 2 11.68 - E1 0.300 BSC 7.62 BSC - E2 0.150 BSC 3.81 BSC - E3 e - 0.460 0.050 BSC 0.015 - - 11.68 2 1.27 BSC 0.38 - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.90 2.41 - L3 0.003 0.015 0.08 0.038 - ND 7 7 3 NE 7 7 3 N 28 28 -F- 3 Rev. 0 5/18/94 B3 E1 E2 MIN A1 e1 0.007 M E F S H S MIN 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L2 B2 L1 D2 e1 D1 NOTES: 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 8 FN6297.0 May 31, 2006 5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A Ceramic Leadless Chip Carrier Packages (CLCC) J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 SYMBOL j x 45o E3 B E h x 45o 0.010 S E F S A PLANE 2 PLANE 1 -E- L e -H- L3 NOTES 0.060 0.100 1.52 2.54 6, 7 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.342 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC D2 0.100 BSC 2.54 BSC D3 - 0.358 - E 0.342 0.358 8.69 0.200 BSC E2 0.100 BSC E3 - e e1 0.358 0.050 BSC 0.015 - 0.040 REF 0.020 REF - 9.09 2 9.09 - 5.08 BSC - 2.54 BSC - - 9.09 2 1.27 BSC 0.38 - 2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 5 5 NE 5 5 3 N 20 20 3 3 Rev. 0 5/18/94 -FB3 E1 E2 MAX 0.050 j B1 MIN A h 0.007 M E F S H S MILLIMETERS MAX A1 E1 A1 MIN L2 B2 L1 D2 e1 D1 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 9 FN6297.0 May 31, 2006