ISL45041 ® Data Sheet August 12, 2010 TFT-LCD I2C Programmable VCOM Calibrator Features • 128-Step Adjustable Sink Current Output The VCOM voltage of an LCD panel needs to be adjusted to remove flicker. This part provides a digital interface to control the sink-current output that attaches to an external voltage divider. The increase in output sink current lowers the voltage on the external divider, which is applied to an external VCOM buffer amplifier. The desired VCOM setting is loaded from an external source via a standard 2-wire I2C serial interface. At power up, the part automatically comes up at the last programmed EEPROM setting. An external resistor attaches to the SET pin and sets the full-scale sink current that determines the lowest voltage of the external voltage divider. The ISL45041 is available in an 8 Ld 3mmx3mm TDFN package with a maximum thickness of 0.8mm for ultra thin LCD panel design. An evaluation kit complete with software to control the DCP from a computer is available. Reference Application Note AN1275 and “Ordering Information”. • 2.25V to 3.6V Logic Supply Voltage Operating Range (2.25V Minimum Programming Voltage) • Analog Supply Voltage Range 4.5V to 18V for VDD from 2.6V to 3.6V; 4.5V to 13V for VDD from 2.25V to 2.6V • I2C Interface (Slave and Transmitter) - Address: 1001111 • On-Board 7-Bit EEPROM • Output Adjustment SET Pin • Output Guaranteed Monotonic Over-Temperature • Thin 8 Ld 3mmx3mm DFN (0.8mm max) • Pb-free (RoHS compliant) Applications • LCD Panels Pinout ISL45041 (8 LD TDFN) TOP VIEW Ordering Information PART NUMBER (Note) TEMP. RANGE PART MARKING (°C) PACKAGE (Pb-Free) FN6189.3 PKG. DWG. # OUT 1 8 SET AVDD 2 7 SCL ISL45041IRZ 041Z 0 to +85 8 Ld 3x3 TDFN L8.3X3A WP 3 6 SDA ISL45041IRZ-T* 041Z 0 to +85 8 Ld 3x3 TDFN L8.3X3A Tape and Reel GND 4 5 VDD ISL45041EVAL1Z Evaluation Board *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL45041 Pin Descriptions PIN TYPE PULL U/D OUT Output Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function description for the maximum adjustable sink current setting. AVDD Supply High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor. WP Input GND Supply Ground connection. VDD Supply System power supply input. Bypass to GND with 0.1µF capacitor. SDA In/Out I2C Serial Data Input and Output. SCL Input I2C Clock Input SET Analog Pull-Down FUNCTION Write Protect. Active Low. To enable programming, connect to 0.7*VDD supply or greater. The WP pin is designed for static control. It has an internal pull-down 150k resistor. To avoid possibly over-writing the EEPROM contents, no frequency above 1Hz should be applied to this input. Care should be taken to avoid any glitches on the input. When removing or applying mechanical jumpers, always ensure the VDD power is off. A high to low transition on the WP pin results in the register contents being loaded with EEPROM data. Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. Block Diagram ISL45041 AVDD OUT SCL 128 D<7:0> SDA I2C INTERFACE DATA REGISTERS ANALOG DCP AND CURRENT OUTPUT BLOCK SET WP 7-BIT EEPROM GND VDD 2 FN6189.3 August 12, 2010 ISL45041 Absolute Maximum Ratings Thermal Information VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V Input Voltages to GND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V Output Voltages to GND OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V ESD Rating HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV HBM for Input Pins (SCL, SDA) . . . . . . . . . . . . . . . . . . . . . . . .4kV Thermal Resistance (Typical, Note 1) θJA (°C/W) 8 Ld TDFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 170 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified. Typicals are at TA = +25°C PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 7) TYP MAX (Note 7) UNITS DC CHARACTERISTICS VDD Supply Range - Operating VDD Full 2.25 - 3.6 V VDD Supply Range - EEPROM Programming VDD Full 2.25 - 3.6 V VDD Supply Current IDD (Note 4) Full - - 50 µA AVDD Supply Range AVDD VDD Range 2.6V to 3.6V Full 4.5 - 18 V VDD Range 2.25V to 2.6V Full 4.5 - 13 V (Note 2) Full - - 25 µA Full 7 7 7 Bits Full - - ±1 LSB AVDD Supply Current IAVDD SET Voltage Resolution SETVR SET Differential Nonlinearity SETDN SET Zero-Scale Error SETZSE Full - - ±2 LSB SET Full-Scale Error SETFSE Full - - ±8 LSB SET Current ISET SET External Resistance SETER Monotonic Over-Temperature Through RSET (Note 5) Full - 20 - µA To GND, AVDD = 20V Full 10 - 200 kΩ To GND, AVDD = 4.5V Full 2.25 - 45 kΩ AVDD to SET Voltage Attenuation AVDD to SET (Note 3) Full - 1:20 - V/V OUT Settling Time OUTST to ±0.5 LSB Error Band (Note 3) Full - 8 - µs OUT Voltage Range VOUT SET Voltage Drift SETVD (Note 3) Full VSET + 0.5V - 13 V 25 to 55 - <10 - mV SDA, SCL, WP Input Logic High VIH Full 0.7*VDD - - V SDA, SCL, WP Input Logic Low VIL Full - - 0.3*VDD V Full - 0.22*VDD - V Full 15 25 35 µA SDA, SCL, WP Hysteresis (Note 3) WP Input Current ILWPN SDA, SCL Logic High VOHS @ 3mA Full 0.4 - - V SDA, SCL Logic Low VOLS @ 3mA Full - - 0.4 V 3 FN6189.3 August 12, 2010 ISL45041 Electrical Specifications Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified. Typicals are at TA = +25°C (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 7) TYP MAX (Note 7) UNITS I2C SCL Clock Frequency FSCL Full 0 - 400 kHz I2C Clock High Time tSCH Full 0.6 - - µs I2C Clock Low Time tSCL Full 1.3 - - µs I2C Spike Rejection Filter Pulse Width tDSP Full 0 - 50 ns I2C Data Set-up Time tSDS Full 100 - - ns I2C Data Hold Time tSDH Full 0 - 900 ns I2C SDA, SCL Input Rise Time tICR Dependent on Load (Note 6) Full - 20 + 0.1*Cb 1000 ns I2C SDA, SCL Input Fall Time tICF (Note 6) Full - 20 + 0.1*Cb 300 ns I2C Bus Free Time Between Stop and tBUF Full 1.3 - - µs I2C Repeated Start Condition Set-up tSTS Full 0.6 - - µs I2C Repeated Start Condition Hold tSTH Full 0.6 - - µs I2C Stop Condition Set-up tSPS Full 0.6 - - µs I2C Bus Capacitive Load Cb Full - - 400 pF Capacitance on SDA CSDA Full - - 10 pF Capacitance on SCL CS Full - - 10 pF - - 22 pF Write Cycle Time tW - - 100 ms Start WP = 0 WP = 1 Full NOTES: 2. Tested at AVDD = 20V. 3. Simulated and Determined via Design and NOT Directly Tested. 4. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply. 5. A Typical Current of 20µA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. Reference “RSET Resistor” on page 5. 6. Simulated and Designed According to I2C Specifications. 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 4 FN6189.3 August 12, 2010 ISL45041 Application Information TABLE 1. (Continued) This device provides the ability to reduce the flicker of an LCD panel by adjustment of the VCOM voltage during production test and alignment. A 128-step resolution is provided under digital control, which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. AVDD SETTING VALUE VOUT 60 4.453 70 4.281 80 4.109 90 3.936 100 3.764 110 3.592 128 3.282 AVDD ISL45041 R1 + OUT SET RSET RSET Resistor R2 IOUT FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE The adjustment of the output is provided by the 2-wire I2C serial interface. Expected Output Voltage The ISL45041 provides an output sink current, which lowers the voltage on the external voltage divider (VCOM output voltage). Equation 1 and Equation 2 can be used to calculate the output current (IOUT) and output voltage (VOUT) values. AV DD Setting I OUT = --------------------- x --------------------------20 ( R SET ) 128 (EQ. 1) R1 ⎛ R2 ⎞ ⎛ ⎞ Setting V OUT = ⎜ ---------------------⎟ AV DD ⎜ 1 – --------------------- x ---------------------------⎟ R + R 20 ( R ) 128 ⎝ 1 ⎝ 2⎠ SET ⎠ (EQ. 2) The external RSET resistor sets the full-scale sink current that determines the lowest voltage of the external voltage divider R1 and R2 (Figure 1). The voltage difference between the OUT pin and SET pin (Figure 2) has to be greater than 1.75V. This will keep the output MOS transistor in the saturation region. Expected current settings and 7-Bit accuracy occurs when the output MOS transistor is operating in the saturation region. Figure 2 shows the internal connection for the output MOS transistor. The value of the AVDD supply sets the voltage at the source of the output transistor. This voltage is equal to (Setting/128) x (AVDD/20). The ISET current is therefore equal to (Setting/128) x (AVDD/20 x RSET). The value of the Drain voltage is found using Equation 2. The values of R1 and R2 (Equation 2) should be determined (setting equal to 128) so the minimum value of VOUT is greater than 1.75V + AVDD/20. SETTING AV DD ----------------------------x -----------------128 20 OUT PIN R1 NOTE: Where setting is an integer between 1 and 128. Table 1 gives the calculated value of VOUT for the evaluation board using the on-board resistors values of: RSET = 24.9k, R1 = 200k, R2 = 243k, and AVDD = 10V. AVDD VSAT 0.5V RSET TABLE 1. SETTING VALUE VOUT 1 5.468 10 5.313 20 5.141 30 4.969 40 4.797 50 4.625 AVDD = 15V R2 SET PIN FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE Ramp-Up of the VDD Power Supply It is required that the ramp-up from 10% VDD to 90% VDD level be achieved in less than or equal to 10ms to assure that the EEPROM and Power-on-reset circuits are synchronized and the correct value is read from the EEPROM Memory. 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For information regarding Intersil Corporation and its products, see www.intersil.com 5 FN6189.3 August 12, 2010 I2C Timing Diagram Figure 3 shows the I2C timing diagram and expected scope photos of SCL and SDA when writing all zeros or all ones. 4 7-BIT ADDRESS 9 F 0 TO WRITE TO EEPROM 8-BIT ADDRESS E I2C Slave Address 6 ISL45041 FN6189.3 August 12, 2010 FIGURE 3. ISL45041 I2C TIMING DIAGRAM ISL45041 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 ( 1.95) A B 3.00 ( 8X 0.50) 6 PIN 1 INDEX AREA (4X) (1.50) ( 2.90 ) 0.15 PIN 1 TOP VIEW (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL "X" 2X 1.950 PIN #1 INDEX AREA 0.10 C 0.75 ±0.05 6X 0.65 C 0.08 C 1 SIDE VIEW 6 1.50 ±0.10 8 8X 0.30 ±0.05 8X 0.30 ± 0.10 2.30 ±0.10 C 4 0.10 M C A B 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" BOTTOM VIEW NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. either a mold or mark feature. 7 FN6189.3 August 12, 2010