SPICE Device Model Si9433BDY www.vishay.com Vishay Siliconix P-Channel 20 V (D-S) MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C to 125 °C temperature ranges under the pulsed 0 V to 5 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the - 55 °C to + 125 °C Temperature Range • Model the Gate Charge SUBCIRCUIT MODEL SCHEMATIC D 4 R1 M2 G 3 1 DBD 2 CGS M1 S Note • This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. S13-0598-Rev. C, 25-Mar-13 1 Document Number: 72773 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model Si9433BDY www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS SIMULATED MEASURED DATA DATA UNIT Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA 1.2 - V On-State Drain Currenta ID(on) VDS = - 5 V, VGS = - 4.5 V 78 - A Drain-Source On-State Resistancea RDS(on) VGS = - 4.5 V, ID = - 6.2 A 0.026 0.030 VGS = - 2.7 V, ID = - 5 A 0.043 0.050 Forward Transconductancea gfs VDS = - 10 V, ID = - 6.2 A 13 15 S Diode Forward Voltage VSD IS = - 2.6 A, VGS = 0 V - 0.82 - 0.76 V 8 8.8 VDS = - 6 V, VGS = - 4.5 V, ID = - 6.2 A 1.8 1.8 2.4 2.4 Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = - 6 V, RL = 6 ID = - 1 A, VGEN = - 4.5 V, Rg = 6 tf 58 40 29 55 58 65 18 30 nC ns Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. S13-0598-Rev. C, 25-Mar-13 2 Document Number: 72773 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model Si9433BDY www.vishay.com Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted) Note • Dots and squares represent measured data. S13-0598-Rev. C, 25-Mar-13 3 Document Number: 72773 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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