10-Bit, 80 MSPS, High Speed, Low Power D/A Converter August 1997 Features Description • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 80 MSPS The HI5780 is a 10-bit, 80 MSPS, high speed, low power CMOS D/A converter. The converter incorporates a 10-bit input data register with current outputs. The HI5780 includes a power down feature that reduces power consumption and a blanking control. The on-chip bandgap reference can be used to set the output current range of the D/A. • Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mW • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • TTL/CMOS Compatible Inputs • Built in Bandgap Voltage Reference Ordering Information • Power Down and Blanking Control Pins PART NUMBER • Direct Replacement for Sony CXD2306 TEMP. RANGE (oC) PACKAGE PKG. NO. Q32.7x7-S Applications HI5780JCQ -20 to 75 32 Ld MQFP • Wireless Communications HI5780-EV 25 Evaluation Kit • Direct Digital Frequency Synthesis • Signal Reconstruction • Test Equipment • High Resolution Imaging and Graphics Systems • Arbitrary Waveform Generators Pinout AGND NC DGND DVDD NC D0 (LSB) D1 D2 HI5780 (MQFP) 23 IOUT 3 22 VG D6 4 21 AVDD D7 5 20 AVDD D8 6 19 VREF D9 (MSB) 7 18 REFOUT NC 8 17 9 10 11 12 13 14 15 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 10-1716 IREF NC DGND 2 D5 VB D4 DVDD IOUT NC 32 31 30 29 28 27 26 25 24 PD 1 BLK D3 CLK [ /Title (HI578 0) /Subject (10Bit, 80 MSPS, High Speed, Low Power D/A Converter) /Autho r () /Keywords (Intersil Corporation, Semiconductor Communications Division, Intersil Semiconductor, CommLink, HI5780 File Number 4024.4 HI5780 Typical Application Circuit +5V +5V HI5780 0.01µF 0.01µF (20, 21) AVDD DVDD (13, 28) D9 0.1µF D9 (MSB) (7) (22) VG D8 D8 (6) D7 D7 (5) (18) REFOUT D6 D6 (4) (19) VREF D5 D5 (3) D4 D4 (2) D3 D3 (1) D2 D2 (32) D1 D1 (31) D0 D0 (30) 0.1µF (14) VB D/A OUT (24) IOUT 200Ω (23) IOUT CLK (9) (17) IREF BLK (10) 50Ω 2.0kΩ DGND (8, 12,15, 16, 26, 27, 29) (25) AGND PD (11) POWER DOWN CONTROL Functional Block Diagram IOUT (LSB) D0 D1 4 LSB D2 CURRENT CELLS D3 D4 D5 DECODER D6 6 MSB CURRENT CELLS D7 D8 IOUT DATA REGISTER VG DECODER (MSB) D9 CURRENT CELLS (FOR FULL SCALE) BLK CLK CLOCK GENERATOR - + VREF IREF BIAS VOLTAGE GENERATOR VB BANDGAP VOLTAGE REFERENCE PD 10-1717 REFOUT HI5780 Absolute Maximum Ratings Thermal Information Supply Voltage VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Digital Input Voltages (D9-D0, CLK, BLANK, PD) . . . . VDD to -0.5V Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . ±2.5mA Reference Input Voltage Range (VREF) . . . . . . . . . . . . VDD to -0.5 V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Operating Conditions Temperature Range, HI5780BIx . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD , DVDD = 5.00V, VREF = 2.0V, fCLK = 80 MSPS, RLOAD = 200Ω, RREF = 3.3kΩ, TA = 25oC HI5780JCQ PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 10 - - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL (Notes 4, 5) (“Best Fit” Straight Line) -2.0 1.25 2.0 LSB Differential Linearity Error, DNL (Notes 4, 5) -0.5 0.25 0.5 LSB Offset Error, IOS (Notes 4, 5) - - 5 µA Full Scale Output Current, IFS (Note 4) 9.0 9.6 10 mA Full Scale Drift Coefficient, IDRIFT (Note 2) - 0.26 - mV/oC Output Voltage Compliance Range (Note 3), 10-Bit Accuracy 1.8 1.92 2.0 V Throughput Rate (Note 3) 80.0 - - MSPS Output Voltage Full Scale Step Settling Time, tSETT FS To ±0.5 LSB Error Band RL = 75Ω, 10-Bit Accuracy (Note 3) - 6.0 - ns Singlet Glitch Area, GE (Peak) RLOAD = 75Ω, VOUT = 1.0VP-P (Note 3) - 40 - pV-s Differential Gain, DG (Note 4) - 2.5 - % Differential Phase, DP (Note 4) - 1.3 - Degrees Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 40 MSPS, fOUT = 2.02MHz, 20MHz Span (Note 3) - 48.5 - dBc fCLK = 80 MSPS, fOUT = 2.02MHz, 40MHz Span (Note 3) - 47.5 - dBc fCLK = 40 MSPS, fOUT = 10MHz, 20MHz Span (Note 3) - 40.75 - dBc fCLK = 80 MSPS, fOUT = 20MHz, 40MHz Span (Note 3) - 38.5 - dBc fCLK = 40 MSPS, fOUT = 2.02MHz, 2MHz Span (Note 3) - 75.0 - dBc fCLK = 80 MSPS, fOUT = 2.02MHz, 2MHz Span (Note 3) - 73.5 - dBc fCLK = 40 MSPS, fOUT = 10MHz, 2MHz Span (Note 3) - 56.5 - dBc fCLK = 80 MSPS, fOUT = 20MHz, 2MHz Span (Note 3) - 49.0 - dBc 1.0 1.25 1.3 V DYNAMIC CHARACTERISTICS Spurious Free Dynamic Range, SFDR Within a Window REFERENCE Internal Reference Voltage, REFOUT (Notes 4, 5) Internal Reference Voltage Drift (Note 3) - 0.34 - mV/oC Reference Input Voltage Range, VREF (Note 3) 0.5 - 2.0 V 10-1718 HI5780 Electrical Specifications AVDD , DVDD = 5.00V, VREF = 2.0V, fCLK = 80 MSPS, RLOAD = 200Ω, RREF = 3.3kΩ, TA = 25oC (Continued) HI5780JCQ PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (D9-D0, CLK, BLK, PD) Input Logic High Voltage, VIH (Note 5) 2.15 - - V Input Logic Low Voltage, VIL (Note 5) - - 0.85 V Input Logic Current, IIH (Note 5) - - 5 µA Input Logic Current, IIL (Note 5) -5 - - µA Digital Input Capacitance, CIN (Note 3) - 3.0 - pF TIMING CHARACTERISTICS Data Setup Time, tSU (See Figure 1, Note 3) 5.0 3.0 - ns Data Hold Time, tHLD (See Figure 1, Note 3) 1.0 0 - ns Propagation Delay Time, tPD (See Figure 1, Note 3) - 8.0 - ns CLK Pulse Width, tPW1 , tPW2 (See Figure 1, Note 3) 6.25 - - ns POWER SUPPLY CHARACTERISTICS IVDD (Notes 4, 5) - 20 30 mA Power Dissipation (Note 5) - 100 150 mW Sleep Mode Power Consumption PD = 1 (Note 4) - 1.25 - mW NOTES: 2. RLOAD is connected to IOUT (pin 24) and RREF is connected to IREF (pin 17). 3. Parameter guaranteed by design or characterization and not production tested. 4. Typical values are test results at TA = 25oC. 5. All devices are 100% tested at 25oC. Timing Diagrams 50% CLK D9-D0 1/ 2 LSB ERROR BAND GLITCH AREA = 1/2 (H x W) V HEIGHT (H) IOUT tPD tSETT FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM WIDTH (W) t(ps) FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD 10-1719 HI5780 Timing Diagrams (Continued) tPW1 tPW2 50% CLK tSU tSU tSU tHLD tHLD tHLD D9-D0 tSETT tPD 1 /2 LSB CHANGE IOUT 1/ 2 LSB CHANGE tPD tSETT tPD tSETT FIGURE 3. PROPAGATION DELAY, SETUP TIME AND MINIMUM PULSE WIDTH DIAGRAM Pin Descriptions PIN PIN NAME DESCRIPTION 1-7, 30-32 D0 (LSB) thru D9 (MSB) 9 CLK Data Clock Pin 100kHz to 80MHz. 13, 28 DVDD Digital Logic Supply +5V. 15, 27 DGND Digital Ground. 20, 21 AVDD Analog Supply +5V. 23 BLK Output Blanking pin. When set (‘1’) this pin zeros the IOUT pin. 25 AGND 11 PD Power Down Mode pin. This pin when set (‘1’) places the HI5780 in lower power mode and zeros the output. Power consumption is reduced. 24 IOUT Current Output pin. 23 IOUT Complementary Current Output pin. 18 REFOUT Bandgap Reference Voltage Output. 17 IREF Reference Current setting resistor connected from here to Ground. 19 VREF Reference Voltage Input pin. 14 VB Bias Voltage Generator Bypass Capacitor connected from here to Ground. 22 VG Reference Amplifier Bypass Capacitor connected from here to AVDD . Digital Data Bit 0, the least significant bit thru digital data Bit 9, the most significant bit. Analog Ground Supply Current Return pin. 10-1720 HI5780 1.0 2.0 0.75 1.5 0.5 1.0 0.25 0.5 LSB LSB Typical Performance Curves 0 0 -0.25 -0.5 -0.5 -1.0 -0.75 -1.5 -2.0 -1.0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 CODE FIGURE 4. DIFFERENTIAL LINEARITY 700 800 900 1000 FIGURE 5. INTEGRAL LINEARITY (BEST FIT - STRAIGHT LINE) 23 -10 mA 600 CODE 22 -20 21 -30 20 -40 S -50 19 ATTEN 10dB RL -10.0dBm ∆MKR -48.50dB 2.00MHz 10dB/ HI5780 fS = 40 MSPS fO = 2MHz -60 -70 18 -80 17 -90 16 -100 15 10 20 30 40 50 60 70 80 90 START 0Hz RBW 1.0kHz 100 MHz FIGURE 6. POWER SUPPLY CURRENT vs CLOCK FREQUENCY ATTEN 10dB RL -10.0dBm VBW 1.0kHz FIGURE 7. SPURIOUS FREE DYNAMIC RANGE TO NYQUIST ∆MKR -75.00dB 33kHz 10dB/ HI5780 fS = 40 MSPS fO = 2MHz S CENTER 2.000MHz RBW 300Hz STOP 20.00MHz SWP 50.0s VBW 300Hz SPAN 2.000MHz SWP 56.0s FIGURE 8. SPURIOUS FREE DYNAMIC RANGE WITHIN A WINDOW 10-1721 HI5780 Detailed Description Reference The HI5780 is a 10-bit, current out D/A converter. The DAC can convert at 80 MSPS and runs on +5V supplies. The HI5780 achieves its low power and high speed performance from an advanced CMOS process. The HI5780 consumes 150mW (Maximum) and has a power down mode that only consumes 1.25mW when in sleep mode. The HI5780 is an excellent converter to be used for communications applications and high performance video systems. The internal reference in the HI5780 is a 1.25V (typical) bandgap voltage reference. The internal reference is buffered by an amplifier to provide adequate drive for the current cells. Reference Out (REFOUT) is connected to the VREF pin. The Full Scale Output Current is controlled by the resistor connected to IREF . The full scale output voltage, is set by the following equation: VO UT (Full Scale) = V REF x 16 ( R LOAD /R REF ). Digital Inputs The HI5780 is a TTL/CMOS-compatible D/A. Data is latched by a 10-bit latch. Once latched data inputs D0 (LSB) thru D9 (MSB) are decoded to the internal current cells; the internal latch and switching current source controls are implemented in CMOS technology to maintain high switching speeds and low power consumption. Clocks and Termination Applications Voltage Conversion of the Output To convert the output current of the D/A converter to a voltage, an amplifier should be used as shown in Figure 5. The DAC needs a 50Ω termination resistor on the IOUT pin to ensure proper settling. The HFA1110 has an internal feedback resistor to compensate for high frequency operation. The internal 10-bit register is updated on the rising edge of the clock. Since the HI5780 clock rate can run to 80MHz, to minimize reflections and clock noise into the part, proper termination should be used. In PCB layout clock runs should be kept short and have a minimum of loads. To guarantee consistent results from board to board, controlled impedance PCBs should be used with a characteristic line impedance, ZO , of 50Ω . +5V 2 1 HFA1110 HI5780 DAC IOUT 21 50Ω To terminate the clock line a shunt terminator to ground is the most effective type at a 80 MSPS clock rate. A typical value for termination can be determined by the equation: 8 + 4 5 6 50Ω -5.2V FIGURE 10. HIGH SPEED CURRENT TO VOLTAGE CONVERSION RT = Z O , for the termination resistor. For a controlled impedance board with a ZO of 50Ω, the RT = 50Ω. Shunt termination is best used at the receiving end of the transmission line or as close to the HI5780 CLK pin as possible. Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. HI5780 DAC ZO = 50Ω Definition of Specifications CLK RT = 50Ω Output Voltage Full Scale Settling Time, is the time required from the 50% point on the clock input for a full scale step to settle within an 1/2 LSB error band. FIGURE 9. AC TERMINATION OF THE HI5780 CLOCK LINE Rise and Fall times and propagation delay of the line will be affected by the Shunt Terminator. The terminator can be connected to DGND. Noise Reduction To reduce power supply noise, separate analog and digital power supplies should be used with 0.1µF and 0.01µF ceramic capacitors placed as close to the body of the HI5780 as possible on the analog (AVDD) and digital (DVDD) supplies. The analog and digital ground returns should be connected together back at the device to ensure proper operation on power up. Glitch Area, GE, is the switching transient appearing on the output during a code transition. It is measured as the area under the curve and expressed as a Volt-Time specification. Differential Gain, ∆AV , is the gain error from an ideal sine wave with a normalized amplitude. Differential Phase, ∆Φ, is the phase error from and ideal sine wave. Spurious Free Dynamic Range, SFDR, is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. A sine wave is loaded into the D/A and the output filtered at 1/2 the clock frequency to eliminate noise from clocking alias terms. 10-1722 HI5780 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 10-1723