HI5630 Datasheet

HI5630
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Data
March 2003
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8-INT
1-88
®
Triple 8-Bit, 80MSPS A/D Converter with
Internal Voltage Reference
The HI5630 is a monolithic, triple 8-bit, 80MSPS
analog-to-digital converter fabricated in an advanced CMOS
process. It is designed for digitizing RGB graphics from work
stations and personal computers. The HI5630 reaches a
new level of multi-channel integration. The fully pipeline
architecture and an innovative input stage enable the
HI5630 to accept a variety of single-ended or fully differential
input configurations which present valid data to the output
bus with a latency of 5 clock cycles. Only one external clock
is necessary to drive all three converters with a clock out
signal provided. An internal band-gap voltage reference is
also provided allowing the system designer to realize an
increased level of system integration resulting in decreased
cost and power dissipation.
The HI5630 can be bench tested using a complete ADC
evaluation board with clock drivers, ADC, latches and a
reconstruct DAC. In addition, complete LCD monitor
reference designs are available for immediate volume
production (contact factory).
FN4645.3
Features
• Triple 8-Bit A/D Converter on a Monolithic Chip
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 80MSPS
• ENOB (fIN = 1MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 300MHz
• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
• Single Supply Voltage Operation . . . . . . . . . . . . . . . . .+5V
• On-Chip Sample and Hold Amplifiers
• Clock Output
• Offset Binary or Two’s Complement Output Format
• Stand-By Low Power mode
Applications
• LCD Monitors, Projectors and Plasma Display Panels
• Video Digitizing (RGB, Composite or Y-C)
• Medical Imaging
Part Number Information
HI5630
(MQFP)
TOP VIEW
Q64.14x14
ADC Evaluation Platform
N/C
DFS
STBY
AGND
AVDD
25
64 Ld MQFP
Pinout
GD0
BD7
HI5630EVAL1
0 to 70
PKG. NO.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DGND
DVDD
GD1
GD2
GD3
DGND
DVDD
CLKOUT
CLKIN
DVDD
DGND
GD4
GD5
GD6
DVDD
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
BIN +
BIN BVDC
AGND
VRIN
VROUT
AVDD
GIN +
GIN GVDC
AGND
AVDD
RIN +
RIN RVDC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
N/C
GD7
RD0
RD1
RD2
RD3
RD4
DGND
DVDD
RD5
RD6
RD7
N/C
AGND
AVDD
AGND
HI5630/8CN
PACKAGE
BD6
BD5
BD4
BD3
DGND
DVDD
BD2
BD1
BD0
TEMP.
PART NUMBER RANGE (oC)
• High Speed Multi-Channel Data Acquisition
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5630
Functional Block Diagram
DC BIAS
RVDC
RINRIN+
S/H
STAGE M - 6
RD0 (LSB)
RD1
RD2
2-BIT
FLASH
RD3
2-BIT
DAC
RD4
RD5
RD6
+
∑
RD7 (MSB)
-
X2
GD0 (LSB)
GD1
GD2
GD3
GD4
X2
GD5
STAGE M
GD6
GD7 (MSB)
2-BIT
FLASH
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
BD0 (LSB)
BD1
BD2
BD3
GVDC
GINGIN+
BD4
SAME AS
RED ABOVE
BD5
BD6
BD7 (MSB)
BVDC
BINB N+
DFS
SAME AS
RED ABOVE
STBY
CLKIN
CLKOUT
VROUT
VRIN
REFERENCE
POWER
AVDD
2
AGND
DVDD
DGND
HI5630
Typical Video Application Schematic
AVDD
DVDD
HI5630
RIN +
(35) RIN +
(33) RVDC (2V)
(34) RIN -
0.1µF
GIN +
(40) GIN +
(38) GVDC (2V)
(LSB) RD0 (19)
RD0
RD1 (20)
RD1
RD2 (21)
RD2
RD3 (22)
RD3
RD4 (23)
RD4
RD5 (26)
RD5
RD6 (27)
RD6
(MSB) RD7 (28)
RD7
(39) GIN -
0.1µF
DGND
BIN +
(47) BIN +
0.1µF
(LSB) GD0 (64)
GD0
(45) BVDC (2V)
GD1 (3)
GD1
(46) BIN -
GD2 (4)
GD2
GD3 (5)
GD3
GD4 (12)
GD4
GD5 (13)
GD5
GD6 (14)
GD6
(MSB) GD7 (18)
GD7
DGND
(43) VRIN
(42) VROUT
1.0µF
DGND
DVDD
(51) STBY
(52) DFS
(LSB) BD0 (54)
BD0
BD1 (55)
BD1
BD2 (56)
BD2
BD3 (59)
BD3
BD4 (60)
BD4
BD5 (61)
BD5
BD6 (62)
BD6
(MSB) BD7 (63)
BD7
DGND
(9) CLK IN
CLOCK IN
AGND
AGND
DGND
3
CLK OUT (8)
DGND
CLOCK OUT
HI5630
Pin Description
Pin Description
(Continued)
PIN NO.
NAME
Digital Ground
33
RVDC
Digital Supply (5.0V)
34
RIN-
Red Negative Analog Input
GD1
Green Data Bit 1 Output
35
RIN+
Red Positive Analog Input
4
GD2
Green Data Bit 2 Output
36
AVDD
Analog Supply (5.0V)
5
GD3
Green Data Bit 3 Output
37
AGND
Analog Ground
6
DGND
Digital Ground
38
GVDC
Green DC Bias Voltage Output
7
DVDD
Digital Supply (5.0V)
39
GIN-
Green Negative Analog Input
8
CLK OUT
Sample Clock Output
40
GIN+
Green Positive Analog Input
9
CLK IN
Sample Clock Input
41
AVDD
Analog Supply (5.0V)
10
DVDD
Digital Supply (5.0V)
42
VROUT
11
DGND
Digital Ground
43
VRIN
12
GD4
Green Data Bit 4 Output
44
AGND
Analog Ground
13
GD5
Green Data Bit 5 Output
45
BVDC
Blue DC Bias Voltage Output
14
GD6
Green Data Bit 6 Output
46
BIN-
Blue Negative Analog Input
15
DVDD
Digital Supply (5.0V)
47
BIN+
Blue Positive Analog Input
16
DGND
Digital Ground
48
AGND
Analog Ground
17
NC
No Connection
49
AVDD
Analog Supply (5.0V)
18
GD7
Green Data Bit 7 Output
50
AGND
Analog Ground
19
RD0
Red Data Bit 0 Output
51
STBY
Stand-By Power Mode
20
RD1
Red Data Bit 1 Output
52
DFS
Data Format Select Input
21
RD2
Red Data Bit 2 Output
53
NC
No Connection
22
RD3
Red Data Bit 3 Output
54
BD0
Blue Data Bit 0 Output
23
RD4
Red Data Bit 4 Output
55
BD1
Blue Data Bit 1 Output
24
DGND
Digital Ground
56
BD2
Blue Data Bit 2 Output
25
DVDD
Digital Supply (5.0V)
57
DVDD
Digital Supply (5.0V)
26
RD5
Red Data Bit 5 Output
58
DGND
Digital Ground
27
RD6
Red Data Bit 6 Output
59
BD3
Blue Data Bit 3 Output
28
RD7
Red Data Bit 7 Output
60
BD4
Blue Data Bit 4 Output
29
NC
No Connection
61
BD5
Blue Data Bit 5 Output
30
AGND
Analog Ground
62
BD6
Blue Data Bit 6 Output
31
AVDD
Analog Supply (5.0V)
63
BD7
Blue Data Bit 7 Output
32
AGND
Analog Ground
64
GD0
Green Data Bit 0 Output
PIN NO.
NAME
1
DGND
2
DVDD
3
DESCRIPTION
4
DESCRIPTION
Red DC Bias Voltage Output (2.0)
+2.5V Reference Voltage Output
+2.5V Reference Voltage Input
HI5630
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage, AVDD or DVDD to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVDD
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVDD
Thermal Resistance (Typical, Note 1)
Operating Conditions
θJA (oC/W)
MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
Temperature Range
HI5630/8CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a 1S2P (1 Signal and 2 Power) evaluation PC board in free air.
Electrical Specifications
AVDD = 5V, DVDD = 5V; Single Ended Inputs, VRIN = 2.5V; fS = 80MSPS at 50% Duty Cycle; CL = 10pF;
TA = 25oC; Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
-
8
-
Bits
Integral Linearity Error, INL
fIN = 1MHz
-
±0.4
±2.0
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 1MHz
-
±0.2
±1.0
LSB
Channel Offset Match
fIN = DC
-
1
-
LSB
Channel Full Scale Error Match
fIN = DC
-
0.25
-
LSB
Offset Code, VOC
VIN+ = VIN-
-
140
-
CODE
Full Scale Error, FSE
fIN = DC
-
1
-
LSB
-
-
-
s
Bit Error Rate (BER)
ANALOG INPUT
Analog Input Range
(Note 2)
-
0.95
1
V
Analog Input Resistance
VIN+ = VIN- = VREF
-
1
-
MΩ
-
10
-
pF
VIN+ = VIN- = VREF
-10
1.0
10
µA
-
300
-
MHz
2.33
2.5
2.67
V
-
2
4
mA
-
6
-
µV/oC
VDC Output Voltage (Loaded)
-
1.97
-
V
VDC Output Current, IVDC
-
-
-
mA
VDC Temperature Coefficient
-
60
-
µV/oC
Analog Input Capacitance
Analog Input Bias Current
Full Power Input Bandwidth, FPBW
INTERNAL VOLTAGE REFERENCE 1µF Decoupling Cap Needed
Reference Output Voltage, VREF
IREF = 4mA
Reference Output Current, IROUT
V Applied = 2.5V
Reference Temperature Coefficient
DC BIAS PINS RVDC, GVDC, BVDC with 0.1µF Decoupling Cap Needed
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
(Note 2)
2.2
2.5
2.8
V
Total Reference Resistance, RRIN
VRIN = 2.5V
-
2.93
-
kΩ
Reference Current, IRIN
VRIN = 2.5V
-
0.95
-
mA
Minimum Conversion Rate
No Missing Codes
1
-
-
MSPS
Maximum Conversion Rate
No Missing Codes
-
-
80
MSPS
Overclocking Conversion Rate
No Missing Codes
-
95
-
MSPS
-
1
-
Cycle
DYNAMIC CHARACTERISTICS
Transient Response
5
HI5630
Electrical Specifications
AVDD = 5V, DVDD = 5V; Single Ended Inputs, VRIN = 2.5V; fS = 80MSPS at 50% Duty Cycle; CL = 10pF;
TA = 25oC; Unless Otherwise Specified (Continued)
MIN
TYP
MAX
UNITS
Over-Voltage Recovery
PARAMETER
0.2V Overdrive
TEST CONDITIONS
-
1
-
Cycle
Effective Number of Bits, ENOB
fIN = 1MHz (Figure 11)
-
7.6
-
Bits
Signal to Noise and Distortion Ratio, SINAD
fIN = 1MHz
-
47.8
-
dB
Signal to Noise Ratio, SNR
fIN = 1MHz (Figure 12)
-
47.9
-
dB
Total Harmonic Distortion, THD
fIN = 1MHz
-
- 63
-
dB
Spurious Free Dynamic Range, SFDR
fIN = 1MHz (Figure 13)
-
- 64
-
dB
-
75
-
dB
-
4
-
V
Channel Crosstalk
SAMPLING CLOCK INPUT Note 3
Input Logic High Voltage, VIH
Figure 10
Input Logic Low Voltage, VIL
Figure 10
-
0.4
-
V
Input Logic High Current, IIH
VIH = 4.5V
-10.0
-
+10.0
µA
Input Logic Low Current, IIL
VIL = 0V
-10.0
-
+10.0
µA
-
7
-
pF
-
-
V
Input Capacitance, CIN
CLOCK OUTPUT CL = 10pF (Note 3)
Output Logic High Voltage, VOH
IOH = 100µA
4.0
Output Logic Low Voltage, VOL
IOL = 100µA
-
-
0.8
V
-
7
-
pF
-
-
V
Output Capacitance, CCOUT
DIGITAL OUTPUTS CL = 10pF (Note 3)
Output Logic High Voltage, VOH
IOH = 100µA; DVDD = 5V
4.0
Output Logic Low Voltage, VOL
IOL = 100µA; DVDD = 5V
-
-
0.8
V
-
7
-
pF
Output Capacitance, CDOUT
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample
-
5
-
Cycles
Power-Up Initialization
Data Invalid Time
-
-
20
Cycles
-
-
-
ns
-
-
-
ns
-
±5
-
%
Analog Supply Voltage, AVDD
4.75
5.0
5.25
V
Digital Supply Voltage, DVDD
Sample Clock Pulse Width (Low)
Sample Clock Pulse Width (High)
Sample Clock Duty Cycle Variation
Figure 9
POWER SUPPLY CHARACTERISTICS
4.75
5.0
5.25
V
Supply Current, ITOTAL
-
348
-
mA
Analog Current, IAVDD
-
235
265
mA
Digital5 Current, IDVDD
-
113
-
mA
Power Dissipation
-
1.74
-
W
Standby Current
-
8
-
mA
Standby Power
-
40
-
mW
Offset Error PSRR, ∆VOS
AVDD or DVDD = 5V ±5%
-
±0.4
-
LSB
Gain Error PSRR, ∆FSE
AVDD or DVDD = 5V ±5%
-
±0.15
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
6
HI5630
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1
SN + 2
SN + 5 HN + 5
S N + 6 HN + 6 S N + 7
HN + 7 S N + 8
HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1 , N - 1
B2 , N - 2
6TH
STAGE
B1 , N
B2 , N - 1
B9 , N - 5
DATA
OUTPUT
B1 , N + 1
B1 , N + 4
B2 , N + 4
B2 , N
B9 , N - 4
DN - 4
B1 , N + 5
B9 , N
DN - 3
B1 , N + 6
B2 , N + 5
B9 , N + 1
DN - 1
DN
NOTES:
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM , N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. HI5630 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
1.5V
1.5V
tOD
tH
DATA
OUTPUT
2.4V
DATA N-1
DATA N
0.5V
FIGURE 2. HI5630 INPUT-TO OUTPUT TIMING
7
B2 , N + 6
B9 , N + 2
tLAT
CLOCK
INPUT
B1 , N + 7
B9 , N + 3
DN + 1
DN + 2
HI5630
Detailed Description
Theory of Operation
The HI5630 is a triple 8-Bit fully differential sampling pipeline
A/D converter with digital error correction logic. Each of the
three channels are identical so this discussion will only cover
one channel. Figure 3 depicts the circuit for the front end
differential-in-differential-out sample-and-hold (S/H). The
switches are controlled by an internal sampling clock which
is a non-overlapping two phase signal, Φ1 and Φ2 , derived
from the master sampling clock. During the sampling phase,
Φ1 , the input signal is applied to the sampling capacitors,
CS . At the same time the holding capacitors, CH , are
discharged to analog ground. At the falling edge of Φ1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase, Φ2 , the two bottom
plates of the sampling capacitors are connected together
and the holding capacitors are switched to the op amp
output nodes. The charge then redistributes between CS
and CH completing one sample-and-hold cycle. The front
end sample-and-hold output is a fully-differential, sampleddata representation of the analog input. The circuit not only
performs the sample-and-hold function but will also convert
a single-ended input to a fully-differential output for the
converter core. During the sampling phase, the VIN pins see
only the on-resistance of a switch and CS . The relatively
small values of these components result in a typical full
power input bandwidth of 250MHz for the converter.
Φ1
VIN+
Φ1
Φ1
Φ1
CS
Φ2
VIN-
CH
-+
VOUT+
+-
VOUT-
CS
Φ1
CH
Φ1
which is controlled by the internal sampling clock. The
function of the digital delay line is to time align the digital
outputs of the identical two-bit subconverter stages with the
corresponding output of the last stage flash converter before
applying the results to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final
ten bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 5th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
buffered latching technique. The digital output data is
available in two’s complement or offset binary format
depending on the state of the Data Format Select (DFS)
control input (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VROUT
The HI5630 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. VROUT must be connected to VRIN when using the
internal reference voltage. An internal band-gap reference
voltage followed by an amplifier/buffer generates the
precision +2.5V reference voltage used by the converter. A
8:1 array of substrate PNPs generates the “delta-VBE” and a
two-stage op amp closes the loop to create an internal
+1.25V band-gap reference voltage. This voltage is then
amplified by a wide-band uncompensated operational
amplifier connected in a gain-of-two configuration. An
external, user-supplied, 1µF capacitor connected from the
VROUT output pin to analog ground is used to set the dominant
pole and to maintain the stability of the operational amplifier.
Reference Voltage Input, VRIN
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram, identical pipeline subconverter stages, each
containing a two-bit flash converter and a two-bit multiplying
digital-to-analog converter, follow the S/H circuit with the last
stage being a two bit flash converter. Each converter stage
in the pipeline will be sampling in one phase and amplifying
in the other clock phase. Each individual subconverter clock
signal is offset by 180 degrees from the previous stage clock
signal resulting in alternate stages in the pipeline performing
the same operation.
The output of each of the identical two-bit subconverter
stages is a two-bit digital word containing a supplementary
bit to be used by the digital error correction logic. The output
of each subconverter stage is input to a digital delay line
8
The HI5630 is designed to accept a +2.5V reference voltage
source at the VREF IN input pin. Typical operation of the
converter requires VRIN to be set at +2.5V. The HI5630 is
tested with VRIN connected to VROUT yielding a fully
differential analog input voltage range of ±0.5V.
The user does have the option of supplying an external
+2.5V reference voltage. As a result of the high input
impedance presented at the VRIN input pin, 3.0kΩ typically,
the external reference voltage being used is only required to
source 1mA of reference input current. In the situation where
an external reference voltage will be used an external 1µF
capacitor must be connected from the VROUT output pin to
analog ground in order to maintain the stability of the internal
operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VRIN .
HI5630
DC Voltage Source, VDC
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.0V DC voltage
source to the user to help simplify circuit design. The
characteristics of the DC source is equivalent to the internal
reference.
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
VIN+
VIN+
VDC
R
Analog Input, Differential Connection
The analog input to the HI5630 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figures 4 and 5) will deliver the best
performance from the converter.
VIN+
VIN+
R
HI5630
C
HI5630
VDC
VIN-
R
VDC
VIN-
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
Analog Input, Single-Ended Connection
The configuration shown in Figure 6 may be used with a
single ended AC coupled input.
VDC
R
VIN-
VIN-
VIN+
VIN
R
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
Since the HI5630 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, VDC , equal to 2.0V (typical), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes
an excellent DC bias source and stays well within the analog
input common mode voltage range over temperature.
For the AC coupled differential input (Figure 4) and with
VRIN connected to VROUT , full scale is achieved when the
VIN and VIN- input signals are 0.5VP- P , with -VIN being
180 degrees out of phase with VIN . The converter will be at
positive full scale when the VIN+ input is at VDC + 0.25V
and the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V).
Conversely, the converter will be at negative full scale
when the VIN+ input is equal to VDC - 0.25V and VIN- is
equal to VDC + 0.25V (VIN+ - VIN- = -0.5V).
The analog input can be DC coupled (Figure 5) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 4.75V).
The resistors, R, in Figure 5 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
9
VDC
HI5630
VIN-
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
Again, with VRIN connected to VROUT , if VIN is a 1VP-P
sinewave, then VIN+ is a 1.0VP-P sinewave riding on a
positive voltage equal to VDC . The converter will be at
positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN- =
+0.5V) and will be at negative full scale when VIN+ is equal
to VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient headroom
must be provided such that the input voltage never goes
above +5V or below AGND. In this case, VDC could range
between 0.5V and 4.5V without a significant change in ADC
performance. The simplest way to produce VDC is to use the
DC bias source, VDC , output of the HI5630.
The single ended analog input can be DC coupled (Figure 1)
as long as the input is within the analog input common mode
voltage range.
The resistor, R, in Figure 7 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5630.
HI5630
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and digital
supplies and grounds. For best performance, the supplies to
the HI5630 should be driven by clean, linear regulated supplies.
The board should also have good high frequency decoupling
capacitors mounted as close as possible to the converter. If the
part is powered off a single supply then the analog supply
should be isolated with a ferrite bead from the digital supply.
VIN
VIN+
VDC
R
HI5630
C
VDC
VIN-
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
Digital Output Control and Clock Requirements
Static Performance Definitions
The HI5630 provides a standard high-speed interface to
external TTL logic families.
Offset Error (VOS) - The midscale code transition should
occur at a level 1/4 LSB above half-scale. Offset is defined
as the deviation of the actual code transition from this point.
In order to ensure rated performance of the HI5630, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Full-Scale Error (FSE) - The last code transition should
occur for an analog input that is 3/4 LSB below Positive Full
Scale (+FS) with the offset error removed. Full scale error is
defined as the deviation of the actual code transition from
this point.
Performance of the HI5630 will only be guaranteed at
conversion rates above 1MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS will have to be
performed before valid data is available.
Differential Linearity Error (DNL) - DNL is the worst case
deviation of a code width from the ideal value of 1 LSB.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
Integral Linearity Error (INL) - INL is the worst case
deviation of a code center from a best fit straight line
calculated from the measured data.
Power Supply Sensitivity - Each of the power supplies are
moved plus and minus 5% and the shift in the offset and full
scale error (in LSBs) is noted.
Supply and Ground Considerations
The HI5630 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
M
S
B
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
L
S
B
M
S
B
L
S
B
DIFFERENTIAL
INPUT VOLTAGE
(VIN+ - VIN-)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0.498291V
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0.494385V
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
+ 9/16 LSB
2.19727mV
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
- 7/16 LSB
-1.70898V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-FS + 19/16 LSB
-0.493896V
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
-Full Scale (-FS) + 9/16 LSB
-0.497803V
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
CODE CENTER
DESCRIPTION
+Full Scale (+FS) - 7/16 LSB
+FS -
1 7/
16 LSB
NOTE:
8. The voltages listed above represent the ideal center of each output code shown with VRIN = +2.5V.
10
HI5630
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5630. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is typically -0.5dB down from
full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers
are quoted in dBc (decibels with respect to carrier) and DO
NOT include any correction factors for normalizing to full scale.
measuring the number of cycles it takes for the output code
to settle within 8-bit accuracy.
Full Power Input Bandwidth (FPBW) - Full power input
bandwidth is the analog input frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
Video Definitions
The Effective Number of Bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
where: VCORR = 0.5dB (Typical).
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is backed off from full scale.
Differential Gain (DG) - Differential Gain is the peak
difference in chrominance amplitude (in percent) relative to
the reference burst.
Signal To Noise and Distortion Ratio (SINAD) - SINAD is
the ratio of the measured RMS signal to RMS sum of all the
other spectral components below the Nyquist frequency,
fS/2, excluding DC.
Differential Phase (DP) - Differential Phase is the peak
difference in chrominance phase (in degrees) relative to the
reference burst.
Signal To Noise Ratio (SNR) - SNR is the ratio of the
measured RMS signal to RMS noise at a specified input and
sampling frequency. The noise is the RMS sum of all of the
spectral components below fS /2 excluding the fundamental,
the first five harmonics and DC.
Total Harmonic Distortion (THD) - THD is the ratio of the
RMS sum of the first 5 harmonic components to the RMS
value of the fundamental input signal.
2nd and 3rd Harmonic Distortion - This is the ratio of the
RMS value of the applicable harmonic component to the
RMS value of the fundamental input signal.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP) - Aperture delay is the time delay
between the external sample command (the falling edge of
the clock) and the time at which the signal is actually sampled.
This delay is due to internal clock path propagation delays.
Aperture Jitter (tAJ) - Aperture jitter is the RMS variation in
the aperture delay due to variation of internal clock path delays.
Data Hold Time (tH) - Data hold time is the time to where
the previous data (N - 1) is no longer valid.
Spurious Free Dynamic Range (SFDR) - SFDR is the ratio
of the fundamental RMS amplitude to the RMS amplitude of the
next largest spectral component in the spectrum below fS /2.
Data Output Delay Time (tOD) - Data output delay time is
the time from the rising edge of the external sample clock to
where the new data (N) is valid.
Intermodulation Distortion (IMD) - Nonlinearities in the
signal path will tend to generate intermodulation products
when two tones, f1 and f2 , are present at the inputs. The
ratio of the measured signal to the distortion terms is
calculated. The terms included in the calculation are (f1+f2),
(f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The
ADC is tested with each tone 6dB below full scale.
Data Latency (tLAT) - After the analog sample is taken, the
digital data representing an analog input sample is output to
the digital data bus on the 7th cycle of the clock after the
analog sample is taken. This is due to the pipeline nature of
the converter where the analog sample has to ripple through
the internal subconverter stages. This delay is specified as
the data latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 7 sample clock cycles.
Transient Response - Transient response is measured by
providing a full-scale transition to the analog input of the
ADC and measuring the number of cycles it takes for the
output code to settle within 8-bit accuracy.
Over-Voltage Recovery - Over-Voltage Recovery is
measured by providing a full-scale transition to the analog
input of the ADC which overdrives the input by 200mV, and
11
Power-Up Initialization - This time is defined as the
maximum number of clock cycles that are required to
initialize the converter at power-up. The requirement arises
from the need to initialize the dynamic circuits within the
converter.
HI5630
Typical Performance Curves
5.0
7.7
7.6
4.5
7.5
PASSING RANGE
4.0
7.3
VIH (V)
ENOB (BITS)
7.4
7.2
3.5
7.1
3.0
7.0
6.9
2.5
6.8
6.7
0
10
20
30
40
2.0
30
50
35
40
CLOCK FREQUENCY (MHz)
FIGURE 8. ENOB vs INPUT FREQUENCY (fCLK = 80MHz)
45
50
55
DUTY CYCLE (%)
60
65
70
FIGURE 9. DUTY CYCLE vs VIH
5.0
7.70
BLUE
7.65
4.5
GREEN
7.60
PASSING RANGE
7.55
ENOB (BITS)
VIH (V)
4.0
3.5
3.0
RED
7.50
7.45
7.40
7.35
7.30
2.5
7.25
2.0
0
200m
400m
600m
800m
VIL (V)
1.00
1.20
1.40
7.20
1.6
0
FIGURE 10. VIH vs VIL
25
70
TEMPERATURE (oC)
85
FIGURE 11. ENOB vs TEMPERATURE
47.5
68
BLUE
BLUE
47.0
GREEN
66
46.5
RED
64
SFDR (dB)
SNR (dB)
RED
46.0
62
45.5
60
45.0
58
44.5
GREEN
56
0
25
70
TEMPERATURE (oC)
FIGURE 12. SNR vs TEMPERATURE
12
85
0
25
70
TEMPERATURE (oC)
FIGURE 13. SFDR vs TEMPERATURE
85
HI5630
Typical Performance Curves
(Continued)
1.970
0.7
RED
1.968
0.6
1.966
0.5
VDC (V)
INL (LSB)
1.964
GREEN
0.4
BLUE
0.3
1.962
RED VDC
1.960
BLUE VDC
1.958
0.2
GREEN VDC
1.956
0.1
1.954
0
1.952
25
70
TEMPERATURE (oC)
0
85
0
FIGURE 14. INL vs TEMPERATURE
25
70
TEMPERATURE (oC)
85
FIGURE 15. VDC vs TEMPERATURE
2.476
300
2.474
250
2.472
CURRENT (mA)
VREF (V) WITH 4mA LOAD
I TOTAL
VREF (4mA LOAD)
2.470
2.468
I AVDD
200
150
100
I DVDD
2.466
50
2.464
2.462
0
0
25
70
TEMPERATURE (oC)
FIGURE 16. VREF vs TEMPERATURE
85
0
25
70
TEMPERATURE (oC)
85
FIGURE 17. SUPPLY CURRENT (mA) vs TEMPERATURE
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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13