HIP9010 TM Data Sheet November 1998 Engine Knock Signal Processor Features The HIP9010 is used to provide a method of detecting premature detonation or “Knock” in automotive engines. • Two Sensor Inputs A block diagram of this IC is shown in Figure 1. The chip alternately selects one of the two sensors mounted on the engine block. Two programmable bandpass filters process the signal from both sensors, and divides the signal into two channels. When the engine is not knocking, programmable gain adjust stages are set to ensure that both the reference channel and the knock channel contain similar energies. This technique ensures that the detection system is comparatively immune to changes in the engine background noise level. When the engine is knocking, the energy in the knock channel increases. • Accurate and Stable Filter Elements FN3601.4 • Microprocessor Programmable • Digitally Programmable Gain • Digitally Programmable Time Constants • Digitally Programmable Filter Characteristics • On-Chip Clock • Operating Temperature Range -40oC to 125oC Applications • Engine Knock Detector Processor Ordering Information PART NUMBER HIP9010AB TEMP. RANGE ( oC) -40 to 125 1 PACKAGE 20 Ld SOIC (W) PKG. NO. • Analog Signal Processing where Controllable Filter Characteristics are Required Pinout M20.3 HIP9010 (SOIC) TOP VIEW VDD 1 20 S0IN GND 2 19 S0FB VMID 3 18 S1FB INOUT 4 17 S1IN NC 5 16 NC NC 6 15 NC INT/HOLD 7 14 TEST CS 8 13 SCK OSCIN 9 12 MOSI OSCOUT 10 11 MISO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved Simplified Block Diagram REFERENCE FREQUENCY CHANNEL 2 PROGRAMMABLE BANDPASS FILTER 1-20kHz 64 STEPS (19) S0FB (20) S0IN + POWER SUPPLY AND BIAS CIRCUITS INOUT (4) PROGRAMMABLE INTEGRATOR 40-600µs 32 STEPS PROGRAMMABLE BANDPASS FILTER 1-20kHz 64 STEPS PROGRAMMABLE STAGE GAIN 1-0.133 64 STEPS HIP9010 (17) S1IN CHANNEL SELECT SWITCHES (18) S1FB ACTIVE FULL WAVE RECTIFIER 3RD ORDER ANTIALIASING FILTER + PROGRAMMABLE GAIN STAGE 1-0.133 64 STEPS DIFFERENTIAL TO SINGLE-ENDED CONVERTER AND OUTPUT DRIVER OSCIN (9) ACTIVE FULL WAVE RECTIFIER CLOCK TO SWITCHED CAPACITOR NETWORKS OSCOUT (10) SCK (13) CS (8) KNOCK FREQUENCY CHANNEL (3) VMID REGISTERS AND STATE MACHINE SPI MOSI (12) INTERSPACE MISO (11) INT/HOLD (7) (1) VDD (2) GND (14) TEST FIGURE 1. HIP9010 Absolute Maximum Ratings Thermal Information DC Logic Supply, V DD . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V (Max) Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering) . . . . . . . . . . . . . . . 300oC At distance 1/16in ± 1/32in (1.59mm ± 0.79mm) from case for 10s (Max) (SOIC - Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, ±5%, GND = 0V, Clock Frequency 4MHz, ±0.5%, TA = -40oC to 125oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 3 7.5 12 mA DC ELECTRICAL CHARACTERISTICS Quiescent Supply Current IDD VDD = 5.25V, GND = 0V Midpoint Voltage, Pin 3 VMID VDD = 5.0V, IL = 2mA Source 2.3 2.45 2.55 V Midpoint Voltage, Pin 3 VMID VDD = 5.0V, IL = 0mA 2.4 2.5 2.6 V Input Leakage, Pin 14 ILTEST Measured at VDD = 5.0V - - 3 µA Internal Pull-Up Resistance, Pin 14 RTEST VDD = 5.0V, I Measure = 15µA 30 100 200 KΩ - - ±3 µA Leakage of Pins 7, 8, 12 and 13 IL Measured at GND and V DD = 5V Low Input Voltage, Pins 7, 8, 12 and 13 VIL - - 30 % of VDD High Input Voltage, Pins 7, 8, 12 and 13 VIH 70 - - % of VDD Low Level Output, Pin 11 VOL 0.01 - 0.30 V Measured at GND and V DD = 5V - - ±10 µA - - 1.5 V Leakage Pin 11 IL ISOURCE = 4mA Low Level Output, Pin 10 VOL ISOURCE = 500µA, V DD = 5V High Level Output, Pin 10 VOH ISINK = -500µA, V DD = 5V 4.4 - - V 4.7 4.9 - V INPUT AMPLIFIERS S0FB and S1FB High Output Voltage VOUTHI 100µA ISINK, VDD = 5V S0FB and S1FB Low Output Voltage V OUTLO 100µA ISOURCE, VDD = 5V - 15 200 mV S0FB and S1FB Closed Loop ACL Input Resistor = 1MΩ, Feedback Resistor = 49.9kΩ -25 -26 -27 dB S0FB and S1FB Closed Loop ACL Input Resistor = 47.5kΩ, Feedback Resistor = 475kΩ 18 20 21 dB BW Test Mode, 70mVRMS Input to S0FB or S1FB, Output Pin 4 - -2 - dB ATEN Test Mode, 70mVRMS Input to S0FB or S1FB, Output Pin 4 -10 -15 - dB VOUTP-P Run Mode 3.5 4.0 - VP-P Q Run Mode - 2.5 - Q %G Run Mode - ±1 - % ANTIALIASING FILTER Response 1kHz to 20kHz, Referenced to 1kHz Attenuation at 180kHz Referenced to 1kHz PROGRAMMABLE FILTERS Peak to Peak Voltage Output Filters Q (Note 2) PROGRAMMABLE GAIN AMPLIFIERS Percent Amplifier Gain Deviation Per Table 2 3 HIP9010 Electrical Specifications VDD = 5V, ±5%, GND = 0V, Clock Frequency 4MHz, ±0.5%, TA = -40oC to 125oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 0.1 - mV 430 500 570 mV INTEGRATOR Integrator Offset Voltage INTGVIO By Design Integrator Reset Voltage V RESET Pin 4 Voltage at Initiation of Integration Cycle. VDD = 5V Integrator Droop after 500µs VDROOP Hold Mode, Pin 7 = 0V, VDD = 5V, Pin 4 set to 20% to 80% of VDD - ±±3 ±±50 mV OUTPUT AND SAMPLE AND HOLD Differential to Single Ended Converter Offset Voltage DIFVIO By Design - 0.1 - mV Change in Converter Output DIFOUT Run Mode, 500µA, Sinking to No Load - ±±1 ±±3 mV VOUT VRESET Run Mode, maximum signal output from Input Amplifier <2.25VP-P, Equation Output x 0.95 + Device Reset Voltage. For Total VOUT ≤ 4.7V -8%, ±±100mV Equation x 0.95 -VRESET 8%, ±100mV V SYSTEM GAIN DEVIATION Gain Deviation from “Ideal Equation” Correlation, Factor - 5.0% NOTE: 2. Q = fO /BW, Where: fO = Center Frequency, BW = 3dB bandwidth. Ideal Equation RF INTO UT ( volts ) = Input signal (V P – P ) × ---------R IN G K N N × 1.273 × --------------------------------------------------- – G R × 1.273 × --------------------------------------------------- + V R ESET TC (ms) × fQ (kHz) TC (ms) × f Q (kHz) When the two filters are set to the same frequency and the input signal is present for the periods TIN, then: RF INTO UT ( volts ) = Input signal (V P – P ) × ---------R IN 1.273 TI N × --------- ( G K – G R ) + VRESET TC GR and GK = Programed Gain of Reference and Knock channels. TIN = Time input signal is present In ms. TC = Programmed integrator time constant ms. N = Number of cycles of input signal. fQ = Frequency of input signal. Assumes both filters are programmed to the same frequency. VRESET = Integrator Reset Voltage. 1.273 = 4/π RF = Feedback resistor value. RIN = Signal input resistor value. For example, assume 300mV P-P input with the time constant programmed to 300µs and the Integration time is 1.2ms. The RF/RIN ratio is one and the Reference channel is programmed to a Gain of 0.188. The Knock channel is then automatically set to a gain of one. The input signal is continuous for the total integration time, TIN. INTO UT ( volts ) = 0.3V (V P – P ) × 4 1.273 1.2ms × ----------------------- × ( 1.000 – 0.188 ) 0.300m s + VRESET = 1.24 V + 0.500V = 1.74V HIP9010 VDD +5V HIP9010 VMID C3, 0.022µF GND MOSI C2, 3.3nF MISO S1IN R2 C1, 3.3nF S0IN R1 TRANSDUCERS SCK S1FB 20pF SPI BUS CS R4 INT/HOLD S0FB TEST R3 OSCIN 4MHz OSCOUT 20pF INTOUT 1M A/D CONVERTER MICROPROCESSOR FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE HIP9010 IN AN AUTOMOTIVE APPLICATION Pin Descriptions PIN NUMBER SYMBOL 1 VDD 5V power input. 2 GND This terminal is tied to ground. 3 VMID This terminal is tied to the internal mid-supply generator and is brought out for supply bypassing by a 0.022µF capacitor. 4 INTOUT 5 and 6 NC 7 INT/HOLD 8 CS 9 OSCIN 10 OSCOUT 11 MISO Output of the chip SPI data bus. It is the inversion of the chip DATAIN line. This is an open drain output. The output must be disabled by placing the CS High when the chip is not selected. 12 MOSI Input of the chip SPI data bus. Data length is eight bits. 13 SCK Input from the SPI clock. Normally high, the data is clocked to the chip internal circuitry on the rising clock edge. 14 TEST A low on this pin places the chip in the test mode. For normal operation this terminal is tied high or left open. 15 and 16 NC 17 S1IN Inverting input to sensor one amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this terminal and terminal 18, S1FB to establish the gain of the amplifier. 18 S1FB Output of the sensor one amplifier. This terminal is used to apply feedback. 19 S0FB Output of the sensor zero amplifier. This terminal is used to apply feedback. 20 S0IN Inverting input to sensor zero amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this terminal and terminal 19, S0FB to establish the gain of the amplifier. DESCRIPTION Buffered output of the integrator. These terminals are not internally connected. DO NOT USE. Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). A low input on this pin enables the chip to communicate over the SPI bus. Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and pin 10. To bias the inverter, a 1.0MΩ to 10MΩ resistor is usually connected between this pin and pin 10. Output of the inverter used for the oscillator. See pin 9 above. These terminals are not internally connected. DO NOT USE. 5 HIP9010 Description of the HIP9010 Operation This IC is designed to be a universal digitally controlled, analog interface between engine acoustical sensors or accelerometers and internal combustion engine fuel management systems. Two wideband input amplifiers are provided that allow the use of two sensors that may be of the piezoelectric type that can be mounted in optimum locations on either in-line or V-type engine configurations. Output from these amplifiers is directed from a channel select switch into both digitally controlled filter and amplifier channels. Both filter bandpass and gain settings are programmable from a microprocessor. Output from the two channels is combined in a digitally programmable integrator. Integrator output is applied to a line driver for further processing by the engine fuel management system. Broadband piezoelectric ceramic transducers used for the engine signal pickup have device capacitances in the order of 1100pF and output voltages that range from 5mV to 8VRMS. During normal engine operation a single input channel is selected and applied to the filters. One filter channel processes a signal that is used to establish the background reference level. The second channel is used to observe the engine during the time interval that preignition may be expected. This information is compared with the “background” signal via the IC’s integrator and will tend to cancel the background noise and accentuate noise due to engine pre-detonation. Moreover, the bandpass of filter channels can be optimized to further discriminate between engine background and combustion noise and pre-detonation noise. A basic approach to engine pre-detonation systems is to only observe engine background during the time interval that noise is expected and if detected, retard timing. This approach does not require the sensitivity and selectivity that is needed for a continuously adjustable solution. Enhanced fuel economy and performance is obtainable when this IC is coupled with a microprocessor controlled fuel management system. Circuit Block Description Input Amplifiers Two amplifiers are used to interface to the two engine sensors. These amplifiers have a typical open loop gain of 100dB, with a typical bandwidth of 2.6MHz. The common mode input voltage range extends to within 0.5V of either supply rail. The amplifier output has a similar output range. Sufficient gain, bandwidth and output swing capability was provided to ensure that the amplifiers can handle attenuation gain settings of 20 to 1 or -26dB. This would be needed when high peak output signals, in the range of 8VRMS , are obtained from the transducer. Gain settings of 10 times can also be needed when the transducers have output levels of 5mVRMS . 6 In a typical application the input signal frequency may vary from DC to 20kHz. External capacitors are used to decouple the IC from the sensor (C1 and C2). A typical value of the capacitors is 3.3nF. Series input resistors, R1 and R2, are used to connect the inverting inputs of the amplifiers, (pins 20 and 17). Feedback resistors, R3 and R4, in conjunction with R1 and R2 are used to set the gain of the amplifiers. R3 SENSOR C1 R1 0 PIN 20 VMID + PIN 19 PIN 3 R4 SENSOR C2 R2 1 PIN 17 VMID + PIN 18 PIN 3 FIGURE 3. INPUT AMPLIFIER CONNECTIONS A mid-voltage level is generated by the IC. This level is set to be half way between VDD and ground. Throughout the IC this level is used as a quiet, DC reference for the circuits within the IC. This point is brought out for several reasons: it can be used as a reference voltage, and it must be bypassed to ensure that it is a quiet reference for the internal circuitry. The input amplifiers are designed with power down capability, which, when activated disables their bias circuit and their output goes into a three-state condition. This is very important during the test mode, in which the output terminals of the amplifiers are driven by the outside world with test signals. Antialiasing Filter The IC has a 3rd order Butterworth filter with a -3dB point at 70kHz. Double poly-silicon capacitors and implanted resistors are used to set poles in the filter. This filter is required to have no more than 1dB attenuation at 20kHz (highest frequency off interest) and a minimum attenuation of 10dB at 180kHz. This filter precedes the switch capacitor filters which run at 200kHz. Programmable Band Pass Switched Capacitor Filters Two identical programmable filters are used to detect the two frequencies of interest. The Knock Frequency Filter is programmed to pass the frequency component of the engine knock. The Reference Frequency Filter is used to detect background noise at a second programmed frequency. The filter frequency is established by the characteristics of the particular engine and transducer. By subtracting the energy component of these two filters, we can detect if a knock has occurred. The filters have a nominal differential gain of 4. Their frequency is set by program words (discussed in the Communications Protocol section). Center frequencies can HIP9010 be programmed from 1.22kHz to 19.98kHz, in 64 steps. The filter Qs are typically 2.4. Balance/Gain Adjust Stage The gains from the Knock Frequency Filter and the Reference Frequency Filter can be adjusted with respect to one another, so that the difference energies in the two bands can be compensated. This balance is achieved by feeding one of the filters unattenuated (gain = 1) and attenuating the other. This can be adjusted with 64 different gain settings, ranging between 1 and 0.133. The signals can swing between 20 and 80 percent of VDD . Programming is discussed in the Communications Protocol section. The test/channel attenuate word is used to determine which of the two channels is attenuated and which is set to unity gain. Active Full Wave Rectifier The output of the filters are independently full wave rectified using switch capacitor techniques. Each of two rectifier circuits provide both negative and positive values for the knock frequency and reference frequency filter outputs. The output is able to swing from 20% to 80% of VDD . Care was taken to minimize the RMS variations from input to output of this section. Integrator Stage The signals from the two rectifiers are summed and integrated together. A differential system is used to reduce noise. One system integrates the positive energy of the Knock Frequency Rectifier with respect to the positive energy of the Reference Frequency Rectifier. The second system does the integration of the negative energy value of the two rectifiers. The positive and negative energy signals are opposite phase signals. Using this technique reduces system noise. The integrator time constant is software programmable by the Integrator Time Constant discussed in the Communications Protocol section. The time constant can be programmed from 40µs to 600µs, with a total of 32 steps. If for example, we program a time constant to 200µs, then with one volt difference between each channel, the output of the integrator will change by 1 volt in 200µs. When integration is enabled by the rising edge of the INT/HOLD input, the output of the integrator will fall to 0.5V, within 20µs after the integrate line reaches the integrate state. The output of the integrator is an analog voltage. Test Multiplexer This circuit receives the positive and negative outputs from the two integrators, together with the outputs from different parts of the IC. The output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capacitor filter output, the gain control output and the antialiasing filter output. 7 Differential to Single-Ended Converter This signal takes the output of the two integrators (through the test-multiplexer circuit) and provides a signal that is the sum of the two signals. This technique is used to improve the noise immunity of the system. Output Buffer This output amplifier is the same amplifier circuits as the input amplifier used to interface with the sensors. When the output of the antialiasing filter is tested, this amplifier is in the power down mode. Communications Protocol The multiprocessor talks to the knock sensor via an SPI bus (MOSI). A chip select pin (CS) is used to enable the chip, which, in conjunction with the SPI clock (SCK), moves in the eight bit programming word. Five different programming words are used to set gains, frequency response, integrator constants, test mode, channel select and test mode conditions. With chip select (CS) going low, on the next rising edge of the SPI clock (SCK), data is latched into the IC. The data is shifted with the most significant bit first and least significant bit last. Each word is divided into two parts: first the address and then the value. Depending on the function being controlled, the address is 2 or 3 bits, and the value is either 5 or 6 bits long. During the hold mode of operation, all five programming words can be entered into the IC, but during the integrate time any single byte may be entered but will not be acted upon until the start of the next hold period. The integration or hold mode of operation is controlled by the INT/HOLD input signal. Programming Words 1. Reference Filter Frequency: Defines the center frequency of the Reference Filter in the system. The first 2 bits are used for the address and the last 6 bits are used for its value. 01FFFFFF Example: 01001010 would be the reference filter (01 for the first two bits) at a center frequency of 1.78kHz (bit value in Table 2 of 10). 2. Knock Filter Frequency: Defines the center frequency of the Knock Filter in the system. The first 2 bits are used for the address and the last 6 bits are used for its value. 00FFFFFF Example: 00100111 would be the knock filter frequency (00 for the first two bits) at a center frequency of 6.37kHz (bit value in Table 2 of 39). 3. Balance Control: Defines the ratio of the gain of the knock band center frequency to that of the reference band center frequency. This role can be reversed by the value of C A in the fifth programming bit, as explained in 5, Test/Channel Select/Channel Attenuate Control. The first 2 bits are used for the address and the last 6 bits for its value. 10GGGGGG Example: 10010100 would be the balance control (10 for the first two bits) with an attenuation of 0.514 (bit value in Table 2 of 20.) Depending on the value of CA in the fifth word this would apply to the reference or the knock gain section. HIP9010 4. Integrator Time Constant: Defines the Integration Time Constant for the system. The first 3 bits are used for the address and the last 5 bits for the value. 110TTTTT Example: 11000011 would be the integrator time constant (110 on for the first 3 bits) and an integration constant of 55µs (bit value of 3 in Table 2). 5. Test/Channel Select/Channel Attenuate Control: This word serves several purposes. By looking at the structure, 111TATBTCCSCA , the first 3 bits are used for the address, and the last 5 bits are used for the value. The options are: - If CS is “0” channel “0” is selected. If CS is “1” channel “1” is selected. - If CA is “0” attenuation applies to the knock filter. If CA is “1” attenuation applies to the reference filter. - During the test mode (TEST input is a low level), if TA is “0” all sections get their input from the output of the antialiasing filter input. This input can come from either the output of channel “0” amplifier or channel “1” output depending upon the state of the CS bit. If TA is “0” the input amplifiers are powered down. If TA is set to “1” during the test mode the chip is configured in its normal operating state, getting inputs to all sections from previous sections. - Combinations of TA , TB and TC are used to test the different analog parts of the circuit. Table 1 shows these combinations. All blocks except for the antialiasing filter are sampled via the differential to single ended converter in the test mode. TABLE 1. SHOWING PROGRAMMING IN THE TEST MODE ANALOG OUTPUT FROM: TEST PIN 14 TA TB TC CHS 0 0 0 0 0 Knock Rectifier 0 0 0 0 1 Reference 0 0 0 1 0 Knock Filter 0 0 0 1 1 Reference Filter 0 0 1 0 0 Antialias Filter(1) 0 0 1 0 1 Antialias Filter(1) 0 0 1 1 0 Integrator 0 0 1 1 1 Integrator 0 1 0 0 0 Knock Rectifier 0 1 0 0 1 Reference 0 1 0 1 0 Knock Filter 0 1 0 1 1 Reference Filter 0 1 1 0 0 Antialias Filter(1) 0 1 1 0 1 Antialias Filter(1) 0 1 1 1 0 Integrator 0 1 1 1 1 Integrator 1 x x x x Integrator VDD S0IN S1IN HALF OF DIFFERENTIAL AMPLIFIER TO NEXT STAGE FIGURE 4A. S0IN AND S1IN INPUT CIRCUIT MISO 11 FIGURE 4B. MISO OUTPUT OF SPI DATA BUS IS AN OPEN DRAIN TRANSISTOR VDD 50µA TO LOGIC TEST 14 FIGURE 4C. TEST PMOS TRANSISTOR HAS EQUIVALENT CURRENT PULLUP CAPABILITY OF A 50k TO 200k RESISTOR VDD S0FB S1FB INOUT NOTE: 3. All Test function blocks have their outputs buffered by the differential to single ended converter. Their outputs are available at the INTOUT pin 4 of the chip. In the case of the antialias filter test function, the output is taken directly to the INTOUT pin 4 of the chip. 8 FIGURE 4D. S0FB, S1FB AND INOUT EQUIVALENT OUTPUT CIRCUITS FIGURE 4. INTERFACE CIRCUITS HIP9010 TABLE 2. FREQUENCY, BALANCE / GAIN AND INTEGRATOR TIME CONSTANT SETTINGS BIT VALUE PER FUNCTION FREQUENCY kHz OUTPUT LEVEL TIME CONSTANT µs BIT VALUE PER FUNCTION FREQUENCY kHz OUTPUT LEVEL 0 1.22 1.000 40 32 4.95 0.360 1 1.26 0.960 45 33 5.12 0.346 2 1.31 0.923 50 34 5.29 0.333 3 1.35 0.889 55 35 5.48 0.320 4 1.40 0.857 60 36 5.68 0.309 5 1.45 0.828 65 37 5.90 0.298 6 1.51 0.800 70 38 6.12 0.288 7 1.57 0.774 75 39 6.37 0.279 8 1.63 0.750 80 40 6.64 0.270 9 1.71 0.727 90 41 6.94 0.262 10 1.78 0.706 100 42 7.27 0.254 11 1.87 0.686 110 43 7.63 0.247 12 1.96 0.667 120 44 8.02 0.240 13 2.07 0.649 130 45 8.46 0.234 14 2.18 0.632 140 46 8.95 0.228 15 2.31 0.615 150 47 9.50 0.222 16 2.46 0.600 160 48 10.12 0.217 17 2.54 0.576 180 49 10.46 0.208 18 2.62 0.554 200 50 10.83 0.200 19 2.71 0.533 220 51 11.22 0.193 20 2.81 0.514 240 52 11.65 0.186 21 2.92 0.497 260 53 12.10 0.179 22 3.03 0.480 280 54 12.60 0.173 23 3.15 0.465 300 55 13.14 0.168 24 3.28 0.450 320 56 13.72 0.163 25 3.43 0.436 360 57 14.36 0.158 26 3.59 0.424 400 58 15.07 0.153 27 3.76 0.411 440 59 15.84 0.149 28 3.95 0.400 480 60 16.71 0.144 29 4.16 0.389 520 61 17.67 0.141 30 4.39 0.379 560 62 18.76 0.137 31 4.66 0.369 600 63 19.98 0.133 9 HIP9010 ADDRESS DECODER MOSI REFERENCE FILTER DIGITAL MULTIPLEXER CS SPI INTERFACE KNOCK FILTER SCK BALANCE CONTROL INTEGRATOR TIME CONSTANT TEST/ CHANNEL SELECT ATTENUATE MOSI OSCILLATOR CIRCUIT OSCOUT OSCIN MISO TEST COMPARATOR OUT (FROM RECTIFIER PHASE DETECTOR) FIGURE 5. DIGITAL BLOCK DIAGRAM The digital block diagram shows the programming flow of the chip. An eight bit word is received at the MISO port. Data is shifted in by the SCK clock when the chip is enabled by the CS pin. The word is decoded by the address decoding circuit, and the information is directed to one of 5 registers. These registers control: 1. Reference knock filter frequency. 2. Knock filter frequency. 3. Balance control or attenuation of one channel with respect to the other. 4. Integration time constant of the sum of the two channels. 5. One of 3 functions. a) test conditions of the part. b) channel select to one of two sensors. c) channel to be attenuated. A crystal oscillator circuit is provided. The chip requires a 4MHz crystal to be connected across OSCIN and OSCOUT pins. INT/HOLD T8 CS T1 T5 T4 SCK T2 DATA IN T3 B7 B6 B5 B4 B3 B2 B1 B0 T6 T7 FIGURE 6. SPI TIMING TABLE 3. SPI TIMING REQUIREMENTS DESCRIPTION UNITS T1 minimum time from CS falling edge to SCK falling edge. 10ns T2 minimum time from CS falling edge to SCK rising edge. 80ns 2. Inverted signal of the MOSI pin. T3 minimum time for the SCK low. 60ns 3. Voltage of an internal comparator used to rectify the analog signal. T4 minimum time for the SCK high. 60ns T5 minimum time from SCK rise after 8 bits to CS rising edge. 80ns T6 minimum time from data valid to rising edge of SCK. 60ns T7 minimum time for data valid after the rising edge of the SCK. 10ns T8 minimum time after CS rises until INT/HOLD goes high. 8µs In the test mode, use the digital multiplexer to output one of the following signals: 1. Contents of one of the five registers in the chip. Upon power up, chip requires that the INT/HOLD pin is toggled. If this is not done then it is important to note, that only the first result and SPI data bytes sent after power up will not be valid. Any subsequent chip operation will then be performed correctly. 10 HIP9010 Test Multiplexer This circuit receives the positive and negative outputs out of the two integrators, together with the outputs from different parts of the chip. The output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capacitor filter output, the gain control output as well as the antialias output. CS INT/HOLD FIGURE 7. POWER UP SEQUENCE Differential to Single-ended Converter This signal takes the output of the two integrators (through the test multiplexer circuit) and provides a signal that is the sum of the two signals. This technique is used to improve the noise immunity of the system. T3 T1 INT/HOLD Output Buffer This output amplifier is the same as the input amplifier used to interface to the sensors. For test purposes when we look at the output of the antialias filter, the input amplifiers are in the power down mode. T2 T4 INTOUT FIGURE 8. INTEGRATOR TIMING TABLE 4. INTERGRATE/HOLD TIMING REQUIREMENTS DESCRIPTION UNITS T1 maximum rise time of the INT/HOLD signal. 45ns T2 maximum time after INT/HOLD rises for the INOUT to begin to intergrate. 20µs T3 maximum fall time of INT/HOLD signal. 45ns T4 typical time after INT/HOLD goes low before chip goes into hold state. 20µs T5 minimum INT/HOLD time during power up sequence. 1µs 11 HIP9010 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) N 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e µα B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 20 0o 20 8o 0o 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 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