HT16L23v120.pdf

HT16L23
RAM Mapping 52×4 / 48×8 LCD Driver
Feature
Applications
• Logic operating voltage: 1.8V~5.5V
• Leisure products
• LCD operating voltage (VLCD): 2.4V~6.0V
• Games
• Internal 32kHz RC oscillator
• Telephone display
• Bias: 1/3 or 1/4; Duty: 1/4 or 1/8
• Audio combo display
• Internal LCD bias generation with voltage-follower
buffers
• Video player display
• External VLCD pin to supply LCD operating
voltage
• Measurement equipment display
• Kitchen appliance display
• Household appliance
• Integrated regulator to adjust LCD operating
voltage: 3.0V, 3.2V, 3.3V, 3.4V, 4.4V, 4.5V, 4.6V,
5.0V
• Consumer electronics
General Description
• Integrated LED driver
The HT16L23 device is a memory mapping and
multi-function LCD controller/driver. The display
segments of the device are 208 patterns (52 segments
and 4 commons) for 1/4 duty display or 384 patterns
(48 segments and 8 commons) for 1/8 duty display.
It can also support LED drive outputs on certain
segment pins. The software configuration feature of
the HT16L23 device makes it suitable for multiple
LCD applications including LCD modules and display
subsystems. The HT16L23 device communicates with
most microprocessors/microcontrollers via a two-wire
bidirectional I2C or a three-wire SPI interface.
• Support I C or SPI 3-wire serial interface controlled
by IFS pin
2
• Four selectable LCD frame frequencies: 64Hz or
85.3Hz or 128Hz or 170.6Hz
• Up to 48×8 bits RAM for display data storage
• Display pixel:
♦♦
52×4 pixel: 52 segments and 4 commons
♦♦
48×8 pixel: 48 segments and 8 commons
• Support two driver output mode segment/LED on
SEG44~SEG51/LED7~LED0
• Versatile blinking modes: off, 0.5Hz, 1Hz, 2Hz
• R/W address auto increment
• Low power consumption
• Manufactured in silicon gate CMOS process
• Package type: 64-pin LQFP
Rev. 1.20
1
January 19, 2016
HT16L23
Block Diagram
RSTB
VDD voltage supported range
Power_on reset
VDD
VSS
COM0
SDA/DIO
Internal RC
Oscillator
SCL/CLK
CSB
Column
/Segment
driver
output
Timing
generator
I2C or 3-wire
Controller
8
Display RAM
COM3
COM4/SEG0
IFS
VE bit
COM7/SEG3
VLCD
Regulator
SEG4
R
－
OP2
＋
R
－
OP1
＋
Segment
/LED driver
output
LCD
Voltage
Selector
SEG43
SEG44/LED7
R
－
SEG51/LED0
OP0
＋
R
LCD bias generator
VLCD voltage supported range
Pin Assignment
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
LED7/SEG44
LED6/SEG45
LED5/SEG46
LED4/SEG47
LED3/SEG48
LED2/SEG49
LED1/SEG50
LED0/SEG51
VSS
IFS
CSB
SCL/CLK
SDA/DIO
RSTB
VDD
VLCD
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
SEG4
SEG5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 54 53 52
48
47
46
45
44
43
42
HT16L23
41
64 LQFP-A
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
Rev. 1.20
2
January 19, 2016
HT16L23
Pin Description
Pin Name
Type
Description
SDA/DIO
I/O
Serial data input/output pin
• Serial data (SDA) input/output for 2-wire I2C interface is an NMOS open
drain structure.
• Serial data (DIO) input/output for 3-wire SPI interface is a CMOS
input/output structure.
SCL/CLK
I
Serial clock input pin
• Serial data (SCL) is clock input for 2-wire I2C interface.
• Serial data (CLK) is clock input for 3-wire SPI interface.
CSB
I
Chip select pin
This pin is available for 3-wire SPI interface and not used for I2C interface.
IFS
I
Communication interface select pin
This pin is used to select the communication interface. When this pin is
connected to VDD, the device communicates with MCU or microprocessors
via a 2-wire I2C interface. When this pin is connected to VSS, the device
communicates with MCU or microprocessors suing a 3-wire SPI interface.
COM0~COM3
O
LCD common outputs.
COM4/SEG0~COM7/SEG3
O
LCD common/segment multiplexed driver outputs.
SEG4~SEG43
O
LCD segment outputs.
SEG44/LED7~SEG51/LED0
O
LCD segment/LED multiplexed driver outputs.
I
Reset input pin
1. This pin is used to initialize all the internal registers and the commands
pin.
2. If use internal power on reset circuit only, the RSTB pin must be
connected to VDD.
RSTB
VDD
—
Positive power supply.
VSS
—
Negative power supply, ground.
VLCD
—
LCD power supply pin
Approximate Internal Connections
SCL, SDA (for schmit Trigger type)
DIO (for Schmitt trigger type)
COM0~COM7; SEG0~SEG51
VDD
Vselect-on
Vselect-off
VSS
VSS
IFS, RSTB
LED0~7
CSB, CLK (for schmit Trigger type)
VDD
VDD
VSS
VSS
Rev. 1.20
VSS
3
January 19, 2016
HT16L23
Absolute Maximum Ratings
Supply voltage .......................................................................................................................VSS−0.3V to VSS+6.6V
Input voltage .........................................................................................................................VSS−0.3V to VDD+0.3V
LED driver output current (total)...................................................................................................................... 88mA
Storage temperature ........................................................................................................................-55°C to +150°C
Operating temperature ......................................................................................................................-40°C to +85°C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings"
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
Timing Diagrams
I2C Timing
SDA
tBUF
tSU:DAT
tf
tLOW
tSP
tHD:STA
tr
SCL
tHD:SDA
tHD:DAT
S
tHIGH
tSU:STA
tAA
tSU:STO
P
Sr
S
SDA
OUT
SPI Timing
tCSW
90%
90%
VDD
CSB
10%
10%
tCSL
tSYS
tCSH
90%
CLK
90%
tCW
10%
tDS
90%
90%
10%
10%
VSS
tHS
90%
10%
10%
VDD
tCW
10%
90%
VSS
VDD
DIO
(INPUT )
VSS
tPD
tPD
90%
90%
10%
10%
VDD
DIO
(OUTPUT )
Rev. 1.20
4
VSS
January 19, 2016
HT16L23
Reset Timing
80%
tSR
0.9V
VDD
tRSON
0.9V
tPOF
tRW
50
%
50%
RSTB
Data
transfer
50%
50%
tRSOFF
tRSOFF
tRSOFF
50%
50%
50%
Note: 1. If the conditions of reset timing are not satisfied in power ON/OFF sequence, the internal power on reset
(POR) circuit will not operate normally.
2. If the VDD drops lower than the minimum operating voltage during operating, the conditions of power on
reset timing must also be satisfied. That is the VDD drop to 0.9V and keep at 0.9V for 10ms (min.) before
rising to the normal operating voltage.
3. Data transfers on the I2C or SPI 3-wire serial interface should at least be delayed for 1ms after the
power-on sequence to ensure that the reset operation is complete.
D.C. Characteristics
Unless otherwise specified, VSS = 0V; VDD = 1.8 to 5.5V; Ta =-40~85°C
Symbol
Parameter
Test Condition
VDD
Condition
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
—
1.8
—
5.5
V
VLCD
LCD Operating Voltage
—
—
2.4
—
6.0
V
VIH
Input High Voltage
—
CSB, CLK, DIO, RSTB
0.7VDD
—
VDD
V
VIL
Input Low Voltage
—
CSB, CLK, DIO, RSTB
0
—
0.3VDD
V
IIL
Input Leakage Current
—
VIN=VSS or VDD
-1
—
1
μA
-2
—
—
mA
IOH
High Level Output
Current
-6
—
—
mA
5.0V
-12
—
—
mA
2.0V
3
—
—
mA
6
—
—
mA
9
—
—
mA
—
1
2.5
μA
—
2
5
μA
—
4
10
μA
2.0V
IOL
Low Level Output Current
3.3V
3.3V
VOH=0.9VDD, DIO
VOL=0.4V, SDA, DIO
5.0V
2.0V
IDD
Operating Current
3.3V
5.0V
Rev. 1.20
No load, fLCD=64Hz, 1/3bias
LCD display on, internal system
oscillator on, VLCD pin input
voltage =5V, disable integrated
regulator
5
January 19, 2016
HT16L23
Symbol
ILCD1
ILCD2
ISTB1
ISTB2
Vreg
IOL1
IOH1
IOL2
IOH2
IOL3
Parameter
Operating Current
Operating Current
Standby Current for VDD
Standby Current for VLCD
Regulator Output
LCD Common Sink
Current
LCD Common Source
Current
LCD Segment Sink
Current
LCD Segment Source
Current
LED Sink Current
Test Condition
Min.
Typ.
Max.
Unit
2.0V
No load, fLCD=64Hz, 1/3bias,
LCD display on, internal system
oscillator on, VLCD pin input
voltage=5V, disable integrated
regulator
—
25
40
μA
2.0V
No load, fLCD=64Hz, 1/3bias, LCD
display on, internal system
oscillator on, VLCD pin input
voltage=5.5V, regulator output is
set to 5V
—
35
56
μA
No load, 1/3bias, LCD display off,
internal system oscillator off,
VLCD pin input voltage =5V
disable integrated regulator
—
—
1
μA
—
—
2
μA
No load, 1/3bias, LCD display off,
internal system oscillator off,
VLCD pin input voltage =5V,
disable integrated regulator
—
—
1
μA
—
—
2
μA
VLCD pin input voltage=5.5V,
regulator output is set to 4.5V,
Ta=-40°C~85°C
4.35
4.5
4.65
V
VLCD pin input voltage=5.5V,
regulator output is set to 4.5V,
Ta=25°C
4.42
4.5
4.58
V
VLCD=3.3V, VOL=0.33V,
disable integrated regulator
250
400
—
μA
VLCD=5V, VOL=0.5V,
disable integrated regulator
500
800
—
μA
VLCD=3.3V, VOH=2.97V,
disable integrated regulator
-140
-230
—
μA
VLCD=5V, VOH=4.5V,
disable integrated regulator
-300
-500
—
μA
VLCD=3.3V, VOL=0.33V,
disable integrated regulator
250
400
—
μA
VLCD=5V, VOL=0.5V,
disable integrated regulator
500
800
—
μA
VLCD=3.3V, VOH=2.97V,
disable integrated regulator
-140
-230
—
μA
VLCD=5V, VOH=4.5V,
disable integrated regulator
-300
-500
—
μA
VLCD=3.3V, VOL=1V,
when SP1 bit is set to “1”
10
—
—
mA
VLCD=5.0V, VOL=2V,
when SP1 bit is set to “1”
20
—
—
mA
Condition
VDD
3.3V
5.0V
3.3V
5.0V
—
—
—
—
—
—
Note:
1. Please use the integrated regulator when the Regulator output voltage is less than (VLCD - 0.5V).
2. If 8 LEDs turn on at the same time, total current of LED drivers can not be allowed more than 80mA.
Rev. 1.20
6
January 19, 2016
HT16L23
A.C. Characteristics
Unless otherwise specified, VDD =1.8 to 5.5V; VSS = 0V; Ta =-40~85°C
Symbol
Parameter
fLCD1
fLCD2
Test Condition
—
LCD Frame Frequency
—
—
fLCD3
tSR
VDD Slew Rate
tPOF
VDD Off Times
RSTB Input Time
RSTB Pulse Width
tRSOFF
Wait Time for Data
Transfers
Max.
Frame frequency is set
to 64Hz
57.6
64
70.4
Frame frequency is set
to 85.3Hz
76
85.3
94.0
Frame frequency is set
to 128Hz
115.2
128
140.8
Frame frequency is set
to170.6Hz
152
170.6
188.0
Frame frequency is set
to 64Hz
51.2
64
83.0
Frame frequency is set
to 85.3Hz
68
85.3
111
Frame frequency is set
to 128Hz
102.4
128
166
Frame frequency is set
to 170.6Hz
136
170.6
222
Frame frequency is set
to 64Hz
45.0
—
64
Frame frequency is set
to 85.3Hz
59.0
—
85.3
Frame frequency is set
to 128Hz
90.0
—
128
Frame frequency is set
to 170.6Hz
118.0
—
170.6
0.05
—
—
V/ms
VDD drop down to 0.9V
10
—
—
ms
When RSTB signal is externally input
from a microcontroller etc.
250
—
—
ns
—
100
—
ms
400
—
—
ns
1
—
—
ms
Ta=25°C,
VDD=3.3V
Ta=-40~85°C,
VDD=2.5~5.5V
Ta=-40~85°C,
VDD=1.8~2.5V
3.3
3.3
5.0
5.0
3.3
5.0
tRW
Typ.
—
5.0
3.3
tRSON
Min.
Condition
VDD
3.3
5.0
3.3
5.0
R=100kΩ and C=0.1μF
(See application circuit)
When RSTB signal is externally input
from a microcontroller etc.
2-wire I2C or 3-wire SPI interface
Unit
Hz
Hz
Hz
Note: fLCD = 1/tLCD
Rev. 1.20
7
January 19, 2016
HT16L23
A.C. Characteristics – I2C Interface
Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
Symbol
fSCL
Parameter
VDD=1.8V to 5.5V VDD=3.0V to 5.5V
Condition
Clock Frequency
Min.
Max.
Min.
Max.
—
tBUF
Bus Free Time
Time in which the bus must be
free before a new transmission
can start
tHD: STA
Start Condition Hold Time
After this period, the first clock
pulse is generated
Unit
—
100
—
400
kHz
4.7
—
1.3
—
μs
4
—
0.6
—
μs
tLOW
SCL Low Time
—
4.7
—
1.3
—
μs
tHIGH
SCL High Time
—
4
—
0.6
—
μs
tSU: STA
Only relevant for repeated
Start Condition Setup Time
START condition
4.7
—
0.6
—
μs
tHD: DAT
Data Hold Time
—
0
—
0
—
ns
tSU: DAT
Data Setup Time
—
250
—
100
—
ns
tR
SDA and SCL Rise Time
Note
—
1
—
0.3
μs
tF
SDA and SCL Fall Time
Note
—
0.3
—
0.3
μs
tSU: STO
Stop Condition Set-up Time
—
4
—
0.6
—
μs
tAA
Output Valid From Clock
—
—
3.5
—
0.9
μs
tSP
Input Filter Time Constant
(SDA and SCL Pins)
—
20
—
20
ns
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
A.C. Characteristics – SPI Interface
Unless otherwise specified, VDD =1.8 to 5.5V; VSS = 0V; Ta =-40~85°C
Symbol
tSYS
Parameter
Clock Cycle Time
Test Condition
Condition
VDD
Min.
Typ.
Max.
Unit
For write data
250
—
—
ns
For read data
1000
—
—
ns
—
For write data
50
—
—
ns
—
For read data
400
—
—
ns
—
tCW
Clock Pulse Width
tDS
Data Setup Time
—
For write data
50
—
—
ns
tDH
Data Hold Time
—
For write data
50
—
—
ns
tCSW
“H” CSB Pulse Width
—
50
—
—
ns
tCSL
CSB Setup Time
(CSB↓–CLK↑)
—
tCSH
CS Hold Time
(CLK↑–CSB↑)
—
tPD
DATA Output Delay Time (CLK–DIO)
—
Rev. 1.20
—
For write data
50
—
—
ns
For read data
400
—
—
ns
2
—
—
μs
—
—
350
ns
—
CO=15pF
8
tPD=10% to 90%
tPD=90% to 10%
January 19, 2016
HT16L23
Characteristics Curves – fLCD vs. VDD vs. Temperature
LCD frame frequency is set to 85.3Hz
80
100
70
90
60
LCD frame frequency (Hz)
LCD frame frequency (Hz)
LCD frame frequency is set to 64Hz
-40℃
-20℃
50
0℃
40
25℃
30
65℃
85℃
20
10
80
-40℃
70
-20℃
60
0℃
50
25℃
40
65℃
30
85℃
20
10
0
0
1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
1.2 1.5 1.8 2.1 2.4 2.7 3
VDD (V)
LCD frame frequency is set to 170.6Hz
160
200
140
180
LCD frame frequency (Hz)
LCD frame frequency (Hz)
LCD frame frequency is set to 128Hz
120
-40℃
100
-20℃
0℃
80
25℃
60
65℃
85℃
40
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
20
160
140
-40℃
120
-20℃
0℃
100
25℃
80
65℃
60
85℃
40
20
0
0
1.2 1.5 1.8 2.1 2.4 2.7 3
1.2 1.5 1.8 2.1 2.4 2.7 3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
Rev. 1.20
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
VDD (V)
9
January 19, 2016
HT16L23
Functional Description
Display Memory – RAM Structure
The display RAM is static 48×8-bits RAM which
stores the LCD data. Logic “1” in the RAM bit-map
indicates the “on” state of the corresponding LCD
segment; similarly, logic 0 indicates the off state.
Power-On Reset
When the power is applied, the device is initialized
by an internal power-on reset circuit. The status of the
internal circuits after initialization is as follows:
The contents of the RAM data are directly mapped
to the LCD data. The first RAM column corresponds
to the segments operated with respect to COM0. In
multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM
are time-multiplexed with COM1, COM2 and COM3
respectively. The LCD display duty can be 1/4 or 1/8
determined by a Duty bit contained in the Drive Mode
Command. The following diagram is a data transfer
format for I2C or SPI interface.
• All common outputs are set to VLCD.
• All segment outputs are set to VLCD.
• The drive mode 1/4 duty output and 1/3 bias is
selected.
• The system oscillator and the LCD bias generator
are off state.
• LCD display is off state.
• Integrated regulator is disabled.
• The segment/LED shared pin is set as the segment
pin.
MSB
LCD
• Frame frequency is set to 64Hz.
LED
• Blinking function is switched off.
D7
LSB
D6
D5
D4
D3
D2
D1
D0
LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0
LCD Display or LED output data transfer format for
Reset Function
I2C or SPI interface
When the RSTB pin is pulled to a low level, a
reset operation is executed and it will initialize all
functions. The status of the internal circuits after
initialization is as follows:
• All common outputs are set to VLCD.
• All segment outputs are set to VLCD.
• The drive mode 1/4 duty output and 1/3 bias is
selected.
• The system oscillator and the LCD bias generator
are off state.
• LCD display is off state.
• Integrated regulator is disabled.
• The segment/LED shared pin is set as the segment
pin.
• Frame frequency is set to 64Hz.
• Blinking function is switched off.
Rev. 1.20
10
January 19, 2016
HT16L23
1/4 Duty Display Mode
• 52×4 Display Mode
When the SP1 bit is set to “0” and the SP0 bit is set to “0” or “1”, the drive mode is selected as
52 segments by 4 commons. This drive mode is also the default setting after a reset.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
Address
SEG1
SEG0
00H
SEG3
SEG2
01H
SEG5
SEG4
02H
↓
↓
↓
↓
↓
↓
SEG51
↓
↓
↓
↓
SEG50
D7
D6
D5
↓
19H
D4
D3
D2
D1
D0
Data
RAM mapping of 52×4 display mode
• 48×4 Display Mode
When the SP1 bit is set to “1” and the SP0 bit is set to “0”, the drive mode is selected as 48
segments by 4 commons together with 4 LED driving outputs.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
Address
SEG1
SEG0
00H
SEG3
SEG2
01H
SEG5
SEG4
↓
↓
↓
↓
↓
02H
↓
SEG47
↓
↓
↓
↓
SEG46
D7
D6
D5
↓
17H
D4
D3
D2
D1
D0
Data
RAM mapping of 48×4 display mode
• 44×4 Display Mode
When the SP1 bit is set to “1” and the SP0 bit is set to “1”, the drive mode is selected as 44
segments by 4 commons together with 8 LED driving outputs.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
Address
SEG1
SEG0
00H
SEG3
SEG2
01H
SEG5
SEG4
↓
↓
↓
↓
↓
D7
D6
D5
D4
02H
↓
SEG43
↓
↓
↓
↓
↓
D3
D2
D1
D0
Data
SEG42
15H
RAM mapping of 44×4 display mode
1/8 Duty Display Mode
• 48×8 Display Mode
When the SP1 bit is set to “0” and the SP0 bit is set to “0” or “1”, the drive mode is selected as
48 segments by 8 commons.
Output
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Address
SEG4
00H
SEG5
01H
SEG6
↓
02H
↓
↓
↓
↓
↓
↓
↓
↓
↓
D7
D6
D5
D4
D3
D2
D1
D0
Data
SEG51
2FH
RAM mapping of 48×8 display mode
Rev. 1.20
11
January 19, 2016
HT16L23
• 44×8 Display Mode
When the SP1 bit is set to “1” and the SP0 bit is set to “0”, the drive mode is selected as 44
segments by 8 commons together with 4 LED driving outputs.
Output
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Address
SEG4
00H
SEG5
01H
SEG6
↓
02H
↓
↓
↓
↓
↓
↓
↓
↓
SEG47
↓
2BH
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM mapping of 48×8 display mode
• 40×8 Display Mode
When the SP1 bit is set to “1” and the SP0 bit is set to “1”, the drive mode is selected as 40
segments by 8 commons together with 8 LED driving outputs.
Output
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Address
SEG4
00H
SEG5
01H
SEG6
↓
02H
↓
↓
↓
↓
↓
↓
↓
↓
↓
D7
D6
D5
D4
D3
D2
D1
D0
Data
SEG43
27H
RAM mapping of 48×8 display mode
System Oscillator
regulator. The LCD voltage may be temperature
compensated externally through the Voltage supply to
the VLCD pin. The internal regulator can also provide
the LCD operating voltage. Therefore, the full-scale
LCD voltage (VOP) is obtained from (VLCD – VSS) or
(Vreg – VSS).
The timing for the internal logic and the LCD drive
signals are generated by an internal oscillator. The
System Clock frequency (fSYS) determines the LCD
frame frequency. During initial system power on the
System Oscillator will be in the stop state.
Fractional LCD biasing voltages, known as 1/3 or 1/4
bias voltage, are obtained from an internal voltage
divider of four series resistors connected between
VLCD and VSS. The centre resistor can be switched
out of circuits to provide a 1/3 bias voltage level
LCD Bias Generator
The LCD supply power can come from the external
VLCD pin or the internal regulator output voltage
determined using the Internal Voltage Adjustment
(IVA) setting command. The device provides an
external VLCD pin and also integrates an internal
Rev. 1.20
configuration.
12
January 19, 2016
HT16L23
LCD Drive Mode Waveforms
• When the LCD drive mode is selected as 1/4 duty and 1/3 bias, the waveform and LCD display is shown as
follows:
tLCD
VLCD
VLCD
COM0
COM0
State1
State1
(on)
(on)
VLCD- Vop/3
VLCD- Vop/3
LCD segment
LCD segment
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM3
COM3
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Waveforms for 1/4 duty drive mode with1/3 bias (VOP=VLCD−VSS)
Note: tLCD = 1/fLCD
Rev. 1.20
13
January 19, 2016
HT16L23
• When the LCD drive mode is selected as 1/8 duty and 1/4bias, the waveform and LCD display is shown as
follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
State1
State1
(on)
(on)
VLCD- Vop/4
VLCD- Vop/4
COM0 VLCD- 2Vop/4
COM0 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
State2
State2
(off)
(off)
VLCD- Vop/4
VLCD- Vop/4
COM1 VLCD- 2Vop/4
COM1 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
COM2 VLCD- 2Vop/4
COM2 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
COM3 VLCD- 2Vop/4
COM3 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
COM4 VLCD- 2Vop/4
COM4 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
COM5 VLCD- 2Vop/4
COM5 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
COM6 VLCD- 2Vop/4
COM6 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
COM7 VLCD- 2Vop/4
COM7 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n
SEG n
VLCD- 2Vop/4
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+1 VLCD- 2Vop/4
SEG n+1 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+2 VLCD- 2Vop/4
SEG n+2 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+3 VLCD- 2Vop/4
SEG n+3 VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
Waveforms for 1/8 duty drive mode with1/4 bias (VOP=VLCD−VSS)
Note: tLCD = 1/fLCD
Rev. 1.20
14
January 19, 2016
HT16L23
Segment Driver Outputs
Frame Frequency
The LCD drive section includes 52 segment outputs
SEG0~SEG51 or 48 segment outputs SEG4~SEG51
which should be connected directly to the LCD
panel. The segment output signals are generated in
accordance with the multiplexed column signals and
with the data resident in the display latch. The unused
segment outputs should be left open-circuit when less
than 52 or 48 segment outputs are required.
The HT16L23 device provides four frame frequencies
selected with Frame Frequency command known as
64Hz, 85.3Hz, 128Hz and 170.6Hz respectively.
LED Function
The LED pins are NMOS-structured output pins.
The Data for the LED output is contained in the
LED output setting command, starting from the most
significant bit. When a written data bit for a LED pin
is set to 1, the corresponding driving LED lights up
while the LED is switched off when the written data
bit is 0. The LED pins are pin-shared with the LCD
segment pins and can be selected using the SP1 and
SP0 bits in the Drive Mode command.
Column Driver Outputs
The LCD drive section includes 4 column outputs
COM0~COM3 or 8 column outputs COM0~COM7
which should be connected directly to the LCD
panel. The column output signals are generated in
accordance with the selected LCD drive mode. The
unused column outputs should be left open-circuit if
less than 4 or 8 column outputs are required.
I2C Serial Interface
I2C Operation
Address Pointer
The device supports I2C serial interface. The I2C bus
is for bidirectional, two-line communication between
different ICs or modules. The two lines are a serial
data line, SDA, and a serial clock line, SCL. Both
lines are connected to the positive supply via pull-up
resistors with a typical value of 4.7kΩ. When the bus
is free, both lines are high. Devices connected to the
bus must have open-drain or open-collector outputs
to implement a wired-or function. Data transfer is
initiated only when the bus is not busy.
The addressing mechanism for the display RAM is
implemented using the address pointer. This allows
the loading of an individual display data byte, or a
series of display data bytes, into any location of the
display RAM. The sequence commences with the
initialization of the address pointer by the Display
Data Input command.
Blinking Function
The device contains versatile blinking capabilities.
The whole display can be blinked at frequencies
selected by the Blinking Frequency command. The
blinking frequency is a subdivided ratio of the system
frequency. The ratio between the system oscillator
and blinking frequencies depends on the blinking
mode in which the device is operating, as shown in
the following table:
Blinking Mode
Blinking Frequency (Hz)
0
Blink off
1
2
Rev. 1.20
2
1
3
0.5
Data Validity
The data on the SDA line must be stable during the
high period of the serial clock. The high or low state
of the data line can only change when the clock signal
on the SCL line is Low as shown in the diagram.
SDA
SCL
Data line stable;
Data valid
15
Change of data
allowed
January 19, 2016
HT16L23
• The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse so
that it remains stable low during the high period of
this clock pulse.
START and STOP Conditions
• A high to low transition on the SDA line while SCL
is high defines a START condition.
• A low to high transition on the SDA line while SCL
is high defines a STOP condition.
• A master receiver must signal an end of data to the
slave by generating a not-acknowledge, NACK,
bit on the last byte that has been clocked out of
the slave. In this case, the master receiver must
leave the data line high during the 9th pulse to not
acknowledge. The master will generate a STOP or
repeated START condition.
• START and STOP conditions are always generated
by the master. The bus is considered to be busy
after the START condition. The bus is considered
to be free again a certain time after the STOP
condition.
• The bus stays busy if a repeated START (Sr) is
generated instead of a STOP condition. In some
respects, the START(S) and repeated START (Sr)
conditions are functionally identical.
Data Output
by Transmitter
not acknowledge
Data Outptu
by Receiver
acknowledge
SCL From
Master
SDA
SDA
S
STOP condition
Sr
2
7
8
9
ACK
1
2
3-8
9
ACK
8
9
clock pulse for
acknowledgement
• The HT16L23 address bits are “0111110”. When
an address byte is sent, the device compares the
first seven bits after the START condition. If they
match, the device outputs an Acknowledge on the
SDA line.
P
SDA
1
7
Slave Addressing
• The slave address byte is the first byte received
following the START condition form the master
device. The first seven bits of the first byte make
up the slave address. The eighth bit defines a read
or write operation to be performed. When the R/W
bit is “1”, then a read operation is selected. A “0”
selects a write operation.
Byte Format
Every byte put on the SDA line must be 8-bit long.
The number of bytes that can be transmitted per
transfer is unrestricted. Each byte has to be followed
by an acknowledge bit. Data is transferred with the
most significant bit, MSB, first.
S
or
Sr
2
START
condition
P
START condition
SCL
S
SCL
SCL
1
P
or
Sr
Acknowledge
• Each bytes of eight bits is followed by one
acknowledge bit. This Acknowledge bit is a low
level placed on the bus by the receiver. The master
generates an extra acknowledge related clock pulse.
Slave Address
MSB
0
LSB
1
1
1
1
1
0
R/W
• A slave receiver which is addressed must generate
an Acknowledge, ACK, after the reception of each
byte.
Rev. 1.20
16
January 19, 2016
HT16L23
I2C Interface Write Operation
Byte Write Operation
• Single Command Type
A Single Command write operation requires a START condition, a slave address with an R/W bit,
a command byte and a STOP condition for a single command write operation.
Slave Address
S
0
1
1
1
Command byte
1
1
0
0
P
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Write ACK
ACK
1st
I2C Single Command Type Write Operation
• Compound Command Type
A Compound Command write operation requires a START condition, a slave address with
an R/W bit, a command byte, a command setting byte and a STOP condition for a compound
command write operation.
Command byte
Command setting
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Slave Address
S
0
1
1
1
1
1
0
0
Write ACK
ACK
1st
P
ACK
2nd
I2C Compound Command Type Write Operation
• Display RAM Single Data Byte
A display RAM data byte write operation requires a START condition, a slave address with an
R/W bit, a display data input command byte, a valid Register Address byte, a Data byte and a
STOP condition.
Slave Address
S
0
1
1
1
1
Command byte
1
0
0
Write ACK
1
0
0
0
0
1st
0
Register Address byte
0
0
X
ACK
X
A5
A4
A3
2nd
A2
Data byte
A1
A0
D7
ACK
D6
D5
D4
D3
D2
D1
P
D0
ACK
I2C Display RAM Single Data Byte Write Operation
Rev. 1.20
17
January 19, 2016
HT16L23
Display RAM Page Write Operation
After a START condition the slave address with the R/W bit is placed on the bus followed with a display data input
command byte and the specified display RAM Register Address of which the contents are written to the internal
address pointer. The data to be written to the memory will be transmitted next and then the internal address pointer
will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock
pulse. After the internal address point reaches the maximum memory address, the address pointer will be reset to
00H.
Command byte
Slave Address
S
0
1
1
1
1
1
0
0
1
Write
0
0
0
D6
D5
D4
0
0
0
X
X
A5
A4
1st
A3
A2
D2
D1
A0
2nd
ACK
Data byte
D3
A1
ACK
ACK
Data byte
D7
0
Register Address byte
D0
D7
D6
D5
D4
1st data
Data byte
D3
D2
D1
D0
D7
D6
D5
D4
2nd data
D3
D2
D1
Nth data
ACK
ACK
P
D0
ACK
ACK
I C Interface N Bytes Display RAM Data Write Operation
2
Duty
SP1
SP0
Maximum Memory Address
0
X
19H
1/4
1
0
17H
1
1
15H
0
X
2FH
1
0
2BH
1
1
27H
1/8
I2C Interface Display RAM Read Operation
In this mode, the master reads the HT16L23 data after setting the slave address. Following the R/W bit (="0")
is an acknowledge bit, a command byte and the register address byte which is written to the internal address
pointer. After the start address of the Read Operation has been configured, another START condition and the slave
address transferred on the bus followed by the R/W bit (="1"). Then the MSB of the data which was addressed is
transmitted first on the I2C bus. The address pointer is only incremented by 1 after the reception of an acknowledge
clock. That means that if the device is configured to transmit the data at the address of AN+1, the master will read
and acknowledge the transferred new data byte and the address pointer is incremented to AN+2. After the internal
address pointer reaches the maximum memory address, the address pointer will be reset to 00H.
This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
Command byte
Slave Address
S
0
1
1
1
1
1
0
0
1
Write
0
0
0
0
Register Address byte
0
0
0
X
X
A5
A4
A3
A2
A1
P
A0
2nd
1st
ACK
ACK
ACK
0
Slave Address
S
0
1
1
1
1
Data byte
Data byte
1
0
1
Read
D7
D6
D5
D4
D3
D2
D1
D7
D0
D5
D4
D3
Data byte
D2
D1
D0
D7
D6
2nd data
1st data
ACK
D6
ACK
D5
D4
D3
Nth data
ACK
D2
D1
D0
P
NACK
ACK
I2C Interface N Bytes Display RAM Data Read Operation
Rev. 1.20
18
January 19, 2016
HT16L23
SPI Serial Interface
• For read operations, the MCU should assert a high
pulse on the CSB pin to change the data transfer
direction from input mode to output mode on the
DIO pin after sending the command byte and the
setting values. If the MCU sets the CSB signal to a
high level again after receiving the output data, the
data direction on the DIO pin will be changed into
input mode and the read operation will end.
SPI Operation
The device also includes a 3-wire SPI serial interface.
The SPI operations are described as follows:
• The CSB pin is used to activate the data transfer.
When the CSB pin is at a high level, the SPI
operation will be reset and stopped. If the CSB pin
changes state from high to low, data transmission
will start.
• For a read operation, the data is output on the DIO
pin at the CLK falling edge.
• The data is transferred from the MSB of each byte
and is shifted into the shift register during each
CLK rising edge.
• For display RAM data read/write operations using
the SPI interface, the read/write control bit is
contained in the Display Data Input Command.
Refer to the Display Data Input Command
description for more details.
• The input data is automatically latched into the
internal register for each 8-bits of input data after
the CSB signal goes low.
SPI Interface Write Operation
Byte Write Operation
• Single Command Type
A Single Command write operation is activated by the CSB signal going low. The 8-bit command
byte is shifted from the MSB into the shift register at each CLK rising edge.
CSB
CLK
Command byte
DIO
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
SPI Single Command Type Write Operation
• Compound Command Type
For a compound command, an 8-bit command byte is first shifted into the shift register followed
by an 8-bit command setting. Note that the CLK high pulse width, after the command byte has
been shifted in, must remain at this level for at least 2μs after which the command setting data
can be consecutively shifted in.
CSB
2μs(min)
CLK
DIO
Command byte
Command setting
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPI Compound Command Type Write Operation
Rev. 1.20
19
January 19, 2016
HT16L23
• Display RAM Single Data Byte
The display RAM single data write operation consists of a display data input (write) command, a
register address and a write data byte.
CSB
2μs(min)
2μs(min)
CLK
Display Data Input command byte
1
DIO
0
0
0
0
0
0
0
Data byte
Register Address byte
X
X
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SPI Display RAM Single Data Byte Write Operation
Display RAM Page Write Operation
The display RAM Page write operation consists of a display data write command, a register address of which the
contents are written to the internal address pointer followed by N bytes of written data. The data to be written to
the memory will be transmitted next and then the internal address pointer will be automatically incremented by
1 to indicate the next memory address location. After the internal address point reaches the maximum memory
address, the address pointer will be reset to 00H.
CSB
2μs(min)
2μs(min)
CLK
Display Data Input Command byte
DIO
1
0
0
0
0
0
0
2μs(min)
0
X
X
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
2μs(min)
2μs(min)
Data byte
Data byte
Register Address byte
D2
D1
D0
1st data
D7
D6
D5
D4
D3
2nd data
Data byte
D2
D1
D0
D7
3rd
data
Data byte
D0
D7
D6
D5
(N-1)th
data
D4
D3
D2
D1
D0
Nth data
SPI Interface N Bytes Display RAM Data Write Operation
Duty
1/4
1/8
Rev. 1.20
SP1
SP0
Maximum Memory Address
0
X
19H
1
0
17H
1
1
15H
0
X
2FH
1
0
2BH
1
1
27H
20
January 19, 2016
HT16L23
SPI Interface Display RAM Read Operation
In this mode, the master reads the HT16L23 data after sending the Display Data Input command when the CSB
pin changes state from high to low. Following the read/write control bit, which is contained in the Display Data
Input command, is the register address byte which is written to the internal address pointer. After the start address
of the Read Operation has been configured, another CSB high pulse is placed on the bus and then the MSB of the
data which was addressed is transmitted first on the SPI bus. The address pointer is only incremented by 1 after the
reception of each data byte. That means that if the device is configured to transmit the data at the address of AN+1,
the master will read the transferred data byte and the address pointer is incremented to AN+2. After the internal
address pointer reaches the maximum memory address, the address pointer will be reset to 00H.
This cycle of reading consecutive addresses will continue until the master pulls the CSB line to a high level to
terminate the data transfer.
CSB
2μs(min)
2μs(min)
CLK
Display data Input command byte
DIO
1
0
0
0
0
0
0
1
X
X
A5 A4 A3 A2 A1 A0
2μs(min)
Data byte
Data byte
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1st data
2nd data
Register Address byte
2μs(min)
Data byte
Data byte
D7
D0
3rd
data
D7 D6 D5 D4 D3 D2 D1 D0
(N-1)th
data
Nth data
SPI Interface N Bytes Display RAM Data Read Operation
Command Summary
Software Reset Command
This command is used to initialize the HT16L23 device.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
Soft reset command
1st
1
0
1
0
1
0
1
0
—
W
—
Note:
• When this software reset command is executed, all the command registers are initialized to the default values.
• After the reset command is executed, the device will experience an internal initialization for 1ms.
• Normal operation can be executed after the device initialization is complete.
• During the initialization period, no commands can be executed.
• If the programmed command is not defined, the function will not be affected.
The status of the internal circuits after initialization is as follows:
• All segment/common outputs are set to VLCD.
• The drive mode 1/4 duty output and 1/3 bias is selected.
• The system oscillator and the LCD bias generator are in an off state.
• The LCD display is in an off state and the integrated regulator is disabled.
• The segment/LED shared pin is setup as a segment pin.
• The frame frequency is set to 64Hz.
• The blinking function is switched off.
Rev. 1.20
21
January 19, 2016
HT16L23
Drive Mode Command
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
Drive mode setting
command
1st
1
0
0
0
0
0
1
0
—
W
—
Duty, bias and
pin-shared setting
2nd
X
X
SP1
SP0
X
Duty
X
Bias
—
W
00H
Function
Note:
Bit
Duty
Bias
0
1/4duty
1/3bias
1
1/4duty
1/4bias
1
0
1/8duty
1/3bias
1
1
1/8duty
1/4bias
SP1
SP0
0
1
1
Duty
Bias
0
0
Segment/LED Shared Pin Selected
Segment48~51/LED3~0
Segment44~47/LED7~4
X
Set as segment pins
Set as segment pins
0
Set as LED pins
Set as segment pins
1
Set as LED pins
Set as LED pins
• Power on status: The drive mode 1/4 duty output and 1/3 bias is selected and also the segment output pins are
selected.
• If the programmed command is not defined, the function will not be affected.
Display Data Input Command
This command sends data from MCU to the memory MAP of the HT16L23 device.
Function
Byte
Display data input/
output command
1st
Address pointer
2nd
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
1
0
0
0
0
0
0
Note
R/W Def
0
Write operation
W
—
R
—
W
00H
1
0
0
0
0
0
0
1
Read operation for 3-wire
SPI interface used only.
X
X
A5
A4
A3
A2
A1
A0
Display data start
address of memory map
Note:
Duty
1/4
1/8
SP1
SP0
Maximum Memory Address
0
X
19H
1
0
17H
1
1
15H
0
X
2FH
1
0
2BH
1
1
27H
• Power on status: The address is set to 00H.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.20
22
January 19, 2016
HT16L23
System Mode Command
This command controls the internal system oscillator on/off and display on/off.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
System mode
setting command
1st
1
0
0
0
0
1
0
0
System oscillator and
display on/off setting
2nd
X
X
X
X
X
X
S
E
Function
(LSB)
Note
Bit0
R/W
Def
—
W
—
—
W
00H
Note:
Bit
S
E
Internal System Oscillator
LCD Display
0
X
off
off
1
0
on
off
1
1
on
on
• Power on status: Display off and disable the internal system oscillator.
• If the programmed command is not defined, the function will not be affected.
Frame Frequency Command
This command selects the frame frequency.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
Frame frequency
command
1st
1
0
0
0
0
1
1
0
—
W
—
Frame frequency
setting
2nd
X
X
X
X
X
X
F1
F0
—
W
02H
Note:
Bit [1:0]
Frame Frequency
F1, F0
00
85.3Hz
01
170.6Hz
10
64Hz
11
128Hz
• Power on status: Frame frequency is set to 64Hz.
• If the programmed command is not defined, the function will not be affected.
Blinking Frequency Command
This command defines the blinking frequency of the display modes.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
Blinking frequency
command
1st
1
0
0
0
1
0
0
0
—
W
—
Blinking frequency
setting
2nd
X
X
X
X
X
X
BK1
BK0
—
W
00H
Note:
Bit
BK1
BK0
Blinking Frequency
0
0
Blinking off
0
1
2Hz
1
0
1Hz
1
1
0.5Hz
• Power on status: Blinking function is switched off.
• If the programmed command is not defined, the function will not be affected.
Rev. 1.20
23
January 19, 2016
HT16L23
LED Output Command
This command defines the blinking frequency of the display modes.
Function Byte
LED output
command
1st
LED output
data
2nd
(MSB)
Bit6
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
1
1
0
0
—
1
0
0
0
X
X
X
X
R/W Def
LED3 LED2 LED1 LED0 When [SP1:SP0]=10 used
LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 When [SP1:SP0]=11 used
W
—
W
00H
Note:
• The LED registers and latches are cleared after a new configuration is written into the SP1 and SP0 bits in the
driver mode command.
• If the programmed command is not defined, the function will not be affected.
Internal Voltage Adjustment (IVA) Setting Command
The internal voltage (VLCD) adjustment can provide sixteen kinds of regulator voltage adjustment options by
setting the LCD operating voltage adjustment command.
Function
Byte
Internal voltage
adjustment(IVA)
setting
1st
Internal voltage
adjust control
2nd
(MSB)
Bit6 Bit5
Bit7
1
0
X
X
0
X
Bit4
Bit3
0
1
VE
Bit2 Bit1
0
X
V2
(LSB)
Bit0
Note
0
—
1
V1
V0
R/W Def
The “VE” bit is used
to enable or disable
the internal regulator
adjustment for the LCD
voltage.
W
—
W
00H
The V3~V0 bits can be
used to adjust the VLCD
voltage.
Note:
VE
Regulator Adjustment
0
Off–bias voltage is supplied from VLCD pin
1
On–bias voltage is supplied from the internal regulator
V2
V1
V0
Regulator Output Voltage (V)
0
0
0
3.0V
0
0
1
3.2V
0
1
0
3.3V
0
1
1
3.4V
1
0
0
4.4V
1
0
1
4.5V
1
1
0
4.6V
1
1
1
5.0V
• Power on status: Disable the internal regulator.
• When the VLCD voltage is lower than 3.5V, it is recommended to disable the internal regulator so that the VLCD
voltage is directly connected to the internal bias voltage generator.
• Caution: Use the internal regulator when the "Regulator output voltage<VLCD−0.5V"
• If the programmed command is not defined, the function will not be affected.
Rev. 1.20
24
January 19, 2016
HT16L23
Operation Flow Chart
Access procedures are illustrated below using flowcharts.
Initialization
Power On
Set Internal LCD bias and
segment/LED share pin
Set Internal LCD frame frequency
Set LCD blinking frequency
Next processing
Display Data Read/Write (Address Setting)
Start
Address setting
Display RAM data write
Display on and enable internal system clock
Next processing
Rev. 1.20
25
January 19, 2016
HT16L23
Power Supply Sequence
• If the power is individually supplied on the LCD and VDD pins, it is strongly recommended to follow the
Holtek power supply sequence requirement.
• If the power supply sequence requirement is not followed, it may result in malfunction.
Holtek Power Supply Sequence Requirement:
1. Power-on sequence:
Turn on the logic power supply VDD first and then turn on the LCD driver power supply VLCD.
2. Power-off sequence:
Turn off the LCD driver power supply VLCD. First and then turn off the logic power supply VDD.
3. The Holtek Power Supply Sequence Requirement must be followed no matter whether the VLCD voltage is
higher than the VDD voltage.
• When the VLCD voltage is smaller than or is equal to VDD voltage application
Voltage
VDD
VDD
VLCD
VLCD
Time
1µs
1µs
• When the VLCD voltage is greater than VDD voltage application
Voltage
VLCD
VLCD
VDD
VDD
Time
1µs
Rev. 1.20
1µs
26
January 19, 2016
HT16L23
Application Circuit
I2C Interface
• 1/4 Duty, [SP1:SP0]=0x
(1) RSTB pin is connected to a MCU.
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM3
SEG0~51
COM0~COM3
SEG0~51
SDA
HT16L23
IFS
VDD
RSTB
VDD
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM3
SEG0~51
COM0~COM3
SEG0~51
SDA
HT16L23
IFS
VDD
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM3
SEG0~51
COM0~COM3
SEG0~51
SDA
VDD
HT16L23
IFS
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
27
VLCD
0.1uF
VLCD
January 19, 2016
HT16L23
• 1/4 Duty, [SP1:SP0]=10
(1) RSTB pin is connected to a MCU.
VDD
LCD panel
4.7K
COM0~COM3
4.7K
SEG0~47
VLCD
SCL
MCU
COM0~COM3
RLED*4
SEG0~47
SDA
LED1
HT16L23
LED2
IFS
VDD
RSTB
LED*4
LED0
LED3
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
VDD
LCD panel
4.7K
COM0~COM3
4.7K
SEG0~47
VLCD
SCL
MCU
COM0~COM3
SDA
RLED*4
SEG0~47
LED1
HT16L23
LED2
IFS
VDD
LED3
RSTB
0.1uF
LED*4
LED0
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
COM0~COM3
4.7K
VLCD
SCL
MCU
COM0~COM3
SDA
VDD
SEG0~47
SEG0~47
LED0
LED2
LED3
VDD
VSS
0.1uF
VDD
Rev. 1.20
LED*4
LED1
HT16L23
IFS
RSTB
RLED*4
VLCD
0.1uF
VLCD
28
January 19, 2016
HT16L23
• 1/4 duty, [SP1:SP0]=11
(1) RSTB pin is connected to a MCU.
VDD
LCD panel
4.7K
4.7K
COM0~COM3
SEG0~43
COM0~COM3
SEG0~43
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L23
VDD
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
0.1uF
LED7
VLCD
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
VDD
LCD panel
4.7K
4.7K
COM0~COM3
SEG0~43
COM0~COM3
SEG0~43
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L23
VDD
LED4
IFS
LED5
LED6
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
LED7
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
4.7K
COM0~COM3
SEG0~43
COM0~COM3
SEG0~43
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L23
VDD
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
VLCD
LED7
0.1uF
VLCD
29
January 19, 2016
HT16L23
• 1/8 duty, [SP1:SP0]=0x
(1) RSTB pin is connected to a MCU.
LCD panel
CSB
COM0~COM7
SEG0~47
COM0~COM7
SEG4~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM7
SEG0~47
COM0~COM7
SEG4~51
SDA
HT16L23
IFS
VDD
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM7
SEG0~47
COM0~COM7
SEG4~51
SDA
VDD
HT16L23
IFS
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
30
VLCD
0.1uF
VLCD
January 19, 2016
HT16L23
• 1/8 duty, [SP1:SP0]=10
(1) RSTB pin is connected to a MCU.
VDD
LCD panel
4.7K
COM0~COM7
4.7K
SEG0~43
VLCD
SCL
MCU
COM0~COM7
RLED*4
SEG4~47
SDA
LED1
HT16L23
LED2
IFS
VDD
RSTB
LED*4
LED0
LED3
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
VDD
LCD panel
4.7K
COM0~COM7
4.7K
SEG0~43
VLCD
SCL
MCU
COM0~COM7
SDA
RLED*4
SEG4~47
LED1
HT16L23
LED2
IFS
VDD
LED3
RSTB
0.1uF
LED*4
LED0
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
COM0~COM7
4.7K
VLCD
SCL
MCU
COM0~COM7
SDA
VDD
SEG0~43
SEG4~47
LED2
LED3
VDD
VSS
0.1uF
VDD
Rev. 1.20
LED*4
LED1
HT16L23
IFS
RSTB
RLED*4
LED0
VLCD
0.1uF
VLCD
31
January 19, 2016
HT16L23
• 1/8 duty, [SP1:SP0]=11
(1) RSTB pin is connected to a MCU.
VDD
LCD panel
4.7K
COM0~COM7
4.7K
SEG0~39
VLCD
RLED*8
SCL
COM0~COM7
SEG4~43
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L23
VDD
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
0.1uF
LED7
VLCD
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
VDD
LCD panel
4.7K
4.7K
COM0~COM7
SEG0~39
COM0~COM7
SEG4~43
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L23
VDD
LED4
IFS
LED5
LED6
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
LED7
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
4.7K
COM0~COM7
SEG0~39
COM0~COM7
SEG4~43
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L23
VDD
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
VLCD
LED7
0.1uF
VLCD
32
January 19, 2016
HT16L23
SPI Interface
• 1/4 duty, [SP1:SP0]=0x
(1) RSTB pin is connected to a MCU.
LCD panel
CSB
COM0~COM3
SEG0~51
COM0~COM3
SEG0~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
VDD
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
LCD panel
CSB
COM0~COM3
SEG0~51
COM0~COM3
SEG0~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
CSB
COM0~COM3
SEG0~51
COM0~COM3
SEG0~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
33
VLCD
0.1uF
VLCD
January 19, 2016
HT16L23
• 1/4 duty, [SP1:SP0]=10
(1) RSTB pin is connected to a MCU.
LCD panel
COM0~COM3
SEG0~47
VLCD
SCL
COM0~COM3
SEG0~47
RLED*4
CLK
MCU
HT16L23
DIO
LED1
LED2
IFS
RSTB
LED*4
LED0
LED3
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
LCD panel
COM0~COM3
SEG0~47
VLCD
CSB
COM0~COM3
SEG0~47
RLED*4
CLK
MCU
HT16L23
DIO
LED1
LED2
IFS
LED3
RSTB
0.1uF
LED*4
LED0
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
SEG0~47
VLCD
CSB
COM0~COM3
SEG0~47
RLED*4
CLK
MCU
HT16L23
DIO
LED1
LED2
IFS
RSTB
LED3
VDD
VSS
0.1uF
VDD
Rev. 1.20
LED*4
LED0
VLCD
0.1uF
VLCD
34
January 19, 2016
HT16L23
• 1/4 duty, [SP1:SP0]=11
(1) RSTB pin is connected to a MCU.
LCD panel
COM0~COM3
SEG0~43
COM0~COM3
SEG0~43
RLED*8
CSB
LED1
CLK
MCU
LED*8
LED0
LED2
DIO
LED3
HT16L23
LED4
LED5
IFS
LED6
RSTB
VDD
VSS
0.1uF
VLCD
LED7
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
LCD panel
COM0~COM3
SEG0~43
VLCD
RLED*8
CSB
COM0~COM3
LED*8
SEG0~43
LED0
LED1
CLK
LED2
MCU
HT16L23
DIO
LED3
LED4
LED5
IFS
LED6
RSTB
0.1uF
VDD
VSS
LED7
0.1uF
0.1uF
100K
VLCD
VLCD
VDD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
SEG0~43
VLCD
RLED*8
CSB
COM0~COM3
LED*8
SEG0~43
LED0
LED1
CLK
LED2
MCU
HT16L23
DIO
LED3
LED4
LED5
IFS
LED6
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
VLCD
LED7
0.1uF
VLCD
35
January 19, 2016
HT16L23
• 1/8 duty, [SP1:SP0]=0x
(1) RSTB pin is connected to a MCU.
LCD panel
CSB
COM0~COM7
SEG0~47
COM0~COM7
SEG4~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
VDD
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
LCD panel
CSB
COM0~COM7
SEG0~47
COM0~COM7
SEG4~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
CSB
COM0~COM7
SEG0~47
COM0~COM7
SEG4~51
CLK
MCU
HT16L23
DIO
IFS
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
36
VLCD
0.1uF
VLCD
January 19, 2016
HT16L23
• 1/8 duty, [SP1:SP0]=10
(1) RSTB pin is connected to a MCU.
LCD panel
COM0~COM7
SEG0~43
VLCD
SCL
COM0~COM7
SEG4~47
RLED*4
CLK
MCU
HT16L23
DIO
LED1
LED2
IFS
RSTB
LED*4
LED0
LED3
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
LCD panel
COM0~COM7
SEG0~43
VLCD
CSB
COM0~COM7
SEG4~47
RLED*4
CLK
MCU
HT16L23
DIO
LED1
LED2
IFS
LED3
RSTB
0.1uF
LED*4
LED0
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM7
SEG0~43
VLCD
CSB
COM0~COM7
SEG4~47
RLED*4
CLK
MCU
HT16L23
DIO
LED1
LED2
IFS
RSTB
LED3
VDD
VSS
0.1uF
VDD
Rev. 1.20
LED*4
LED0
VLCD
0.1uF
VLCD
37
January 19, 2016
HT16L23
• 1/8 duty, [SP1:SP0]=11
(1) RSTB pin is connected to a MCU.
LCD panel
COM0~COM7
SEG0~39
VLCD
RLED*8
CSB
COM0~COM7
SEG4~43
LED1
CLK
MCU
LED*8
LED0
LED2
DIO
LED3
HT16L23
LED4
LED5
IFS
LED6
RSTB
VDD
VSS
VLCD
0.1uF
LED7
0.1uF
VDD
VLCD
(2) RSTB pin is connected to external resistor and capacitor.
LCD panel
COM0~COM7
SEG0~39
VLCD
RLED*8
CSB
COM0~COM7
LED*8
SEG4~43
LED0
LED1
CLK
LED2
MCU
HT16L23
DIO
LED3
LED4
LED5
IFS
LED6
RSTB
0.1uF
VDD
VSS
LED7
0.1uF
0.1uF
100K
VLCD
VLCD
VDD
(3) Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM7
SEG0~39
VLCD
RLED*8
CSB
COM0~COM7
LED*8
SEG4~43
LED0
LED1
CLK
LED2
MCU
HT16L23
DIO
LED3
LED4
LED5
IFS
LED6
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.20
VLCD
LED7
0.1uF
VLCD
38
January 19, 2016
HT16L23
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package
information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be
transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.20
39
January 19, 2016
HT16L23
64-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.20
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.40 BSC
—
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
40
January 19, 2016
HT16L23
Copyright© 2016 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.20
41
January 19, 2016